JPH08327681A - Noise detection circuit, control method therefor and noise reduction circuit - Google Patents

Abstract

PURPOSE: To measure, correct and reduce the effect of noise generated from a digital circuit on an analog circuit in real time by detecting the noise using a plurality of voltage comparators operating with different phase. CONSTITUTION: A noise detection circuit 1 comprises voltage comparators 2a, 2b which are operated, respectively, by ϕ1, ϕ2 in negative phase and receive an input voltage V1 at the time of auto-zero and a reference voltage V2 at the time of comparison. At first, the comparator 2a measures the voltage difference between V1 and V2 and then the comparator 2b measures the voltage difference with a time lag of one half period behind the comparator 2a before delivering outputs OUT1, OUT2 to a correction amount operating circuit. Consequently, the noise can be measured every one half period at high sampling rate. Based on the magnitude of noise, the correction amount operating circuit operates a correction amount which is then delivered to a correction circuit. The correction circuit weights the correction value depending on the noise detection sensitivity of an analog circuit thus correcting the output voltage therefrom.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for reducing the influence of noise generated by a digital circuit on an analog circuit in a mixed analog / digital integrated circuit.

[0002]

2. Description of the Related Art In a mixed IC in which an analog circuit and a digital circuit are formed on the same substrate, there is a problem that the analog circuit malfunctions due to the influence of noise generated by the operation of the digital circuit driven by a clock or data signal. . In order to solve this problem, first of all, quantitatively grasp the magnitude of the noise generated by the digital circuit and its effect,
Need to find out.

Up to now, a noise measuring method using a voltage comparator has been proposed. This is to change the input signal of the voltage comparator by a small amount and to perform the comparison operation with the reference voltage as the standard, measure the frequency of appearance of the high level of the output of the comparator, and synchronize with the digital circuit operation. This is a method of measuring the waveform of noise by performing equivalent sampling. Such a measuring method is described in JP-A-6-53415.

[0004]

In the conventional noise measuring method using the voltage comparator, the operating clock of the voltage comparator is operated in synchronization with the clock of the digital circuit that generates noise, and the clock of the digital circuit is operated. It is measured by driving by sequentially shifting from the clock. Each sampling value is measured by equivalent sampling by changing the input voltage of the voltage comparator to obtain the output voltage frequency distribution. Therefore, according to the conventional method, it is possible to know the temporal change of the influence of noise, but it takes a long time to measure, and it is possible to measure only when synchronized with a digital clock.

As described above, it is difficult to quantitatively evaluate the influence of noise transmitted from the substrate in the analog / digital mixed integrated circuit in real time.

An object of the present invention is to solve the above problems.

It is another object of the present invention to provide a circuit or method capable of establishing a real time measuring means and reducing noise.

[0008]

According to a typical embodiment of the present invention, a noise reduction means for solving the above problems comprises at least one voltage comparator which operates in different phases. It is composed of one noise detecting means and a correcting means of the noise detected by this means.

[0009]

In the noise reducing means according to the typical embodiment of the present invention, the influence of the noise generated by the digital circuit on the analog circuit can be measured in real time by using the plurality of voltage comparators. Since the voltage comparator can amplify a weak signal in a wide band, it can measure a temporal change in noise with respect to an analog circuit. further,
This method can reduce the influence of noise.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

First, a configuration example and a basic operation of a voltage comparator used for noise detection will be described with reference to FIG.

The voltage comparator 2 is a circuit for comparing the voltage values of the input voltage V1 input from the first input terminal and the reference voltage V2 input from the second input terminal. This circuit operates according to the timing chart of FIG. First,
When the switch 5 is in the ON state, the amplifier circuit 6 is in the auto-zero state and V1 is input. Next, when the switch 5 is in the off state, the amplifier circuit 6 is in the comparison state and V2
Is entered. The difference between V1 and V2 is amplified to Vou
t becomes, and Vout, that is, the comparison result is passed through the latch circuit 7 to a high / low level, that is, O as a digital value.
It is output from UT1. Here, the influence of noise is great at the timing T1 at which the control clock φ1 of the auto-zero switch 5 switches from a high level to a low level and at the final comparison timing T2, and the noise at these timings T1 and T2 is the voltage comparator. The comparison result of 2 is affected and held in the latch circuit 7.

Here, the gain of the amplifier circuit 5 is G, the noise transfer coefficient at the time of auto zero, a and b at the time of comparison, and the times T1 and T2.
Assuming that the influence of noise in ΔV (1) and ΔV (2) in FIG.

Vout = G {(V1-aΔV (1))-(V2-bΔV (2))} (1) If V1 = V2, Vout = G {-aΔV ( 1) + bΔV (2)} (2) holds, and the effects of noise at T1 and T2 are combined and output as a noise component in the voltage comparator.

A first embodiment of the present invention based on the above measuring method will be described with reference to FIG. In this embodiment, the noise detection circuit 1 is composed of voltage comparators 2a and 2b. The input voltages V1 and V2 are both voltage comparators 2a and 2a.
The noise detection circuit 1 outputs the comparison results OUT1 and OUT2.

The operation of this embodiment will be described with reference to the timing chart shown in FIG. The voltage comparator 2a and the voltage comparator 2b operate in opposite phases by φ1 and φ2, and both V1 is input during auto-zero and V2 is input during comparison. FIG.
Shows a single operation of the noise detection circuit 1. First, the voltage comparator 2a measures the difference voltage between V1 and V2 captured at the timing of T1 and T2, and outputs it as OUT1. Similarly, the voltage comparator 2b measures the difference voltage between V1 and V2, which is taken in at the timing of T2 and T3 with a half cycle delay from the voltage comparator 2a, and outputs it as OUT2. By thus configuring the noise detection circuit 1 with the two voltage comparators, it is possible to detect noise for each half cycle.

Next, this operation will be described using the pseudo noise waveform shown in FIG. Here, p to z represent sampling values of the noise waveform generated by the digital circuit operation. The noise generated by the operation of the digital circuit is considered to be a high-frequency ringing waveform that occurs at the rising and falling edges of the clock for driving the digital circuit and has peaking immediately after the change. When noise is detected by one voltage comparator, the noise is φ as shown in (1) of FIG.
At the time of comparison when 1 becomes low level, a difference voltage, for example, -a
It is measured as p + bq. On the other hand, according to the first embodiment of the present invention, by operating the two voltage comparators with a half-cycle shift, as shown in (2), noise delayed by a half cycle from φ1 at the timing of φ2, for example, -Aq + b
r can also be measured. As a result, it becomes possible to measure noise at twice the sampling rate as compared with the case of using one voltage comparator.

Next, a second embodiment of the present invention relating to a method of converting a measurement result into a value corresponding to a noise sampling value will be described with reference to FIG. In this embodiment, the outputs OUT1 and OUT2 of the noise detection circuit 1 are added by the cumulative addition circuit 10 and output. By sequentially adding the outputs of the voltage comparator 2a and the voltage comparator 2b, the sampling value becomes the initial value -ap and the final value bz, and (ab) times the intermediate sampling value as shown in (4). It becomes the sum. If the noise transfer coefficients a and b are equal, the noise sampling value can be obtained as a change amount from the initial value. The present embodiment can also be realized by the circuit shown in FIG. In FIG. 7, after the outputs Vout1 and Vout2 of the voltage comparators 2a and 2b are added by the cumulative addition circuit 10, the latch circuit sets the digital level and holds it. The cumulative addition circuit 10 can be composed of, for example, a switched capacitor circuit. According to this circuit configuration, one latch circuit can be configured for two voltage comparators.

However, the noise transfer coefficients at the time of auto-zero and at the time of comparison are generally not equal, and it is difficult to make them match. Here, the noise transfer coefficient at the time of auto-zero has a wider band than that at the time of comparison and is excellent for detecting high-frequency noise. Therefore, it is effective to obtain a sampling value of noise by selectively detecting noise at the time of auto-zero. A third embodiment of the present invention relating to this method will be described with reference to FIG.

FIG. 8 shows the configuration of the voltage comparator 2 for detecting noise. In the present embodiment, the capacitance C1 is connected to the input of the amplifier circuit via the switch 8 to the ground and the output of the amplifier is connected to the capacitance C2 to the ground via the switch 9. The switches 8 and 9 are controlled so as to be in an off state when the comparator is in auto-zero and in an on state when comparing. By connecting the capacitors C1 and C2 to the ground at the time of comparison, it is possible to reduce the influence of high frequency noise measured at the time of comparison. As a result, the output of the noise detection circuit is as shown in (3) of FIG.
It becomes possible to detect without being affected by the noise at the time of comparison, and the sampling value of the noise at the time of auto-zero can be selectively obtained. Although FIG. 8 shows the case where the two capacitors C1 and C2 are connected, the influence of the high frequency noise measured at the time of comparison can be reduced by using only C1 or C2. Also,
In the present embodiment, the case where the switch 8 or the switch 9 is in the off state at the time of auto zero and the on state at the time of comparison has been described. It is also possible to reduce the influence of the generated high frequency noise and detect the noise at the time of comparison. Furthermore, C1 and C2 may be realized by a mirror capacitor combined with an amplifier circuit. In this case, since it is possible to create a larger capacitance value, the effect of reducing the influence of high frequency noise becomes greater.

In the first, second, and third embodiments, the case where the noise detection circuit is composed of two voltage comparators having opposite phases is shown. However, as shown in (2) of FIG. By operating the voltage comparators out of phase,
It is obvious that the noise waveform can be measured at a high sampling rate.

As described above, in the above embodiment, the noise detection method when one noise detection circuit 1 is used is Vout1,
It has been described using Vout2. Here, the outputs OUT1 and OUT2 of the voltage comparator are digital values. For this reason,
Only one noise detection circuit can determine whether or not there is an influence of noise. Therefore, in order to obtain the magnitude of the input noise, a fourth embodiment of the present invention relating to a noise reduction circuit composed of a plurality of noise detection circuits will be described with reference to FIG.

In this embodiment, the noise reduction circuit 11 is
It is composed of four noise detection circuits 1 and a correction amount calculation circuit 12. The noise detection circuit 1 has a reference voltage V2 and an input voltage V2.
1 (1) to V1 (4) are input. Where V1 (1) to V1
(4) and V2 are set apart from each other by a potential difference ΔV. The outputs O11 to O42 of the noise detection circuit 1 are input to the correction amount calculation circuit 12. The correction amount calculation circuit 12 calculates a correction amount for reducing the influence of noise from the detected noise level. The operation of this circuit will be described with reference to FIG. When there is no noise, the output of the noise detection circuit is V1 (1) whose input voltage is higher than V2 and V1 (2) whose input voltage is lower than V2 as shown in (1) of FIG.
(3) and V1 (4) indicate low level. Assuming that the noise voltage Vn is equivalently input to V2, the output level of V1 (3) changes from low level to high level, as shown in (2) of FIG. This output result is Δ
It indicates that noise larger than V is equivalently input to V2. Therefore, it is possible to reduce the influence of noise by correcting the output result by −ΔV. FIG. 11 shows the correction amount for the output level. By monitoring the output level of the comparator, the correction amount for the input noise can be obtained as shown in (1) of FIG. As a result, the influence of noise can be reduced. In addition, it is not necessary that the step size of the input voltage be all equal.
It is also possible to set different values as shown in FIG.
In this case, as shown in FIG. 11B, the correction amount can be changed according to the set value of the input voltage. In addition,
In the present embodiment, the case where the noise reduction circuit is composed of four noise detection circuits has been shown, but it is clear that noise can be detected with higher resolution by increasing the number of noise detection circuits and setting the potential difference ΔV small. Is.

Next, a fifth embodiment of the present invention relating to a method of reducing the influence of noise in an actual analog / digital mixed integrated circuit will be described with reference to FIG. In the integrated circuit 20, a circuit 21 that is affected by noise and a circuit 23 that generates noise are formed together with the noise detection circuit 1 on the same IC substrate. The circuit 23 that generates noise is generally a digital circuit that handles high-level and low-level signals, and the circuit 21 that is affected by noise is an analog circuit that generally handles weak analog signals. The correction amount calculation circuit 12 determines the correction amount based on the magnitude of the noise detected by the noise detection circuit 1. In the correction circuit 22, the correction amount is re-determined by weighting according to the noise detection sensitivity of the analog circuit, and the output voltage of the analog circuit is corrected. In general, the correction circuit 2
By performing the subtraction process in 2, it is possible to reduce the influence of noise from the calculation result of the analog circuit.

Here, the magnitude of noise generated by the digital circuit changes depending on the scale of the digital circuit and the number of synchronously operating gates. Therefore, the input voltage V1 (1) to V1 (n)
It is effective to change the value of according to the magnitude of noise generated by the digital circuit. Therefore, the input voltage control circuit 14 is provided inside or outside the integrated circuit 20 and the magnitude of the input voltage is controlled to correct the analog circuit output according to the magnitude of noise generated by the digital circuit. You can The input voltage control circuit 14 responds to a large noise by controlling V1 (n) to be small when the outputs of the correction amount calculation circuit 12 are all high level and to set V1 (1) to be large when all the outputs are low level. it can. Further, by controlling the voltages V1 (2) to V1 (n-1), the transition point due to noise can be finely determined. By this method, it is possible to measure the influence of noise with higher resolution, and thus it is possible to reduce noise more accurately. The input voltage may be controlled by feedback at any time during circuit operation, or the noise-generating circuit may be activated before the operation of the circuit that is actually affected by noise. Measure the size of
When the circuit is affected by noise, the input voltage may be set to a constant value for operation.

It is also possible to operate the noise detection circuit in synchronization with the digital circuit. By performing the synchronous operation, equivalent sampling can be performed to investigate the influence of noise that occurs periodically. A sixth embodiment of the present invention relating to a method of reducing the influence of noise in an analog / digital mixed integrated circuit for this purpose will be described with reference to FIG. In this embodiment, the noise detection circuit 1 operates in synchronization with the clock of the circuit 23 that generates noise by the clock generation / adjustment circuit 15. Further, the operation clock of the noise detection circuit 1 is set to a long or short cycle with respect to the clock of the circuit 23 that generates noise for a minute time Δt. As a result, the influence of noise can be sampled at intervals of Δt. The circuit 22 that is affected by noise
By operating the circuit 23 that generates noise to measure the influence of noise before the operation of, the influence of high frequency noise can be grasped in advance. According to the present embodiment, the influence of noise can be measured with high time resolution, so that it is extremely effective in reducing noise in a wideband analog circuit.

Next, a seventh embodiment of the present invention relating to a method of correcting the effect of noise when the circuit affected by noise is an A / D converter will be described with reference to FIG. In this embodiment, the A / D converter 24 operates in synchronization with the noise detection circuit 1. It operates according to the clock with the same cycle as the noise detection circuit, and after auto-zero, compares and determines the voltage level. Operation clock of A / D converter 24 and noise detection circuit 1
As a result of matching the operation clocks of the
Since the D converter detects noise at almost the same timing, the noise detection circuit causes the A of high frequency noise to be detected.
The influence on the / D converter can be accurately grasped.
When the noise detection circuit 1 including two voltage comparators as shown in FIG. 3 is used, the influences of the A / D converter 24 during auto-zero and during comparison can be measured separately. Therefore, it is possible to perform correction by applying a weight corresponding to the noise detection sensitivity in each mode of the A / D converter to the correction amount at the time of auto zero and comparison. As a result, the influence of noise can be reduced more accurately. Here, when the influence of noise is large and it is difficult to correct the A / D converter, it is possible to specify to stop selecting the converted output data at the sampling point. in this case,
By holding the digital conversion value of one clock before as data, control such as interpolating and outputting the digital value at the sampling point can be easily performed.

Further, an eighth embodiment of the present invention relating to the method of determining the weighted coefficient in the above embodiment will be described with reference to FIG. Circuit 21 and A / D affected by noise
The weighted coefficient for the converter 24 is given to the integrated circuit board 30 by using a known signal as substrate noise, and its influence is measured by the circuit 21, the A / D converter 24, and the noise detection circuit 1 which are affected by noise. , It can be determined from the ratio of their noise transfer amounts. As a signal input means, as shown in FIG. 16, a square wave is input to the capacitive coupling section 31 of the integrated circuit board 30 to measure the response characteristic to a high frequency signal,
This can be realized by inputting a sine wave to the resistance coupling section 32, measuring frequency characteristics, and examining response characteristics. Here, the signal generation circuit 33 that generates a square wave, a sine wave, or the like input to the capacitive coupling unit 31 or the resistance coupling unit 32 may be formed on the same substrate or outside the integrated circuit.

The voltage comparator in the above embodiment is composed of one amplifier circuit and a latch circuit. However, even if an amplifier circuit is further provided in the preceding stage of the latch circuit in order to improve the resolution, there is no problem. Absent.

[0030]

Since the influence of the noise generated by the digital circuit on the analog circuit can be measured in real time, the influence of the noise can be known and its correction or reduction can be performed.
It is extremely effective in constructing an analog / digital mixed integrated circuit.

[0031]

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a voltage comparator for detecting noise.

FIG. 2 illustrates an operation timing of a voltage comparator.

FIG. 3 is a diagram for explaining the first embodiment of the present invention.

FIG. 4 is a diagram for explaining the operation timing of the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a noise measuring method according to the present invention.

FIG. 6 is a diagram illustrating a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a second embodiment of the present invention.

FIG. 8 is a diagram illustrating a third embodiment of the present invention.

FIG. 9 is a diagram for explaining the fourth embodiment of the present invention.

FIG. 10 is a diagram for explaining the operation of the fourth embodiment of the present invention.

FIG. 11 is a diagram for explaining the operation of the fourth embodiment of the present invention.

FIG. 12 is a diagram for explaining the fourth embodiment of the present invention.

FIG. 13 is a diagram for explaining the fifth embodiment of the present invention.

FIG. 14 is a diagram for explaining the sixth embodiment of the present invention.

FIG. 15 is a diagram illustrating a seventh embodiment of the present invention.

FIG. 16 is a diagram for explaining the eighth embodiment of the present invention.

[Explanation of symbols]

1 ... Noise detection circuit, 2 ... Voltage comparator, 3, 4, 5 ... Switch, 6 ... Amplification circuit, 7 ... Latch circuit, 8, 9 ... Switch, 10 ... Addition circuit, 11 ... Noise reduction circuit, 12 ... Correction Quantity calculation circuit, 13 ... Clock generation circuit, 14 ... Input voltage control circuit, 15 ... Clock generation / control circuit, 20 ... Integrated circuit, 21 ... Circuit affected by noise, 22 ... Correction circuit, 23 ... Generates noise Circuit, 24 ... A / D converter,
25 ... A / D converter correction circuit, 30 ... Integrated circuit board, 3
DESCRIPTION OF SYMBOLS 1 ... Capacitive coupling part, 32 ... Resistance coupling part, 33 ... Signal generating circuit.

Claims (20)

[Claims] 1. A noise detection circuit of an integrated circuit including at least two voltage comparators, means for operating a first voltage comparator and a second voltage comparator in different phases, and a first input during auto-zero operation. A noise detecting circuit having means for inputting a second input voltage to a voltage comparator during a comparison operation. 2. A means for inputting a first input voltage to the voltage comparator during the auto-zero operation and a second input voltage during the comparison operation, and a capacitor, and at least one first voltage comparator.
2. The noise detection circuit according to claim 1, further comprising: an amplifier circuit for amplifying a difference voltage between the input voltage and the second input voltage, and means for holding the amplified signal. 3. The noise detection circuit according to claim 2, wherein the voltage comparator comprises means for connecting a capacitance between the input section of the first amplifier circuit and the ground. 4. The noise detection circuit according to claim 2, wherein the voltage comparator comprises means for connecting a capacitance between the output section of the first amplifier circuit and the ground. 5. The voltage comparator of the noise detecting circuit according to claim 2, wherein the capacitance of the voltage comparator is compared between the input section and the output section of the first amplifying circuit, or at least one of these and the ground. A method of controlling a noise detection circuit, characterized in that the noise detection circuit is connected at times. 6. The voltage comparator of the noise detecting circuit according to claim 2, wherein a capacitance is provided between the input section and the output section of the first amplifying circuit, or at least one of these and the ground, and the zero of the voltage comparator. A method of controlling a noise detection circuit, characterized in that the noise detection circuit is connected at times. 7. The noise detection circuit according to claim 1,
A noise detection circuit having means for sequentially adding the output of the amplifier circuit of the first voltage comparator and output of the amplifier circuit of the second voltage comparator and means for holding the added signal. . 8. The noise detection circuit according to claim 1,
A noise detection circuit comprising means for sequentially adding the output of the first voltage comparator and the output of the second voltage comparator. 9. A noise reduction of an integrated circuit, comprising at least two noise detection circuits according to claim 1, 2, 3, 4, 7, and 8, and a correction amount calculation means of detected noise. circuit. 10. The noise reduction circuit for an integrated circuit according to claim 7, wherein the second input signals of the voltage comparators constituting the first and second noise detection circuits are all equal, and the first noise The first input signal of the voltage comparator forming the detection circuit is larger than the second input signal, and the first input signal of the input signal of the voltage comparator forming the second noise detection circuit is the second input signal. A noise reduction circuit characterized in that a small signal is input to the input signal of. 11. A noise reduction circuit comprising the noise detection circuit of the noise reduction circuit according to any one of claims 9 and 10 with one voltage comparator according to any one of claims 2, 3, and 4. 12. The noise reduction circuit for an integrated circuit according to claim 9, 10, or 11, wherein the voltage value of the first input signal of the voltage comparator constituting the noise detection circuit is determined according to the magnitude of noise. A noise reduction circuit having means for controlling. 13. An integrated circuit in which a circuit operating at least one clock and a noise reducing circuit according to claim 9, 10, 11, 12 are created, wherein the clock of the noise reducing device is operated by the clock. And a means for holding the output of the noise reduction circuit at each time. 14. An integrated circuit in which a circuit that operates with at least one clock and a noise reduction circuit according to any one of claims 9, 10, 11, 12, and 13 are created, and the output of the correction amount calculation circuit of the noise reduction circuit is changed. An integrated circuit comprising means for performing correction by applying a weight according to the noise detection sensitivity of the circuit affected by the noise. 15. A circuit operated by at least one clock, an analog / digital converter, and
In the integrated circuit in which the noise reduction circuit described in 0, 11, 12, and 13 is created, a clock generation / adjustment unit for synchronizing the clocks of the analog / digital converter and the noise detection circuit is provided, and the noise reduction is performed. An integrated circuit comprising means for performing correction by applying a weight corresponding to the noise detection sensitivity of the analog / digital converter from the output of the correction amount calculation circuit of the circuit. 16. The correction amount calculation circuit according to claim 15, wherein correction is performed by weighting according to noise detection sensitivity at the time of auto zero of the analog / digital converter and comparison. A noise reduction method of the noise reduction circuit according to any one of 10, 11, and 12. 17. The correction amount calculation circuit according to claim 15, wherein when the influence of noise greatly exceeds the correction range, interpolation is performed with the previous sampling value. 16. A noise reduction method for a noise reduction circuit according to 16, 17. 18. An integrated circuit in which the noise reduction circuit according to any one of claims 9, 10, 11 and 12 is prepared, having a capacitive junction portion for inputting pseudo noise. 15. The integrated circuit according to 15 above. 19. An integrated circuit in which the noise reduction circuit according to any one of claims 9, 10, 11 and 12 is formed, having a resistance junction for inputting pseudo noise. 15. The integrated circuit according to 15, 18. 20. A noise transfer coefficient of a noise detection circuit and a circuit affected by noise, which receives pseudo noise from a capacitance junction and a resistance junction in the integrated circuit according to claim 18 or 19 or one of them. A noise reduction method for a noise reduction circuit, characterized in that the weight of the noise correction amount is obtained in advance.