JPH08181221A - Semiconductor integrated circuit device and manufacture - Google Patents

Abstract

PURPOSE: To provide a semiconductor integrated circuit device capable of being supplied with the substrate potential of a MOS transistor without sacrificing an integration degree and capable of being manufactured by a simplified process and the manufacture method. CONSTITUTION: In a semiconductor integrated circuit device, which has a MOS transistor with source regions 3A, 4A and drain regions 3B, 4B formed in a transistor forming region partitioned by field insulating films 5 selectively formed to the main surface of a semiconductor substrate and to which the substrate potential of the MOS transistor is applied from the main surface side of the semiconductor substrate, contact holes 9A deeper than the source regions 3A, 4A are formed to boundary sections between the source regions 3A, 4A and the field insulating films 5. Substrate sections 2, 1A under the source regions 3A, 4A are supplied with power-supply potential as substrate potential through conductors 13 filled with the contact holes 9A while the source regions 3A, 4A are supplied with power-supply potential as source potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof, and more particularly to a structure for applying a bulk potential, that is, a substrate potential of an insulated gate field effect transistor (hereinafter referred to as a MOS transistor), and a manufacturing method thereof. .

[0002]

2. Description of the Related Art In order to form a semiconductor integrated circuit by CMOS, a deep junction region (hereinafter referred to as a well) of a second conductivity type which is a conductivity type opposite to the first conductivity type is formed on a silicon substrate of the first conductivity type. The first conductivity type channel MOS transistor is formed in the well, and the first outside of the well is formed.
MO of the second conductivity type channel is formed in the conductivity type silicon substrate region.
Form an S-transistor. The well and the silicon substrate region need to be fixed to the power supply potential in order to give the substrate potential of each MOS transistor. In this way, fixing the power supply potential in order to apply the substrate potential is the same in the case of a MOS transistor not having a CMOS structure.

FIG. 6 is a sectional view showing a conventional CMOS. An N-type well 2 is formed on a P-type silicon substrate 1, and a silicon oxide film that defines a transistor formation region on the main surface of the substrate, that is, a field insulating film 5 is selectively thermally oxidized (usually called LOCOS method). It is formed by.

The P-channel MOS transistor has a P-type drain region 41 formed in the N-well (N-type region) 2,
The gate insulating film 11 having a P-type source region 42 and an N ⁺ -type contact region 43 and made of a silicon oxide film on the channel region between the P-type source and drain regions 42 and 41.
The polysilicon gate electrode 8 covered with the thermally-oxidized silicon film 12 is formed through.

The N-channel MOS transistor has an N-type drain region 51, an N-type source region 52, and a P ⁺ -type contact region 53 formed in the P-type region 1A of the silicon substrate 1.
And the polysilicon gate electrode 8 covered with the thermal oxide silicon film 12 is formed on the channel region between the N-type source and drain regions 52 and 51 via the gate insulating film 11.

Then, the whole is covered with an interlayer insulating film 6 such as a silicon oxide film, contact holes 37 reaching each region are formed in the interlayer insulating film 6, and through the contact holes 37,
The P type source region 42 and the N ⁺ type contact region 43 of the P channel MOS transistor are commonly connected by the electrode wiring layer 34, and the N type source region 52 and the P ⁺ type contact region 53 of the N channel MOS transistor are connected to the electrode wiring layer. Three
5, the P-type drain region 41 of the P-channel MOS transistor and the N-type drain region 51 of the N-channel MOS transistor are also commonly connected by the electrode wiring layer 36.

Since the electrode wiring layer 34 is connected to the power source potential on the high potential side, for example, the positive potential V _DD line, the positive potential V _DD is applied to the N well 2 through the N ⁺ type contact region 43, and the P channel MOS transistor is formed. The substrate potential of is fixed to this power supply potential.

Since the electrode wiring layer 35 is connected to the power source potential on the low potential side, for example, the negative potential V _SS line or the ground line, P ⁺ is formed in the P type region 1A of the silicon substrate 1.
Negative potential _VDD or ground potential is applied through the mold contact region 53, and the substrate potential of the N-channel MOS transistor is fixed to this power supply potential.

The polysilicon gate electrodes 8 of both MOS transistors are commonly connected to receive an input signal, and the power supply wiring layer 36 is connected to an output node to output an output signal.

However, the above CMOS structure requires the N ⁺ type contact region 43 for applying the substrate potential to the P channel MOS transistor, and this region 43 is separated with the P type source region 42 and the field insulating film 5 interposed therebetween. Similarly, a P ⁺ type contact region 53 for applying a substrate potential to the N channel MOS transistor is required, and this region 53 also has an N type source region 52 and a field insulating film 5.
Since they are separated by sandwiching them, there is a problem in improving the degree of integration.

For this reason, a CMOS as shown in FIG.
For example, it is disclosed in JP-A-61-8969.
In FIG. 7, the same or similar parts as in FIG. 6 are designated by the same reference numerals.

In the CMOS of FIG. 7, the N well 2 is penetrated through the P type source region 42 of the P channel MOS transistor.
A contact hole 68 that penetrates inside the
A contact hole 68 penetrating the N-type source region 52 of the channel MOS transistor and penetrating into the P-type region 1A of the silicon substrate 1 is formed, and the electrode wiring layers 34 and 35 are formed.
Are formed by filling the contact holes 68, 68, respectively.

In this way, the respective substrate potentials can be supplied to the inside of the N well and the inside of the P type region 1A through the electrode wiring layer filled in the contact hole 68,
Since the N ⁺ type contact region 43 and the P ⁺ type contact region 53 of FIG. 6 can be omitted, the degree of integration can be improved.

Next, the conventional manufacturing method of FIG. 7 will be described with reference to FIG.

First, in FIG. 8A, an N well 2 is formed in a P type silicon substrate 1 and a field insulating film 5 is formed by a selective oxidation method to define a transistor forming region.
Here, it is also possible to form a channel stopper region below the field insulating film 5 to prevent the generation of a parasitic channel. Then, a gate insulating film 11 and a polysilicon gate electrode 8 are formed, and the surface of the polysilicon gate electrode 8 is covered with a silicon oxide film 12 formed by thermal oxidation. Then, using the polysilicon gate electrode 8 and the field insulating film 5 as a mask, a P channel M is formed in the N well 2.
The P-type drain region 41 and the P-type source region 42 of the OS transistor are formed, and the P-type region 1A of the silicon substrate 1 is formed.
An N-type drain region 51 and an N-type source region 52 of the N-channel MOS transistor are formed therein.

Next, in FIG. 8B, an interlayer insulating film 6 made of a silicon oxide film is formed on the entire surface, and openings 82A, 82A on both source regions 42, 52 and on both drain regions 41, 51 are formed thereon. First photoresist pattern 81 having openings 82B and 82B is formed.

Next, in FIG. 8C, the interlayer insulating film 6 is selectively removed by etching using the first photoresist pattern 81 as a mask, and the surface of both source regions 42 and 52 under the openings 82A and 82A is removed. The upper portions 68 ', 68' of the reaching contact holes are formed, and the openings 82B, 82B are formed.
Contact holes 37, 37 reaching the surfaces of the lower drain regions 41, 51 are formed, respectively.

Next, in FIG. 8D, after removing the first photoresist pattern 81, a second photoresist pattern 91 is newly formed. The second photoresist pattern 91 fills the contact holes 37, 37 formed in the interlayer insulating film 6, but the openings 92A, 92A are provided on the upper portions 68 ', 68' of the contact holes.

Next, in FIG. 8E, the silicon substrate is selectively removed by etching using the second photoresist pattern 91 as a mask. Thereby, the P-type source region 4
Contact hole 68 penetrating 2 to reach the inside of the N well
A contact hole 68 penetrating the N type source region 52 and reaching the inside of the P type region 1A of the silicon substrate 1 is formed.

Thereafter, aluminum is deposited and patterned to form an electrode wiring layer 36 connected to both drain regions 41 and 51 through both contact holes 37, and an electrode connected to P type source region 42 and N well 2 through contact hole 68. Electrode wiring layers 35 connected to the N-type source region 52 and the P-type region 1A of the silicon substrate 1 through the wiring layer 34 and the contact holes 68 are formed.

[0021]

In the prior art shown in FIG. 6, as described above, the presence of the N ⁺ type contact region 43 and the P ⁺ type contact region 53 makes it possible to obtain a highly integrated semiconductor integrated circuit device. It will be difficult.

On the other hand, in the prior art shown in FIG. 7, in order to form the contact holes 68 penetrating the central portions of the source regions 42 and 52, the area of the source regions 42 and 52 must be reduced to a certain value. I can't. Therefore, this point becomes a constraint for high integration.

Further, in the structure of FIG. 7, as described in the manufacturing method of FIG. 8, when the contact holes 68, 68 penetrating the source regions and reaching the inside of the substrate are formed,
A second photoresist pattern 91 is newly formed in addition to the first photoresist pattern 81 having the contact holes 68 'and 37 formed in the interlayer insulating film 6, and the second photoresist pattern 91 is used to form the interlayer insulating film. The drain region 4 by filling the contact holes 37, 37 formed in
1,51 must be protected.

As described above, the PR process of the photoresist pattern is required twice to form the contact hole, which complicates the manufacturing process, resulting in an expensive semiconductor integrated circuit device.

The disadvantages of the prior art shown in FIGS. 6 to 8 are as follows.
The same applies when a refractory silicide film is formed on the surface of the source and drain regions to reduce the resistance.
The same applies to the case of using only N-channel MOS transistors or P-channel MOS transistors instead of the MOS structure.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit device capable of supplying the substrate potential of a MOS transistor without sacrificing the degree of integration and capable of being manufactured by a simplified process, and its manufacture. Is to provide a method.

[0027]

A feature of the present invention is that a source region and a drain region are formed in a transistor formation region partitioned by a field insulating film selectively provided on a main surface of a semiconductor substrate. A MOS transistor having a gate electrode formed on the channel region between the source region and the drain region via a gate insulating film is provided, and the substrate potential of the MOS transistor is set to the main surface side of the semiconductor substrate. In the semiconductor integrated circuit device applied from above, a contact hole deeper than the source region is formed at a boundary portion between the source region and the field insulating film, and a power supply potential is applied through a conductor filling the contact hole. -It has a structure in which it is supplied as the substrate potential to the substrate portion below the source region and is also supplied as the source potential to the source region. That in the semiconductor integrated circuit device. Here, a refractory metal film or a refractory metal alloy film may be formed on the upper surfaces of the source and drain regions.

Another feature of the present invention is that a field insulating film selectively formed on the main surface of the semiconductor substrate and a P channel in which P type source and drain regions are formed in the N type region of the semiconductor substrate. A semiconductor integrated circuit having a MOS transistor and an N-channel MOS transistor in which N-type source and drain regions are formed in a P-type region of the semiconductor substrate, and forming a CMOS from the P-channel MOS transistor and the N-channel MOS transistor. In the circuit device, a contact hole deeper than the P-type source region is formed at a boundary portion between the P-type source region and the field insulating film, and the N-type region of the semiconductor substrate under the P-type source region is formed. And the contact hole is filled with a first conductor connecting to the P-type source region and the N-type source region and the flux. A contact hole deeper than the N-type source region is formed at a boundary with the field insulating film, and a second contact hole connected to the P-type region and the N-type source region of the semiconductor substrate under the N-type source region is formed. In a semiconductor integrated circuit device in which this contact hole is filled with a conductor. Here, it is possible to have an electrode wiring structure that supplies a high-potential-side power supply potential to the first conductor and supplies a low-potential-side power supply potential to the second conductor.

Further, in the above structure, the boundary between the source region and the field insulating film is planar and linear, and the contact hole extends from the boundary to both the source region and the field insulating film. Can be crotch-formed on the side. Or in the above configuration,
The boundary between the source region and the field insulating film is planar and linear, and the contact hole may be formed to extend from the boundary only in the direction of the field insulating film. .

Another feature of the present invention is that a field insulating film is selectively formed on the main surface of a silicon substrate, and a gate electrode is formed on the impurity region of the first conductivity type of the semiconductor substrate via the gate insulating film. And a second-conductivity-type source having a refractory metal film or a refractory metal alloy film formed on the upper surface thereof at a position of the impurity region between the field insulating film and the gate electrode. Forming a drain region and forming an interlayer insulating film covering the entire drain region; and forming a first opening on a boundary part between the source region and the field insulating film and forming a second opening on the drain region. Forming a mask pattern provided with the opening on the interlayer insulating film, and using the mask pattern as a mask, the insulating film is predominantly etched by a refractory metal or a refractory metal alloy and silicon. Etching is performed to remove the interlayer insulating film and the field insulating film under the first opening by etching to expose the impurity region at the boundary portion, and the interlayer insulating film under the second opening is removed. A step of exposing the refractory metal film or the refractory metal alloy film in the drain region by etching to form a drain contact hole; and using the mask pattern again as a mask, refractory metal or refractory metal A second etch is performed that preferentially etches silicon over the alloy to etch away the impurity region at the boundary below the first opening to form a source deeper than the source region.
Forming a substrate contact hole; and filling the drain contact hole with a conductor to form a drain electrode, and filling the source-substrate contact hole with a conductor to form a source and a substrate electrode. A method for manufacturing a semiconductor integrated circuit device has.

[0031]

According to the present invention as described above, a contact hole deeper than the source region is formed at the boundary between the source region and the field insulating film, and the source potential is sourced through the conductor filling the contact hole. Since it is supplied to the substrate portion and the source region below the region, a high-concentration region for contact is unnecessary, and it is not necessary to increase the area of the source region because the through contact hole is not formed in the center of the source region. As a result, the degree of integration can be improved.

Further, since the deep contact hole is formed at the boundary between the source region and the field insulating film, the source region and the drain region provided with the refractory metal film or the refractory metal alloy film on the surface. Can be formed under the condition that is not etched. Therefore, the contact hole to the source region and the substrate region can be formed by using the mask pattern for forming the contact hole to the drain region as it is. Therefore, the manufacturing process can be simplified.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention. (A) is a plan view, (B) and (C) are BB parts and (B) of (A), respectively. It is an expanded sectional view of CC section.

First, the N well 2 is formed on the P-type silicon substrate 1.
(Indicated by a dotted line in (A)) is formed, and a field insulating film 5 made of a thick silicon oxide film partially buried in the substrate is formed on the main surface by a selective thermal oxidation method (LOCOS method) to form a transistor. It divides the area.

In the N well 2, a P type impurity region 3 serving as a source and drain region of a P channel MOS transistor is formed.
A, 3B and 3C are arranged in one direction (X direction in FIG. 1A) with the refractory silicide film 7 formed on the surface thereof, and the gate insulating film 11 is formed at each interval, that is, on the channel region.
Polysilicon gate electrodes 8A and 8B whose surfaces are covered with a thermal silicon oxide film 12 are formed via the vias.

Similarly, in the P-type region 1A of the silicon substrate 1, the N-type impurity regions 4A, 4B and 4C, which are the source and drain regions of the N-channel MOS transistor, have the refractory silicide film 7 formed on the surface thereof. One direction (Fig. 1 (A)
In the X direction), and polysilicon gate electrodes 8A and 8A whose surface is covered with a thermal silicon oxide film 12 via the gate insulating film 11 on the respective intervals, that is, the channel regions.
B is continuously formed from P-channel MOS transistors.

In this embodiment of the master slice system, the P channel MOS transistor is a P type impurity region 3.
A is the P-type source region 3A and P-type impurity region 3B is P
The type drain region 3B is formed by using the polysilicon gate electrode 8A extending over the channel region between the type drain region 3B and the gate insulating film 11.

In the N-channel MOS transistor, the N-type impurity region 4A is used as the N-type source region 4A, the N-type impurity region 4B is used as the N-type drain region 4B, and the P region is formed on the channel region between them via the gate insulating film 11. Channel MO
It is configured using a polysilicon gate electrode 8A continuously extending from the S transistor.

Then, an interlayer insulating film 6 made of a silicon oxide film is entirely deposited.

The boundary 60 between the P-type source region 3A and the N-type source region 4A and the field insulating film 5 extends linearly in the direction perpendicular to the above-mentioned one direction (Y direction in FIG. 1A). , 60, and contact holes 9A, 9A deeper than these source regions are formed at the boundary portions on both sides of the P-type source region 3A and the N-type source region 4A and the field insulating film 5, respectively. Has been formed. The deep contact holes 9A and 9A of this embodiment are shown in FIGS.
As shown in (C), the lower portion formed on the silicon substrates 2 and 1A has a smaller area than the upper portion formed on the interlayer insulating film 6.

The contact holes 9A, 9A are filled with a conductor 13 such as TiW, and an aluminum power source wiring layer 14 on the high potential side and an aluminum power source wiring layer 15 on the low potential side are connected to the upper surface of the conductor 13 respectively. There is. In this case, the contact holes 9A, 9A may be filled with the aluminum power supply wiring layers 14, 15 so that the portions of the aluminum wiring layers 14, 15 in the contact holes serve as the conductors 13.

With this structure, a high-potential power supply potential is supplied to the N well (N-type region) 2 from below the contact hole 9A as the substrate potential of the P-channel MOS transistor, and from above the contact hole 9A to the P-type. Source area 3A
Through the upper surface (high melting point silicide film 7) and side surfaces of P
It is supplied as a source potential to the mold source region 3A.

Similarly, the low-potential power supply potential is the P-type region 1A.
Is supplied as a substrate potential of the N-channel MOS transistor from below the contact hole 9A.
From the upper part of A through the upper surface (refractory metal silicide film 7) and the side surface of the N-type source region 4A, the N-type source region 4
It is supplied to A as a source potential.

The aluminum wiring layer 16 serving as an output node is formed through the contact holes 9B, 9B formed in the interlayer insulating film 6.
Are commonly connected to the P-type drain region 3B and the N-type drain region 4B.

In the CMOS of this master slice, an input signal is input to the common gate electrode 8A, and an output signal is output from the aluminum wiring layer 16.

In FIG. 1A of the plan view, the contact holes 9A and 9B are shown by solid small squares.

Next, a method of an embodiment for manufacturing the semiconductor integrated circuit device of FIG. 1 will be described with reference to FIG.

First, in FIG. 2A, an N-type impurity is ion-implanted into a selective portion of a P-type silicon substrate 1, and an N well (N-type region) 2 is formed by a subsequent activation heat treatment. Then, a field insulating film 5 is formed by a selective thermal oxidation method to define a transistor formation region. Further, a channel stopper region for preventing generation of a parasitic channel can be formed under the field insulating film 5. N
P-type region 1A inside and outside the well (N-type region) 2
And a polysilicon gate electrode 8 via a gate insulating film 11.
A is formed, and its surface is covered with a silicon oxide film 12 formed by a thermal oxidation method. Then, P in the N well 2
P-type impurity regions 3A and 3B to be the source and drain regions of the channel MOS transistor are formed in self-alignment with the gate electrode and the field insulating film by ion implantation of P-type impurities and subsequent activation heat treatment. Similarly, in the P-type region 1A, N-type impurity regions 4A and 4A serving as the source and drain regions of the N-channel MOS transistor are formed.
B is formed in a self-aligned manner with respect to the gate electrode and the field insulating film by ion implantation of N-type impurities and subsequent activation heat treatment. Then, a refractory metal film or a refractory metal alloy film, for example, a refractory metal silicide film 7 such as a titanium silicide film by a salicide process is formed on the upper surfaces of the source and drain regions.

Next, in FIG. 2 (B), an interlayer insulating film 6 made entirely of a silicon oxide film is formed, and a photoresist pattern 21 is formed thereon. The photoresist pattern 21 has a first portion located above the boundary between the P-type source region 3A and the field insulating film 5 and on a portion crotch on both sides of the P-type source region 3A and the field insulating film 5. From the boundary between the opening 22A, the second opening 22B located on the P-type drain region 3B, the N-type source region 4A and the field insulating film 5, the N-type source region 4A and the field insulating film 5 are formed.
The first opening 22A located on the crotch portion on both sides of
A second opening 22B located on the N-type drain region 4B is provided.

Next, referring to FIG. 2C, using the photoresist pattern 21 as a mask, the insulating film is removed from the refractory metal or its alloy and silicon, in this case, the silicon oxide film is predominantly removed by etching. Etching is performed. As a result, the first openings 22A, 2A
Under 2A, the interlayer insulating film 6 and the field insulating film 5 are selectively removed, and the upper portion 9'A of the deep contact hole,
9'A are obtained respectively, and the interlayer insulating film 6 is selectively removed under the second openings 22B and 22B to reach the high melting point silicide film 7 of the P-type drain region 3B and the N-type drain region 4B. Contact holes 9B and 9B are formed, respectively.

Next, in FIG. 2D, using the photoresist pattern 21 as a mask again, anisotropic etching is performed under the etching conditions in which silicon is predominantly removed by etching from the refractory metal or its alloy.
As a result, the N well (N type region) 2 and the P type region 1A of the silicon substrate exposed by removing the field insulating film 5 under the first openings 22A and 22A are removed by etching, and the source region 3A. , Contact holes 9A deeper than 4A,
9A are formed respectively. In this etching, since the refractory metal silicide film 7 in the source regions 3A and 4A serves as an etching stopper, the deep contact holes 9A and 9A are formed.
A is narrower in the lower portion deeply formed below the upper portions 9'A, 9'A formed in the interlayer insulating film 6A on the source regions 3A, 4A. In addition, the drain regions 3B and 4B
Since the refractory metal silicide film 7 also serves as an etching stopper, there is no problem even if the second opening 22B, 22B is provided in the photoresist pattern 21 in this second anisotropic etching.

Next, in FIG. 2E, the deep contact holes 9A, 9A are filled with a conductor 13 such as TiW, and aluminum wiring layers 14, 15, 16 are formed by patterning. Alternatively, the aluminum wiring layers 14 and 15 are used to form the contact holes 9A and 9A.
A portion filled with A and filled with the aluminum wiring layers 14 and 15 may be used as the conductor 13.

After that, a passivation film and other wiring structures are formed if necessary, and the semiconductor integrated circuit device is completed.

3A and 3B are views showing a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 3A is a plan view and FIG. 3B is an enlarged sectional view of a portion BB of FIG. . Note that, in FIG. 3, the same or similar portions as those in FIG.

Also in FIG. 3, similarly to FIG. 1, in the N well 2, the high melting point silicide film 7 is formed on the surface of the P type impurity regions 3A, 3B and 3C to be the source and drain regions of the P channel MOS transistor. And one direction (Fig. 3 (A)
In the X direction), and polysilicon gate electrodes 8A and 8A whose surface is covered with a thermal silicon oxide film 12 via the gate insulating film 11 on the respective intervals, that is, the channel regions.
B are formed respectively.

Similarly, in the P-type region 1A of the silicon substrate 1, the N-type impurity regions 4A, 4B and 4C to be the source and drain regions of the N-channel MOS transistor are formed with the refractory silicide film 7 on the surface thereof. One direction (Fig. 3 (A)
In the X direction), and polysilicon gate electrodes 8A and 8A whose surface is covered with a thermal silicon oxide film 12 via the gate insulating film 11 on the respective intervals, that is, the channel regions.
B is continuously formed from P-channel MOS transistors.

However, in FIG. 3, unlike the case of FIG. 1, the P-channel MOS transistor has a P-type impurity region 3
A is the P-type drain region 3A, and the P-type impurity region 3B is the P-type source region 3B.

Similarly, the N-channel MOS transistor has N
The type impurity region 4A is used as an N type drain region 4A, and the N type impurity region 4B is used as an N type source region 4B.

Therefore, the P-type source region 3B and the N-type source region 4B and the field insulating film 5 respectively have boundaries 70, 70 extending linearly in the X direction, and the deep first contact of the present invention. The holes 9A and 9A are formed on both sides of the P-type source region 3B and the N-type source region 4B and the field insulating film 5 at the boundary portion extending in the same X direction as the arrangement direction of the impurity regions. Are formed deeper than these source regions. Such a configuration is obtained depending on the layout design of the master-slice.

FIG. 4 is a diagram showing a semiconductor integrated circuit device according to a third embodiment of the present invention. (A) is a plan view, (B) and (C) are portions BB and B of (A), respectively. It is an expanded sectional view of CC section. A method of an embodiment for manufacturing the semiconductor integrated circuit device of FIG. 4 will be described with reference to FIG. still,
In FIGS. 4 and 5, the same or similar portions as those in FIGS. 1 and 2 are denoted by the same reference numerals, and thus redundant description will be omitted as much as possible.

The first openings 32A and 32A provided in the photoresist pattern 21 of the third embodiment are defined by the boundaries 60 and 60 between the P-type source regions 3A and N-type source regions 4A and the field insulating film 5. They are respectively located on the portions extending only to the field insulating film 5 side.

Therefore, deep contact holes 19A, 19
A is formed in the same planar shape from the upper portions 19'A, 19'A of the interlayer insulating film 6 to the deep lower portion under the source region,
The conductor 13 filled therein is connected only to the side surfaces of the P-type source region 3A and the refractory metal silicide film 7 on it, and the N-type source region 4A and the refractory metal silicide film 7 on it, respectively. The source potential of is supplied.

In this embodiment, deep contact holes 19A,
19A is formed only in the boundary portion of the field insulating film 5 and the silicon substrate portion thereunder, and does not penetrate into the source regions 3A and 4A in the planar shape, so that the source region can be made as small as necessary. it can.

In the first to third embodiments, one contact hole is illustrated for each source and drain region. However, a plurality of contact holes may be arranged for each region. In particular, the deep contact hole 9A or 19A of the present invention for supplying the substrate potential and the source potential is formed not at the center of the source region but at the boundary between the source region and the field insulating film. By forming a plurality of deep contact holes 9A or 19A without increasing the plane area of the source region, the substrate potential can be made uniform and the contact resistance with the electrode wiring can be reduced. For example, in FIG. 1A, a plurality of deep contact holes 9A are arranged along a linear boundary 60 formed by the P-type source region 3A and the field insulating film 5.
A plurality of deep contact holes 9A can be arranged along the linear boundary 60 formed by the N-type source region 4A and the field insulating film 5.

[0066]

As described above, according to the present invention, a contact hole deeper than the source region is formed at the boundary between the source region and the field insulating film, and the power supply potential is supplied through the conductor filling the contact hole. -Since the power supply potential is supplied to the substrate portion and the source region below the source region, the high-concentration region for contact is unnecessary, and since the through contact hole is not formed in the center of the source region, the area of the source region is increased. Is unnecessary, and the degree of integration can be improved. In addition, since it is formed at the boundary with the field insulating film as described above, the number of deep contact holes necessary for uniformizing the substrate potential and reducing the contact resistance with the electrode wiring are provided in the plane area of the source region. Can be formed without increasing.

In addition, the contact hole is connected to the source region and the source region.
Since it is formed at the boundary with the field insulating film, the high melting point metal film or the high melting point metal alloy film can be formed under the condition that the source region and the drain region provided on the surface are not etched. Therefore, a deep contact hole to the source region and the substrate region can be formed using the mask pattern for forming the contact hole reaching the drain region as it is. Therefore, the manufacturing process can be simplified.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor integrated circuit device of a first embodiment of the present invention, (A) is a plan view, (B) and (C) are portions BB and C- of (A), respectively. It is an expanded sectional view of C section.

2A to 2D are cross-sectional views showing a method of an embodiment of manufacturing the semiconductor integrated circuit device of FIG. 1 in order of steps.

3A and 3B are diagrams showing a semiconductor integrated circuit device according to a second embodiment of the present invention, FIG. 3A being a plan view and FIG.
It is an expanded sectional view of a B section.

FIG. 4 is a diagram showing a semiconductor integrated circuit device according to a third embodiment of the present invention, in which (A) is a plan view, and (B) and (C) are portions BB and C- of (A), respectively. It is an expanded sectional view of C section.

5A to 5C are cross-sectional views showing a method of an embodiment of manufacturing the semiconductor integrated circuit device of FIG.

FIG. 6 is a sectional view showing a conventional semiconductor integrated circuit device.

FIG. 7 is a sectional view showing another conventional semiconductor integrated circuit device.

FIG. 8 is a cross-sectional view showing a method of manufacturing the semiconductor integrated circuit device of FIG. 7 in order of steps.

[Explanation of symbols]

1 P-type silicon substrate 1A P-type region 2 N well (N-type region) 3A, 3B, 3C P-type impurity region 4A, 4B, 4C which becomes a source or drain region 5A N-type impurity region which becomes a source or drain region Field insulating film 6 Interlayer insulating film 7 Refractory metal silicide film 8, 8A, 8B Polysilicon gate electrode 9A, 19A Deep contact hole 9'A, 19'A Upper part of deep contact hole 9B Contact hole 11 Gate insulating film 12 Thermal Silicon oxide film 13 Conductor 14, 15, 16 Electrode wiring layer 21 Photoresist pattern 22A, 22B, 32A Opening 34, 35, 36 Electrode wiring layer 37, 68, 68 'Contact hole 41 P Type drain region 42 P type source region 43 N ⁺ type contact region 51 N Type drain region 52 N type source region 53 P ⁺ type contact region 60, 70 Linear boundary formed by the source region and the field insulating film 5 81 First photoresist patterns 82A, 82B For the first photoresist pattern Opening provided 91 Second photoresist pattern 92A Opening provided in second photoresist pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/822 H01L 27/04 A

Claims (7)

[Claims] 1. A source region and a drain region formed in a transistor forming region partitioned by a field insulating film selectively provided on a main surface of a semiconductor substrate, and between the source region and the drain region. A semiconductor for applying a substrate potential of the insulated gate field effect transistor from a main surface side of the semiconductor substrate, the insulated gate field effect transistor having a gate electrode formed on a channel region of the semiconductor substrate via a gate insulating film. In an integrated circuit device,
A contact hole deeper than the source region is formed at a boundary portion between the source region and the field insulating film, and a power supply potential is applied to a substrate portion below the source region through a conductor filling the contact hole. A semiconductor integrated circuit device having a structure in which it is supplied as a substrate potential and is supplied as a source potential to the source region. 2. The boundary between the source region and the field insulating film is planar and linear, and the contact hole is located on both sides of the source region and the field insulating film from the boundary. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed in a crotch shape. 3. The boundary between the source region and the field insulating film is planar and linear, and the contact hole extends from the boundary only in the direction of the field insulating film. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided. 4. The semiconductor according to claim 1, wherein a refractory metal film or a refractory metal alloy film is formed on upper surfaces of the source and drain regions. Integrated circuit device. 5. A field insulating film selectively formed on a main surface of a semiconductor substrate, and a P-channel insulated gate field effect transistor having P-type source and drain regions formed on an N-type region of the semiconductor substrate. An N-channel insulated gate field effect transistor having N-type source and drain regions formed in a P-type region of the semiconductor substrate, the P-channel insulated gate field-effect transistor and the N-channel insulated gate field-effect transistor. CMOS
In the semiconductor integrated circuit device configured as described above, a contact hole deeper than the P-type source region is formed at a boundary portion between the P-type source region and the field insulating film, and the semiconductor substrate under the P-type source region is formed. Said N
The contact hole is filled with a first conductor connecting to the N-type source region and the P-type source region, and a contact deeper than the N-type source region is formed at a boundary portion between the N-type source region and the field insulating film. A hole is formed and the P of the semiconductor substrate under the N-type source region is formed.
A semiconductor integrated circuit device, characterized in that the contact hole is filled with a second conductor connected to the mold region and the N-type source region. 6. An electrode wiring structure for supplying a high-potential-side power supply potential to the first conductor and supplying a low-potential-side power supply potential to the second conductor. The semiconductor integrated circuit device according to claim 5. 7. A field insulating film is selectively formed on a main surface of a silicon substrate, and a gate electrode is formed on the impurity region of the first conductivity type of the semiconductor substrate via a gate insulating film. A second conductivity type source and drain region having a refractory metal film or a refractory metal alloy film provided on an upper surface thereof is formed at a portion of the impurity region between the gate insulating film and the gate electrode; A step of forming an interlayer insulating film covering the whole, and a first opening is provided on a boundary portion between the source region and the field insulating film, and a second opening is provided on the drain region. A step of forming a mask pattern on the interlayer insulating film, and a first etching for predominantly etching the insulating film with respect to the refractory metal or the alloy of the refractory metal and silicon using the mask pattern as a mask The interlayer insulating film and the field insulating film under the first opening are removed by etching to expose the impurity region at the boundary portion, and the interlayer insulating film under the second opening is removed by etching. Forming a drain contact hole by exposing the refractory metal film or the refractory metal alloy film in the drain region; and using the mask pattern again as a mask to remove silicon from the refractory metal or the refractory metal alloy. Performing a second etching that predominantly etches to etch away the impurity region at the boundary below the first opening to form a source-substrate contact hole deeper than the source region; Filling the drain contact hole with a conductor to form a drain electrode, and filling the source-substrate contact hole with a conductor. The method of manufacturing a semiconductor integrated circuit device characterized by a step of forming a over scan and the substrate electrode.