JPH0817941A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the storage capacity of a memory array and improve the refresh characteristics, by supplying only the necessary and minimized back bias voltage to a P-type well where a memory array part is formed, and forming a specified I/O circuit. CONSTITUTION:A memory array part and an I/O circuit are formed. The memory array part is constituted by arranging dynamic memory cells in a matrix. A P-type well region BP where the memory array is formed is formed in an N substrate N-SUB, and a substrate bias voltage VBB like-IV is supplied. That is, a back bias voltage of a small absolute value which is optimum to refresh characteristics is supplied. A back bias voltage wherein the under shoot voltage is considered and the absolute value is increased is supplied to the P-type well region BP where an N channel MOSFET constituting an I/O part is formed. Thereby a leak current is reduced, refresh characteristics are improved, and under shoot countermeasure is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device provided with a memory array section in which dynamic memory cells are arranged in a matrix and an input / output circuit connected to an external terminal. It relates to effective technology.

[0002]

2. Description of the Related Art A dynamic RAM in which the threshold voltage of a MOSFET is optimized by a triple well structure has been proposed by Nikkei McGraw-Hill Co., March 1989, "Nikkei Microdevice", pages 54 to 58. In this dynamic RAM, a memory cell is formed by using an N substrate and a P-type well and an N-type substrate junction are used to improve soft error resistance, and an undershoot of an input pin and an N-channel MOSFET of a peripheral circuit are used. The data destruction of the memory cell caused by the generated minority carriers is eliminated, and the data protection characteristic of the memory cell is improved.

In the above-mentioned triple well structure, in order to solve the problem of substrate effect due to device miniaturization and power down, a well region in which a P-channel MOSFET and an N-channel MOSFET forming a peripheral circuit are formed is formed. A bias voltage is set so that the threshold voltage is set to be optimum in terms of characteristics. On the other hand, the conventional back bias voltage is applied to the P-type well region of the memory array.

[0004]

With the miniaturization of elements,
The refresh characteristic tends to deteriorate. That is, it has been found that the refresh cycle tends to be shortened as the element is miniaturized to increase the storage capacity. As a result of analyzing such refresh characteristics, the inventors of the present application have found the following. The back bias voltage is supplied to the P-type well region where the memory cell is formed by increasing the threshold voltage of the switch MOSFET for address selection, and by coupling with the bit line, the gate voltage of the non-selected memory cell is increased. Lifting switch MOSFET
Is to prevent the high level or low level of the bit line from being transmitted to the storage capacitor by being turned on weekly. Conventionally, the back bias voltage is set exclusively from this point of view, and even in the above-mentioned dynamic RAM, a relatively large negative bias voltage V _BB such as about -3 V in consideration of the undershoot of the input pin is given. is there.

However, with the miniaturization of elements, it is necessary to increase the P-type impurity concentration as a channel stopper under the field insulating film between memory cells, and the storage node of the switch MOSFET (storage capacitor) provided so as to be bonded to it. The PN junction with the source / drain diffusion layer on the side) has a high impurity concentration. Therefore, if the back bias voltage of the P-type well region in which the memory array is formed is increased as in the conventional case, the leak current in the PN junction becomes large, which is a major cause of shortening the refresh cycle as described above. There was found.

An object of the present invention is to provide a semiconductor integrated circuit device which has a large storage capacity of a memory array in which dynamic memory cells are arranged in a matrix and an improvement in its refresh characteristic. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, the P-type well portion in which the memory array portion in which the dynamic type memory cells are arranged in a matrix is formed is supplied with a back bias voltage which is a voltage that is small in absolute value and is optimum for its refresh characteristic, and the external terminal N of input circuit or output circuit connected to
The P-type well portion in which the channel type MOSFET is formed is supplied with a back bias voltage that is increased in absolute value in consideration of the undershoot voltage.

[0008]

According to the above-mentioned means, the P-type well region in which the memory array portion is formed is supplied with only the necessary minimum back bias voltage. Therefore, the source / drain regions to which the capacitors are connected and the P-type well are connected. A back bias voltage for undershoot protection can be supplied to the P-type well region in which the input circuit or the output circuit corresponding to the external terminal is formed while reducing the leak current flowing between the input and output terminals and improving the refresh characteristic.

[0009]

1 is a block diagram of an embodiment of a dynamic RAM to which the present invention is applied. Each circuit block in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Each circuit block in the figure is
It is drawn according to the geometrical arrangement in the actual semiconductor chip. In the present application, MOSFET is used to mean an insulated gate field effect transistor (IGFET).

In this embodiment, it is possible to prevent the operation speed from being slowed down by lengthening various wiring lengths such as control signals and memory array drive signals due to the increase in chip size accompanying the increase in memory capacity. for,
The following arrangements have been made in the arrangement of the memory array portion that constitutes the RAM and the peripheral portion that performs address selection and the like.

In the figure, a cross area formed by the vertical center portion and the horizontal center portion of the chip is provided. Peripheral circuits are mainly arranged in this cross-shaped area, and a memory array is arranged in an area divided into four by the cross-shaped area. That is, a cross-shaped area is provided in the central portion in the vertical and horizontal directions of the chip, whereby a memory array is formed in four divided areas. Although not particularly limited, each of the four memory arrays has a storage capacity of about 4 Mbits, which will be described later. Accordingly, the four memory arrays as a whole have a large storage capacity of about 16 Mbits.

One memory mat MEMORY MAT
Are arranged so that the word lines extend in the horizontal direction, and the complementary bit lines (data lines or digit lines) formed in parallel in pairs in the vertical direction extend. A pair of memory mats MEMORY MAT are arranged on the left and right with the sense amplifier SA as the center. Sense amplifier SA
Is a pair of memory mats MEMORY arranged on the left and right
It is a so-called shared sense amplifier system that is commonly used for MATs.

Of the memory arrays divided into four, a Y selection circuit Y-DECODER is provided on the central side. The Y selection line is a Y selection circuit Y-DECODE
The column switch M of each memory mat MEMORY MAT extends from R to extend over a plurality of memory mats MEMORY MAT of the corresponding memory array.
Performs switch control of the gate of the OSFET.

An X address buffer X-ADDRESS B is provided on the left side portion of the central portion of the chip in the horizontal direction.
UFFER, X redundant circuit X-REDUNDANCY C
KT and X address driver X-ADDRESS DR
X system circuit including IVER (logical stage LOGIC STEP), RAS system control signal circuit RAS CKT, WE system signal control circuit WE SYSTEM, data input buffer DIN BUFFER and internal voltage down converter VCL LIM
Each ITER is provided. Internal voltage step-down circuit VC
The L LIMITER is provided near the center of this area and receives the external power supply VCCE of about 5V to form a constant voltage VCL corresponding to a voltage of about 3.3V supplied to the internal circuit.

A Y address buffer Y-ADDRESS B is provided in the right side portion of the central portion of the chip in the horizontal direction.
UFFER, Y redundant circuit Y-REDUNDANCY and Y address driver Y-ADDRESS DRIVER
A Y-system circuit including (logic stage LOGIC STEP), a CAS-system control signal circuit CAS CKT, and a test circuit TEST FUNCTION are provided.
An internal step-down circuit VDL LIMITER that forms a power supply voltage VCL for peripheral circuits such as an address buffer and a decoder is provided in the central portion of the chip.

As described above, the redundancy circuit X, Y-RE including the address buffer and the address comparison circuit corresponding to the address buffer.
DUNDANCY, CAS and R for generating control clock
If the AS control signal circuits RAS, CAS CKT, etc. are centrally arranged in one place, for example, the clock generation circuit and other circuits are distributed with the wiring channel sandwiched therebetween, in other words, the wiring channel is shared, thereby achieving high integration. In addition, the signal can be transmitted to the address driver (logical stage) or the like at the shortest distance and at the same distance.

The RAS control circuit RAS CKT is used to receive the row address strobe signal RASB and activate the X address buffer X-ADDRESS BUFFER. X address buffer X-ADDRE
The address signal taken into SS BUFFER is supplied to the X-system redundancy circuit X-REDUNDANCY. Here, the stored defective address is compared to determine whether or not the redundant circuit is switched to. The result and the address signal are supplied to the X-system predecoder. Here, a predecode signal is formed, and an X address driver DV provided corresponding to each memory array.
2 and DV3, the respective X decoders X-DECODE provided corresponding to the above memory mats.
Supplied to R.

On the other hand, the internal signal of the RAS system is supplied to the WE system control circuit WE SYSTEM and the CAS system control circuit CAS CKT. For example,
The RASB signal and the column address strobe signal CA
The automatic refresh mode (CBR), the test mode (WCBR) and the like are identified based on the determination of the input order of the SB and the write enable signal WEB. In the test mode, the test circuit TEST FUNCTION is activated, and the test function is set in accordance with a specific address signal supplied at each timing in each public / standardized or private test mode provided as necessary. .

The CAS control circuit CAS CKT is used to receive the signal CASB and form various Y control signals. The Y address buffer Y-ADDRESS BUF is synchronized with the change of the signal CASB to the low level.
The address signal fetched by the FER is supplied to the Y-system redundant circuit Y-REDUNDANCY. The defective address stored here is compared to determine whether or not the redundant circuit is switched. The result and the address signal are supplied to the Y-system predecoder. The predecoder forms a predecode signal. This predecode signal is supplied to each Y decoder Y-DECODER via the Y address driver DV1 provided corresponding to each of the four memory arrays, while the CAS
When the system control circuit CAS CKT receives the RAS signal and the WEB signal as described above and determines the test mode from the determination of the input order, the adjacent control circuits TEST
Activates FUNCTION.

A total of 16 memory mats MEMORY MAT and 8 sense amplifiers SA are arranged symmetrically with respect to the central axis of this area in the upper part of the vertical center of the chip. It Of these, four main amplifiers MA corresponding to the memory mat MEMORY MAT and the sense amplifier SA, each consisting of four left and right pairs.
Is provided. In addition, a boosted voltage generating circuit VC for word line selection or the like is received at the upper part of the vertical center by receiving an internal step-down voltage.
An input pad area corresponding to H and input signals such as address signals and control signals is provided.

In this embodiment, eight memory mats MEMORY MATs and four sense amplifiers SA are arranged in one block, and a total of 16 memory mats MEMORY MATs and 8 are arranged symmetrically with respect to the vertical axis. Each sense amplifier SA is assigned. With this configuration,
It is possible to transmit the amplified signal from each sense amplifier SA to the main amplifier MA through a short signal propagation path while using a small number of four main amplifiers MA.

A total of 16 memory mats MEMORY MAT and 8 sense amplifiers SA are arranged symmetrically with respect to the central axis of this area in the lower part of the vertical center of the chip. To be done. Of these, four main amplifiers MA corresponding to the memory mat MEMORY MAT and the sense amplifier SA, each consisting of four left and right pairs.
Is provided.

In addition to the above, the vertical center portion corresponds to a substrate voltage generating circuit VBB that receives an internal step-down voltage and forms a negative bias voltage to be supplied to the substrate, and an input signal such as an address signal and a control signal. The input pad area and the data output buffer circuit OUTPUTBUFFER are provided. Similarly to the above, it is possible to transmit the amplified signal from each sense amplifier SA to the main amplifier 7 through a short signal propagation path while using a small number of main amplifiers MA such as four.

Although not shown in the figure, various bonding pads are arranged in the vertical central region. Examples of these bonding pads are pads for external power supply, and in order to increase the level margin of the input, in other words, to supply the ground potential of the circuit in order to lower the power supply impedance, there are a total of more than 10 pads. And relatively many are arranged side by side on a straight line. These ground potential pads are connected to ground potential leads formed by the LOC technique and extending in the vertical direction. Of these ground pads, those provided especially for clearing the word line and preventing floating due to coupling of the non-selected word line of the word driver, those provided for the common source of the sense amplifier, etc. It is provided mainly for the purpose of lowering the power source impedance.

As a result, the ground potential of the circuit has a lower power source impedance with respect to the operation of the internal circuit, and the ground wiring between the internal circuits divided into a plurality of types as described above is formed from the LOC lead frame and the bonding wire. Since it is connected by a low-pass filter, the generation of noise can be minimized, and the propagation of circuit ground line noise between internal circuits can also be minimized.

In this embodiment, pads corresponding to the external power supply VCC of about 5V are provided corresponding to the internal voltage down converters VCL and VDL LIMITER which perform the above voltage conversion operation. This also lowers the power supply impedance in the same manner as above, and also reduces the voltage between internal circuits (VCL,
This is for suppressing noise propagation between VDL and VCC).

Address input pad, RAS, CA
Pads for control signals such as S, WE, and OE are arranged in the central area. In addition to this, the following pads are provided for pad control for data input and data output, bonding master, monitor and monitor pads.

For the bonding master, there are one for designating the static column mode, and one for designating the nibble mode and the write mask function in the x4 bit configuration. Internal voltage V of each pad for monitoring
There is one for monitoring CL, VDL, VL, VBB, VCH and VPL. The VPL monitor determines whether or not the VPL adjustment is correctly performed during probing.

The internal step-down circuit VCL LIMITER is
A peripheral circuit power supply voltage VCL of about 3.3 V is generated. The internal step-down circuit VDL LIMITER has about 3.
Memory array such as 3V, that is, sense amplifier S
A power supply voltage VDL supplied to A is generated. The booster circuit VCH receives the above-mentioned internal voltage VCL and is boosted to about 5.3 V word line selection level, the shared switch MO.
Form the boost supply voltage that selects the SFET. Two substrate voltage generating circuits are provided, one of which generates -2 V applied to the P-type well region in which the N-channel type MOSFET forming the input / output circuit is formed, and the memory mat MEMORY MAT. Which generates -1 V applied to the P-type well region to be formed. The plate voltage generation circuit VPL generates the plate voltage of the memory cell.

In the dynamic RAM of this embodiment, the P-type well region in which the N-channel MOSFET is formed can be classified into three types according to the back bias voltage supplied to it. In the first P-type well region, a memory array in which dynamic memory cells are arranged in a matrix is formed, and the second P-type well region is formed.
In the mold well region, an input circuit or an output circuit connected to an external terminal is formed. And the remaining third P
The type well region is a peripheral circuit of the memory array, and includes a precharge circuit for precharging a data line to which a dynamic memory cell is connected, a sense amplifier, and a switch M for connecting the sense amplifier and the data line.
The OSFET is included in the peripheral circuit. That is, the above-mentioned memory array is a portion in which only memory cells are arranged in a matrix.

The P-type well region divided into three as described above does not mean that there are physically three. That is, the first P-type well region in which the memory array is formed is composed of a plurality of memory mats corresponding to a plurality of divided memory mats. Similarly, a third peripheral circuit is formed.
The P-type well region is composed of one provided corresponding to the memory mat and a plurality of P-type well regions appropriately divided corresponding to each logic circuit block forming the address decoder and the control circuit. In the second P-type well region, the input / output circuit connected to the external terminal is divided by circuits such as the main amplifier MA and the voltage generation circuits VCH and VBB as shown in FIG. Are appropriately divided.

A back bias voltage having a small absolute value such as -1V is supplied to the first P-type well region in which the memory array is formed for the reason described later. On the other hand, in the second P-type well region in which the input / output circuit is formed, the semiconductor region to which it is transmitted by the undershoot of the external terminal and the P-type well region are not forward-biased. A back bias voltage having a large absolute value such as 2 V is supplied. Then, the ground potential of the circuit is supplied to the third P-type well region in which peripheral circuits other than the memory array and the input / output circuit are formed. As a result, the threshold voltage of the MOSFET in the peripheral circuit is reduced, and the operation speed can be increased. In particular,
In the case where the power supply voltage is lowered to 3.3V and the internal voltage is lowered to about 2.2V by the internal step-down circuit, a MOSFET for such a low amplitude input signal is obtained.
The conductance is increased, and the operation speed can be increased.

Of the three P-type well regions divided as described above, the ground potential of the circuit is applied to the third P-type well region in which the peripheral circuit is formed, so that the substrate bias generating circuit becomes unnecessary. , The two substrate bias voltage generating circuits VB as described above in order to supply separate back biases to the remaining two first and second P-type well regions.
B is provided.

FIG. 2 is a block diagram focusing on the control signals in the dynamic RAM to which the present invention is applied. This figure is drawn corresponding to the layout diagram shown in FIG.

RAS control circuit RAS CO
NTROL (CKT) is used to receive the signal RASB and activate the X address buffer X-ADDRESS BUFFER. X address buffer X-AD
The address signal taken into the DRESS BUFFER is supplied to the X-system redundant circuit X-REDUNDANDY CKT. Here, the stored defective address is compared to determine whether or not the redundant circuit is switched to.

The result and the address signal are supplied to the X-system predecoder X-PREDEC (X1, AXn1). Here, a predecode signal composed of Xi and AXnl is formed, and each of the memory mats MEMORY MAT is provided through the X address drivers XiB and AXnl provided corresponding to each memory array. It is supplied to the X decoder X-DEC. In the figure, only one driver is exemplarily shown as a representative.

On the other hand, the RAS internal signal is supplied to the WE control circuit WE CONTROL and the CAS control circuit CAS CONTROL (CKT). For example, the automatic refresh mode (CBR), the test mode (WCBR), and the like are identified based on the determination of the input order of the RASB signal, the CASB signal, and the WEB signal. In the test mode, the test circuit TE
ST FUNCTION is activated, and a test function is set according to a specific address signal supplied in each of the public / standardized test mode and the private test mode.

X address buffer X-ADDRES
Of the address signals taken in S BUFFER,
An address signal instructing selection of a memory mat is transmitted to a mat selection circuit MSiL / R, and from there, a plurality of memory mats MEMORY MA provided in each memory array.
Any one of T is selected. Here, CS provided corresponding to the memory mat MEMORY MAT is a common source switch MOSFET.

The four main amplifiers MA correspond to four pairs of complementary data lines (4 bits) from a total of eight memory mats provided symmetrically with respect to the main amplifiers MA.
One of the eight memory mats is selected by the memory mat selection signal MSiL / R. The unit mat control circuit UMC performs such a selection operation. In the figure, four pairs of main amplifiers MA are exemplarily shown as one set, and the remaining three sets of main amplifiers are shown as black boxes by broken lines.

The mat selection circuit MSiL / R forms four types of selection signals MS0L / R to MS3L / R.
For example, when MS0L is formed, 4 corresponding to MS0L
Two memory mats are selected. Each of these four memory mats MS0L has a 4-bit input / output node, which corresponds to each of the four main amplifiers MA.

CAS system control circuit CAS CO
NTROL (CKT) is used to receive the signal CASB and form various Y-system control signals. Signal CAS
The address signal taken into the Y address buffer Y-ADDRESS BUFFER in synchronization with the change of B to the low level is the Y-system redundancy circuit Y-REDUNDANCY.
Supplied to CKT. Here, the stored defective address is compared to determine whether or not the redundant circuit is switched.

The result and the address signal are supplied to the Y-system predecoder Y-PREDEC (Y1, AYn1). Here, a predecode signal composed of Yi and AYnl is formed. This predecode signal Yi and AY
nl is supplied to each Y decoder Y-DEC via Y address drivers (final stage) YiB and AYnl provided corresponding to each of the four memory arrays. In the figure, one Y driver YiB, AYn
Only IB is illustratively shown as a representative.

On the other hand, the CAS-based control circuit CA
S CONTROL (CKT) is RAS as described above.
When the test mode is judged from the judgment of the input order of the B signal and the WEB signal, the adjacent test circuits TES
Activates T FUNCTION.

Although not shown in the figure, the bonding pads to which the address signal and the control signal are supplied are collectively arranged in the central portion of the chip. Therefore, the distance from each pad to the corresponding circuit can be shortened and can be made substantially uniform. As a result, by adopting the layout as in this embodiment, the address signal and the control signal are taken in at high speed, and in the case of an address signal composed of a large number of bits, the skew generated between the address signals composed of a large number of bits is eliminated. Can be kept to a minimum.

As shown in the figure, a sense amplifier (SA)
The power supply VDL for peripherals and the power supply VCL for peripheral circuits are also arranged in the center of the chip. As a result, various voltages can be supplied to the circuits arranged at the four corners of the chip by equidistant and short wiring. Further, although not shown according to each circuit, capacitors having a relatively large capacitance value for stabilizing the voltage, in other words, lowering the power source impedance, are provided dispersed in the circuit along the respective power source wirings. To be

FIG. 3 shows a circuit diagram of an embodiment of the substrate bias generating circuit. The substrate bias generation circuit of this embodiment is a circuit that forms a back bias voltage that is supplied to the second P-type well region in which the input / output circuit is formed and is increased in absolute value, such as -2V. .

In order to form the substrate bias voltage efficiently with low power consumption, the control circuit as described later biases the substrate bias voltage from -2V in absolute value so that the back bias voltage such as -2V is formed. Oscillation pulses OSC and OSCB are intermittently supplied to the next charge pump circuit as when the voltage drops to generate the negative back bias voltage VBB1. Oscillation pulse OSC and OSC
B is made in a phase opposite to each other and non-overlapped by a pulse generation circuit composed of inverter circuits N6 to N9, gate circuits G4 and G5, and an output inverter circuit N10 which form a delay circuit.

Oscillation pulses OSC and OS having opposite phases to each other.
The CB is transmitted to the two charge pump circuits that alternately operate, and the preliminary operation and the output operation are alternately performed to efficiently generate the negative voltage. That is, the oscillation pulse OSC
Is low level, the outputs of the inverter circuits N1 and N2 become high level. At this time, the negative voltage of the potential of the node A causes the P-channel MOSFETs Q1 and Q2 to be in the ON state, so that the capacitors C1 and X2 are precharged. Be seen.

At this time, the oscillation pulse OSCB is at a high level, and the low level of the output signal of the inverter circuit N3 causes the holding voltage of the capacitor C3 charged up in the preceding cycle to be a negative voltage, and the P-channel type switch MOSFET Q7. Is turned on. As a result, similarly, due to the low level of the inverter circuit N4 corresponding to the high level of the oscillation pulse OSCB, the negative voltage of the node A of the capacitor C4 is switched MOSFETQ.
It is output as a back bias voltage VBB1 through 7.

Next, when the oscillation pulse OSC changes to the high level, the output signal of the inverter circuit N1 changes to the low level, and the holding voltage of the capacitor C3 becomes a negative voltage by the above-mentioned charge-up operation and the P channel The type switch MOSFET Q3 is turned on. In synchronization with this, the output signal of the inverter circuit N2 also changes to low level, and the negative voltage of the node B of the capacitor C2 is output as the back bias voltage VBB1 through the switch MOSFET Q3 in the ON state.

At this time, the oscillation pulse OSCB is at the low level, and the P-channel MOSFETs Q5 and Q6 are turned on by the high level of the output signals of the inverter circuits N3 and N4 and the negative voltage of the node B.
The capacitors C3 and Q4 are being charged up. Hereinafter, when the oscillation pulses OSC and OSCB change, a negative voltage output operation is performed on one side and a charge-up operation is performed on the other side to perform an efficient charge pump operation.

M3 is a metal wire formed by Matusu slice, and the MOSFETs Q3 and Q7 can be diode-connected. At this time, the negative voltage formed by the capacitors C1 and C3 is invalidated, and the negative voltage formed by the capacitor C2 or C4 is reduced by the threshold voltage of the MOSFETs Q3 and Q7 and output.

The substrate bias generating circuit for supplying a bias voltage such as -1V to the first P-type well region in which the memory array is formed is composed of a circuit similar to the circuit of FIG. However, inverter circuits N1 to N4 that form a high level for precharging the capacitors C1 to C4
Has its operating voltage a constant voltage formed by an internal voltage down converter. For example, when the power supply voltage supplied from the external terminal is 5V, the constant voltage VDL such as about 3.3V is set as described above, and when the power supply voltage supplied from the external terminal is about 3.3V, the internal voltage down converter is used. About 2.2 formed
A constant voltage VDL of about V is set.

As described above, when the power supply voltage VCCE supplied from the external terminal is about 5V and the internal voltage down converter VDL is about 3.3V, the bias voltage supplied to the first P-type well region is formed. In the charge pump circuit described above, the wiring of M3 is connected to the above MOSFETs Q3 and Q7 in the diode form by the master slice method. This allows these MOSFETs Q3 and Q
By utilizing the level decrease due to the threshold voltage of 4, the absolutely small bias voltage such as -1V is formed.

Power supply voltage VCCE supplied from an external terminal
Is about 3.3V, and the internal step-down circuit VDL is about 2.2.
In a charge pump circuit that forms a bias voltage supplied to the first P-type well region at a low voltage such as V, the negative voltage formed by the capacitors C1 and C3 by the wiring of M3 by the master slice method described above. Form the switching signal of these MOSFETQ
3 and Q7 are switch-controlled to efficiently form a back bias voltage such as -1V as described above even when the voltage is low as described above.

The gate circuits G1 to G3 are intermittently oscillated by the combination of signals supplied to their inputs so that the substrate bias voltage becomes -2 V as described above.
And output OSCB. As a result, useless current consumption is suppressed and the substrate bias voltage is made constant. Further, as will be described later, when the burn-in test is performed by increasing the power supply voltage, the substrate bias voltage is increased in response to the increase in the power supply voltage. Also in the substrate bias circuit that forms a substrate bias voltage such as -1V of the memory array, a control circuit for increasing the bias voltage in correspondence with the constant voltage and burn-in test is also provided.

FIG. 4 shows a schematic element structure sectional view in the dynamic RAM according to the present invention. An example using an N-type substrate (N-SUB) is shown in FIG. 7A, and an example using a P-type substrate (P-SUB) is shown in FIG.

In FIG. 7A, an N type substrate is used. That is, in this embodiment, the triple well structure is formed by the N-type substrate. A deep P-type well PWELL is formed on the N-type substrate N-SUB. This deep P-type well PW
N channel type MO that constitutes the input / output unit in the ELL
A third P-type well region BP in which the SFET is formed, and P
An N type well region BN in which a channel type MOSFET is formed is formed.

P channel type M constituting the input / output section
The power supply voltage VCC or the boosted voltage VCH is supplied to the N-type well region BN in which the OSFET is formed. Although not shown, the P-type well region BP in which the N-channel MOSFET forming the input / output unit is formed is supplied with a bias voltage such as −2V formed by the substrate bias generating circuit as described above. . In the deep P-type well region where the input / output section is formed, the ground potential VS of the circuit is formed.
S is supplied. The power supply voltage VCC is supplied to the N-type well region BN forming the galile ring to absorb minority carriers in the deep P-type well region PWELL.

N-channel type MOS constituting peripheral circuits
The FET and the P-channel type MOSFET have a third P-type well region BP and an N-type formed in a deep P-type well region PWELL which is separated from the deep P-type well region which constitutes the input / output section as described above. It is formed in the well region BP. P-channel type MOSFET forming a peripheral circuit
The power supply voltage VCC or the boosted voltage VCH is supplied to the N-type well region BN in which is formed. For example, as will be described later, a P-channel type MOSFE forming a word driver that forms a word line selection signal by the boosted voltage VCH.
A boosted voltage VC is applied to the third P-type well region where T is formed.
H is supplied, and the voltage VCC is supplied to the N-type well region in which the P-channel MOSFET forming the circuit that operates with the internal power supply voltage such as the decoder is formed. Although not shown, the circuit ground potential VSS is applied to the third P-type well region in which the N-channel MOSFET is formed.

Then, the first P-type well region BP in which the memory array is formed is formed in the N substrate N-SUB and is supplied with the substrate bias voltage VBB such as -1V. Around the memory array is provided a guard ring composed of a pair of deep P-type well regions and an N-type well region BN sandwiched by the N-type substrate N-SUB.

A P-type substrate is used in FIG. In other words, in this embodiment, the P-type substrate has a triple well structure. A deep N-type well NWELL is formed on the P-type substrate P-SUB. This deep N-type well NW
N channel type MO that constitutes the input / output unit in the ELL
A third P-type well region BP in which the SFET is formed, and P
An N type well region BN in which a channel type MOSFET is formed is formed.

P-channel type M which constitutes the input / output section
The power supply voltage VCC or the boosted voltage VCH is supplied to the N-type well region BN in which the OSFET is formed. Although not shown, the P-type well region BP in which the N-channel MOSFET forming the input / output unit is formed is supplied with a bias voltage such as −2V formed by the substrate bias generating circuit as described above. . The power supply voltage VCC is supplied to the deep P-type well region where the input / output unit is formed. N-type well region B forming the galile ring
The power supply voltage VCC is supplied to N, and the P-type well region B
The ground potential VSS of the circuit is applied to P. Substrate P-S
The circuit ground potential VSS is also applied to UB.

N-channel type MOS constituting peripheral circuits
FET and P-channel MOSFET are P-type substrate P-
The third P-type well region BP and the N-type well region BP are formed on the SUB. N-type well region B in which a P-channel MOSFET forming a peripheral circuit is formed
The power supply voltage VCC or the boosted voltage VCH is supplied to N. For example, as will be described later, the boosted voltage VCH is supplied to the third P-type well region in which the P-channel type MOSFET forming the word driver for forming the selection signal of the word line is formed by the boosted voltage VCH, and the decoder etc. The voltage VCC is supplied to the N-type well region in which the P-channel MOSFET forming the circuit that operates with the internal power supply voltage is formed. And, though not shown,
The circuit ground potential VSS is supplied to the third P-type well region BP in which the N-channel MOSFET is formed.

The memory array is formed in the first P-type well region BP formed in the deep N-type well region. A substrate bias voltage VBB such as -1V is supplied to the first P-type well region BP. Around the memory array, a guard ring is provided which is composed of a shallow N-type well region BN and a pair of shallow P-type well regions formed so as to sandwich the shallow N-type well region BN. The power supply voltage VCC is supplied to the N-type well region BN, and the ground potential VSS of the circuit is supplied to the P-type well region BP.

5 to 7 are circuit diagrams showing one embodiment of the memory mat portion in the dynamic RAM according to the present invention. The memory mat of this embodiment is
As described above, the shared sense amplifier system is adopted. Therefore, two memory mats are arranged around the sense amplifier.

FIG. 5 shows a P-channel type amplification MOSFET which constitutes a sense amplifier, and a switch MOSFET which connects the precharge circuit and the sense amplifier to the data line of the memory array provided on the left side thereof. The memory array is formed in the first P-type well region BP1. A substrate bias voltage having an absolute small value such as -1V is supplied to the first P-type well region as described above.

The P-channel type amplification MOSFET constituting the sense amplifier is formed in the N-type well region BN.
Then, an N-channel type switch MOSF for connecting the data line of the left side memory array and the sense amplifier.
N channel type precharge MOSFET for short-circuiting ET and data lines and supplying half precharge voltage
Further, the N-channel type amplification MOSFET constituting the sense amplifier shown in FIG. 6 is formed in the third P-type well region. As described above, the ground potential of the circuit is applied to the third P-type well region.

FIG. 6 shows the N-channel amplification MO.
The SFET, the P-channel type amplification MOSFET, and the N-channel type switch MOSFET for connecting the right side memory array, its data line and the sense amplifier are shown. In this embodiment, in order to compensate the input offset of the sense amplifier, when the sense amplifier starts the amplification operation, the N-channel type amplification MOSFET is activated first,
The variation in the threshold voltage between the gate and the source of the N-channel type amplification MOSFET is compensated by using the capacitor provided on the source side.

That is, the source potential is pulled down to the ground potential side through the capacitor to perform the first stage amplification operation,
N channel type MOS provided between the source of the amplification MOSFET and the common source line when the amplification signal is increased
The FET is turned on to start the normal amplification operation. After that, the P-channel type amplification MOSFET is brought into an operating state, and the high level lowered by the amplification operation of the N-channel type amplification MOSFET as described above is raised to the power supply voltage level.

The P-channel type amplification MOSFET is
The N-channel type switch MOSFET formed in the N-type well region and connecting the data line of the memory array on the right side and the sense amplifier is formed in the third P-type well region to which the ground potential of the circuit is applied. Then, the memory array is formed in the first P-type well region. A substrate bias voltage such as -1V is supplied to the first P-type well region as described above.

FIG. 7 shows the memory array and column switch on the right side. As in this embodiment, since the column switch is provided at the right end of the two memory arrays formed by sandwiching the sense amplifier, the amplified signal of the memory array on the left side is deselected at that time on the right side. The data lines of the memory array are used as signal lines and connected to the input / output lines. That is, when reading the memory array on the left side, the switch MOSFET for the memory array on the right side is turned on after the sense amplifier is activated, and the data line is used as a signal line to be transmitted to the input / output line. It is something to do. When reading from the memory array on the right side, the signal on the data line is transmitted to the input / output line through the selected column switch MOSFET. The column switch as above is N
It is composed of a channel type MOSFET. These column switch MOSFETs are also formed in the third P-type well region and are supplied with a bias voltage such as the ground potential of the circuit.

FIG. 8 shows a circuit diagram of an embodiment of the word driver. In the word driver, in order to perform full write to the storage capacitor, the potential of the word line is set higher than the operating voltage of the sense amplifier by the threshold voltage of the address selecting MOSFET of the memory cell. There is a need. Therefore, the operating voltage is VC
The voltage is boosted like H. On the other hand, since the decoder or the like uses the internal step-down voltage, it is necessary to perform level conversion.

In this embodiment, the gate circuit G1 decodes the signals A to C to form a memory array selection signal. Since this signal is a voltage lower than the boosted voltage VCH as described above, the latch-type gate circuits G2 and G3 and the inverter circuit N2 that operate at the boosted voltage VCH.
Form a signal WPH whose level has been converted.

In the selected memory array, the signal WPH goes to a high level like VCH to turn off the P-channel MOSFET. Then, an N channel type MO that receives the decoder outputs DEC1 to DEC3
All the SFETs are turned on and a low level selection signal is formed. As a result, the P-channel MOSFET forming the word driver is turned on, and the word line WLi is set to a high level like VCH. The P-channel MOSFET that receives this word line WLi is
Since it is a feedback P-channel MOSFET and its conductance is formed small, the input signal of the word driver is set to a low level by the decoder outputs DEC1 to DEC3.

In the non-selected word line, the feedback P-channel MOSFET for receiving the low level of the word line is in the ON state, and the input signal of the word driver is VCH.
It is fixed to. In the non-selected memory array, the signal WP
H is set to low level and the input of the word driver is set to V
It is fixed at a high level like CH.

In such a peripheral circuit, the high voltage VC
P-channel MOSFET for outputting H level signal
A high voltage VCH corresponding thereto is supplied to the N-type well region BN in which is formed. That is, as shown in FIG. 3, in the N-type well region, a bias voltage such as VCC / VCH is applied corresponding to the operating voltage supplied to the source of the P-channel MOSFET in which it is formed. .

A circuit diagram of an embodiment of the output buffer is shown in FIG. This output buffer is composed of an output control circuit and an output circuit. The output circuit is a P-channel type output MOSFET Q1 and an N-channel type output MOSF.
It is composed of a CMOS circuit composed of ETQ2. The output control circuit includes gate circuits G1 and G2, inverter circuits N1 to N3, and resistors R1 and R2.

The N-channel output MOSFET Q2
Is formed in the second P-type well region BP2, and the drain of the output MOSFET Q2 and the second P-type well region are not forward biased with respect to the undershoot transmitted from the external terminal IO1. For example -2
A substrate bias voltage VBB1 such as V is supplied. P
The channel type output MOSFET Q1 is formed in the N type well region, and its source is supplied with the power supply voltage VCCE. Therefore, although not shown, the power supply voltage VCCE is supplied as a bias voltage to the N-type well region.

On the other hand, the gate circuits G1 and G2 that form the control circuit and the N-channel MOSFETs that form the inverter circuits N1 to N3 are formed in the third P-type well region and have the above-mentioned circuit configuration. The ground potential is applied as the bias voltage. The P-channel MOSFET that constitutes the control circuit is formed in the N-type well region, and the power supply voltage is applied as a bias voltage corresponding to its operating voltage.

FIG. 10 is a characteristic diagram showing the relationship between the external voltage and the internal voltage in one embodiment of the dynamic RAM according to the present invention. In this embodiment, an example using a power supply voltage VCCE of about 3.3V from the external terminal is shown. When the power supply voltage VCCE is 3.3V, the internal voltage is made constant in the shaded area A for operation. That is, the power supply voltage VCCE is 3.3V.
The substrate voltage Vbbmat of the memory array is stabilized even if the voltage fluctuates within a permissible range with respect to. The input / output unit may be stabilized like the substrate voltage Vbb (I / O1), or may be changed according to the power supply voltage like the substrate voltage Vbb (I / O2).

Further, in order to efficiently perform the acceleration test for the burn-in (aging) test, the power supply voltage VCCE
When the voltage is increased beyond the normal allowable range, the internal voltage is also increased as the power supply voltage increases. That is,
When the power supply voltage for the burn-in test is set as in the shaded area B, the internal voltage is also increased accordingly.

FIG. 11 shows a refresh characteristic diagram for explaining the present invention. Regarding the refresh cycle, it is necessary to match the refresh cycle with the one having the worst refresh characteristic among many memory cells such as about 16 Mbits or 64 Mbits. In the figure, it will be understood that the refresh time tREF surely becomes longer as the substrate bias voltage Vbb is made shallower.

That is, even in memory cells having the same characteristics, if the substrate bias voltage is made smaller in absolute value, the voltage applied between the source and drain connected to the capacitor and the substrate becomes smaller. The leakage current is also reduced. This is because as the storage capacity is increased to about 16 M or 64 M bits, the capacity value of the storage capacitor is correspondingly reduced, and the leak current cannot be ignored. With the above-mentioned large storage capacity, it is almost impossible to make the characteristics of all the memory cells uniform, and there are some 1-bit or several-bit memory cells with a short refresh time. However, since the refresh cycle is set correspondingly, the current consumption increases.

According to the present invention, the substrate bias voltage is set to the necessary minimum, the voltage applied between the source and drain connected to the capacitor of the memory cell and the substrate is reduced, and the leak current is also reduced. The refresh cycle of the dynamic RAM having a large storage capacity can be significantly lengthened, and as a result, a significant reduction in power consumption can be achieved.

The operational effects obtained from the above embodiment are as follows. That is, (1) A back bias voltage, which is a voltage that is small in absolute value and is optimum for the refresh characteristic, is supplied to the P-type well section in which the memory array section in which the dynamic memory cells are arranged in a matrix is formed. , N-channel type MOS of input circuit or output circuit connected to external terminal
The P-type well portion in which the FET is formed is supplied with a back bias voltage that is increased in absolute value in consideration of the undershoot voltage, thereby reducing the leak current and improving the refresh characteristic, and at the same time, it is connected to the external terminal. The effect of being able to take measures against undershoot can be obtained in the P-type well region in which the corresponding input circuit or output circuit is formed.

(2) By forming an N-channel MOSFET other than the N-channel MOSFETs of the memory array section and the input circuit or the output circuit in the third P-type well region and supplying the circuit ground potential, The effect that the operation can be speeded up even with the voltage is obtained.

(3) By forming the first back bias voltage supplied to the first P-type well region by a charge pump circuit using a pulse signal formed by a constant internal voltage, The effect that the substrate bias voltage can be made constant can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the layout of the dynamic RAM is not limited to the example of FIG. 1 described above, and various embodiments can be adopted. Similarly, the substrate bias generating circuit and other internal circuits can adopt various embodiments. Bias voltage is generated by internal circuit,
It may be configured to be supplied from the outside as needed. The P-type well region in which the peripheral circuit is formed may be supplied with the same bias voltage as that of the memory array or the same bias voltage as that of the input / output circuit, in addition to supplying the ground potential of the circuit as described above.

In addition to the dynamic RAM, the present invention is
The present invention can be widely used for semiconductor integrated circuit devices such as digital integrated circuits having a memory array in which dynamic memory cells are arranged in a matrix.

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the P-type well portion in which the memory array portion in which the dynamic type memory cells are arranged in a matrix is formed is supplied with a back bias voltage which is a voltage that is small in absolute value and is optimum for its refresh characteristic, and the external terminal N of input circuit or output circuit connected to
The P-type well portion in which the channel-type MOSFET is formed is supplied with a back bias voltage that is increased in absolute value in consideration of the undershoot voltage, thereby reducing leak current and improving refresh characteristics. P where an input circuit or output circuit corresponding to the terminal is formed
An undershoot countermeasure can be applied to the mold well region.

The N-channel MOSFETs other than the N-channel MOSFETs of the memory array section and the input circuit or the output circuit are formed in the third P-type well region, and the ground potential of the circuit is supplied so that a low voltage can be obtained. The operation speed can be increased.

The first back bias voltage supplied to the first P-type well region is formed by the charge pump circuit using the pulse signal formed by the constant internal voltage, so that the substrate bias voltage is increased. The constant voltage can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a block diagram of an embodiment focusing on a control signal in a dynamic RAM to which the present invention is applied.

FIG. 3 is a circuit diagram showing an embodiment of a substrate bias generation circuit.

FIG. 4 is a schematic element structure sectional view showing one embodiment of a dynamic RAM according to the present invention.

FIG. 5 is a partial circuit diagram showing an embodiment of a memory mat section in the dynamic RAM according to the present invention.

FIG. 6 is another partial circuit diagram showing an embodiment of the memory mat section in the dynamic RAM according to the present invention.

FIG. 7 is a remaining partial circuit diagram showing one embodiment of the memory mat section in the dynamic RAM according to the present invention.

FIG. 8 is a circuit diagram showing an embodiment of a word driver in the dynamic RAM according to the present invention.

FIG. 9 is a circuit diagram showing an embodiment of an output buffer in the dynamic RAM according to the present invention.

FIG. 10 is a characteristic diagram showing a relationship between an external voltage and an internal voltage showing an embodiment in the dynamic RAM according to the present invention.

FIG. 11 is a refresh characteristic diagram for explaining the present invention.

[Explanation of symbols]

MEMORY MAT ... memory mat, SA ... sense amplifier, Y-DECODER ... Y selection circuit (decoder),
X-ADDRESS BUFFER ... X address buffer, X-REDUNDANCY CKT ... X redundant circuit,
X-ADDRESS DRIVER ... X address driver, LOGIC STEP ... logic stage, RAS CKT ...
RAS system control circuit, WE SYSTEM ... WE system control circuit, DIN BUFFER ... Data input buffer, VC
L LIMITER ... Internal step-down circuit, Y-ADDRES
S BUFFER ... Y address buffer, Y-REDU
NDANCE ... Y redundant circuit, Y-ADDRESS DR
IVER ... Y address driver, CAS CKT ... CA
S system control circuit, TEST FUNCTION ... test circuit, VDL LIMITER ... internal step-down circuit, DV2-
DV3 ... X address driver, X-DECODER ... X
Decoder, DV1 ... Y address driver, VCH ... Boosted voltage generation circuit, MA ... Main amplifier, VBB ... Substrate voltage generation circuit, OUTPUT BUFFER ... Data output buffer, Q1 to Q6 ... MOSFET, N1 to N10 ... Inverter circuit, G1 to G5 ... Gate circuits, C1-C4 ...
Capacitors. N-SUB ... N-type substrate, P-SUB ... P-type substrate, PWELL ... Deep P-type well region, NWELL ...
Deep N-type well region, BP1 ... First P-type well region,
BP2 ... second P-type well region, BP3 ... third P-type well region, BN ... N-type well region, BP ... P-type well region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 21/8238 27/092 H01L 27/08 321 B

Claims (6)

[Claims] 1. A first P in which a memory array section in which dynamic memory cells are arranged in a matrix is formed.
Type well section and a second P-type well section in which an N-channel MOSFET of an input circuit or an output circuit connected to an external terminal is formed, and the first P-type well section is optimal for refresh characteristics. The first back bias voltage having a small absolute value is supplied, and the second back bias voltage having a large absolute value is supplied to the second P-type well portion in consideration of the undershoot voltage at the external terminal. A semiconductor integrated circuit device characterized by the following. 2. A first P in which a memory array section in which dynamic memory cells are arranged in a matrix is formed.
A second P-type well portion in which an N-channel MOSFET of an input circuit or an output circuit connected to an external terminal is formed, and the memory array portion and the N-channel MOSFET of the input circuit or the output circuit Including a third P-type well region in which the N-channel MOSFET is formed, and the first P-type well portion is supplied with a first back bias voltage having a small absolute value which is optimum for refresh characteristics. The second P-type well portion is supplied with a second back-bias voltage that is increased in absolute value in consideration of the undershoot voltage at the external terminal, and the ground potential of the circuit is supplied to the third P-type well region. A semiconductor integrated circuit device characterized by being supplied. 3. A first back bias voltage supplied to the first P-type well region and a second back bias voltage supplied to the second P-type well region are respectively formed inside. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is generated by the first and second charge pump circuits. 4. The first back bias voltage supplied to the first P-type well region is formed by a first charge pump circuit using a pulse signal formed by a constant internal voltage. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a semiconductor integrated circuit device. 5. The first P-type well region is formed on an N-type semiconductor substrate, and the second and third P-type well regions are deep P-type formed on the N-type semiconductor substrate. 3. The deep P-type well region is also formed in the well region, and the N-type well region forming the P-channel type MOSFET is also formed in the deep P-type well region.
Semiconductor integrated circuit device. 6. The first P-type well region is formed in a deep first N-type well region formed on a P-type semiconductor substrate, and the second P-type well region is formed of a P-type semiconductor. It is formed in a deep second N-type well region formed on the substrate, and an N-type well region for forming a P-channel MOSFET is also formed in the deep second N-type well region. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is provided.