JPH02207564A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the malfunction of data reading out, circuit operation, etc., by a method wherein the substrate potential is fed to the peripheral part near a sense amplifier circuit. CONSTITUTION:When a word line 30 of one of divided memory cell array 2A is selected, the data in minor potential of a memory cell M are read out of the whole complementary data line 37 of the memory cell array 2A. Next, all of respective sense amplifier circuits of sense up circuit 4A are driven by the sense amplifier driving signals phip transmitted from a timing producing circuit 6 conforming to the control signals from an external device. Through these procedures, the data read out on the complementary line 37 are amplified and later, the data selected by a column select decoder circuit 3A are outputted out of a DRAM 1. When the sense amplifier circuit 4A is driven, the substrate potential VBB in a p type well region 21 is boosted, but a wiring 40 is extended over the region 21 to actively feed the region 21 with the substrate potential VBB so that the region 21 may be instantaneously fed back with the substrate potential VBB. Through these procedures, the inversion of data, the multifunction of data reading out and peripheral circuit operation are reduced, thereby enhancing the electrical reliability.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular, to a DRA
M(Dyna+mic Rando+a Access
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having a memory.

[Conventional technology]

DRAM memory cell is MO8FET for memory cell selection
and an information storage capacitive element in series.

This memory cell is placed at the intersection of a data line and a word line.

The data line is connected to one semiconductor region of each memory cell selection MO3FET of a plurality of memory cells arranged in its extending direction, and is also connected to a sense amplifier circuit. The data line reads minute potential information written in the information storage capacitive element of the memory cell selected by the word line among the plurality of memory cells.

The sense amplifier circuit is configured to amplify minute potential information read out to the data line and output it to the outside of the device.

This type of DRAM has a built-in substrate potential generation circuit (VS-generator). The substrate potential generation circuit is configured to generate a substrate potential based on a reference potential supplied from outside the device, and to supply this substrate potential to the semiconductor substrate. The reference potential is, for example, the circuit reference potential 0 [
v]. Further, the substrate potential is a negative potential of about -3 [V]. Substrate potential is supplied by n-channel MO8FET
p between the source region, drain region, and the semiconductor substrate.
Parasitic capacitance formed at the n-junction can be reduced. Reducing the parasitic capacitance increases the signal transmission speed and, as a result, increases the operating speed of the DRAM. In addition, when supplying substrate potential, n-channel MO8FE
Holes, which are majority carriers of the electron-hole pairs generated during T operation, are drawn toward the depth of the semiconductor substrate.
Substrate current flows.

The substrate potential generated by the substrate potential generation circuit is applied to the DRAM.
is supplied in the peripheral area (almost always the outermost area). The substrate potential is transmitted from the substrate potential generation circuit to the peripheral area of the DRAM by substrate potential supply wiring. The substrate potential supply wiring is formed of aluminum wiring or a semiconductor region (diffusion layer).

Regarding the substrate potential generation circuit built into DRAM, see, for example, Science Forum Co., Ltd., VLSI Device Handbook, November 28, 1980, No. 29.
It is described on pages 8 and 299.

[Problem to be solved by the invention]

The inventor has developed a DRAM with a large capacity of 1 [Mbitl].
is currently under development. In this DRAM, the memory cell array is divided into a plurality of, for example, four (mat configuration is adopted), and a sense amplifier circuit is arranged at the end of each of the six divided memory cell arrays. When reading information from one memory cell in a divided memory cell array, a DRAM simultaneously operates all sense amplifier circuits placed at the ends of this memory cell array6. 256 [Kbit
], and 512 sense amplifier circuits are arranged, so the information read operation operates the 512 sense amplifier circuits simultaneously. Due to this operation of the sense amplifier circuit, a large amount of substrate current flows from the MOSFETs forming the sense amplifier circuit to the semiconductor substrate. Since the semiconductor substrate has a high resistance, the substrate current locally increases the potential of the semiconductor substrate, particularly the potential of the sense amplifier circuit and its surrounding area. Therefore, noise is generated in the data line due to coupling between the data line and the semiconductor substrate during an information read operation. This noise fluctuates the minute potential information read out to the data line, causing frequent malfunctions such as data inversion during information reading operations. In particular, DRAM operates the sense amplifier circuit under clock control (dynamic operation), so
Unlike SRAM (statie RAM), malfunctions are likely to occur.

Also, substrate current is generated in the operation of decoder circuits other than the sense amplifier circuit, but MOSFETs that operate at -degrees
Since the number of ETs is smaller than that of the sense amplifier circuit, the potential of the semiconductor substrate does not rise to the point where malfunction occurs.

In addition, around the sense amplifier circuit, there are MOSFETs and column select MOSFETs that constitute a column select decoder circuit.
8FET (Y switch) etc. are arranged. Therefore, the electrical characteristics of these MOSFETs vary due to the aforementioned increase in the potential of the semiconductor substrate, resulting in a reduction in operating margin and malfunction.

These problems can be solved to some extent by designing the substrate potential generation circuit so that the substrate potential does not exceed a predetermined value, or by delaying the sense point during operation of the sense amplifier circuit.

However, these solutions involve increasing the operating timing margin of the sense amplifier circuit, etc., which results in a reduction in the operating speed of the DRAM.

An object of the present invention is to provide a technique that can reduce malfunctions such as information read operations and circuit operations and improve electrical reliability in a semiconductor device circuit device having a DRAM.

Another object of the present invention is to provide a technique capable of achieving the above object and increasing the operating speed of the semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that can reduce the number of manufacturing steps to achieve the above object.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) In a semiconductor integrated circuit device having a DRAM,
A substrate potential is supplied near the periphery of the sense amplifier circuit of the DRAM. The substrate potential is supplied from a substrate potential generation circuit built into the DRAM.

(2) The substrate potential is transmitted by a substrate potential supply wiring formed of the same conductive layer as the data line or word line of the DRAM.

[For production]

According to the above-mentioned means (1), when a plurality of sense amplifier circuits operate simultaneously, fluctuations in substrate potential in the sense amplifier circuit area and the surrounding circuit area can be immediately absorbed, so that information It is possible to reduce malfunctions in information read operations such as inversion of , and malfunctions in peripheral circuit operations. As a result, the operating margin during the DRAM information read operation,
Since the operational margin etc. during the operation of the peripheral circuits can be increased, the electrical reliability of the semiconductor integrated circuit device can be improved. Further, since the operation timing margin during the information read operation of the DRAM, the operation timing margin during the operation of the peripheral circuits, etc. can be reduced, the operation speed of the semiconductor integrated circuit device can be increased.

According to the above-mentioned means (2), the substrate potential supply wiring can be formed in the process of forming the data line or the word line, so the semiconductor integration is reduced by the amount corresponding to the process of forming the substrate potential supply wiring. The number of manufacturing steps for the circuit device can be reduced.

The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to a single DRAM.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 1 (block diagram) shows the configuration of a DRAM that is an embodiment of the present invention.

As shown in FIG. 1, the DRAMI has a rectangular plane and is composed of semiconductor pellets made of single crystal silicon.

A memory cell array (M
A) 2 is placed. Although the memory cell array 2 is not particularly limited, it is divided into four memory cell arrays 28 to 2D (a mat configuration is adopted), two above the DRAMI and two below.

Each of the memory cell arrays 2A to 2D has, for example, 256 [K
bit]. In other words, DRAM
The total memory cell array 2 has a large capacity of 1 [Mbit].

A column address decoder circuit (YDEC) is provided between the upper two memory cell arrays 2A and 2B of the DRAM.
) 3A is placed. Similarly, the lower 2 of DRAMl
A column address decoder circuit 3B is arranged between the memory cell arrays 2c and 2D. Each of the column address decoder circuits 3A and 3B is configured to control a column select MISFET via a column select signal line (not shown). Column selection MISF
ET is the complementary data line DL and the common person exit signal line (I10
wire).

A sense amplifier circuit (SA) 4 is provided between each of the memory cell arrays 2A and 2B and the column address decoder circuit 3A.
A and 4B are arranged.

A sense amplifier circuit 4C14D is provided between each of the memory cell arrays 2C12D and the column address decoder circuit 3B.
are arranged. In other words, sense amplifier circuit 4
A to 4D are divided memory cell arrays 2A to 2, respectively.
The DRAM of this embodiment is arranged at each end of D.
Although I is not particularly limited, the sense amplifier circuits 4 are arranged centrally in the center thereof. The sense amplifier circuit 4 (each of the divided sense amplifier circuits 4A to 4D) is constituted by an assembly of a plurality of sense amplifier circuits, for example, 512 sense amplifier circuits. The complementary data lines (two data lines) DL extend in the column direction from one side of each sense amplifier circuit to each memory cell array 2. In other words, the DRAM in this embodiment employs a folded bit line method, although it is not particularly limited.

A row address decoder circuit (XDEC) 5A is arranged between memory cell arrays 2A and 2C. The row address decoder circuit 5A is connected to the memory cell arrays 2A and 2.
It is configured to select a word line WL extending in the row direction in C. Similarly, a row address decoder circuit 5B is arranged between memory cell arrays 2B and 2D. Each of the row address decoder circuits 5A and 5B is configured in a two-word line division method, although this is not particularly limited.

A timing generation circuit (TG) 6° data input buffer circuit (D□NB) 7 is arranged in the upper periphery of the memory cell arrays 2A and 2B of the DRAMI, respectively.

The timing generation circuit 6 receives a control signal RA from outside the device.
This circuit generates various timing signals necessary to control the operation of each circuit based on S, CAS, and WE. A row address buffer circuit (XADB) is located around the lower side of the memory cell arrays 2C and 2D of DRAM1.
8, a column address buffer circuit (YADB) 9, and a substrate potential generation circuit (V, lIG, . . . ) 10 are arranged. The substrate potential generation circuit 10 generates a substrate potential v811 based on a reference potential Vss supplied from outside the device, and converts this substrate potential v11. is configured to supply the DRAMI semiconductor substrate (20). The reference potential Vss is, for example, a circuit reference potential of 0 [V].

Also, the substrate potential V. is a negative potential of about -2.5 to -3.5 [V]. As described above, the supply of the substrate potential V a s+ can reduce the parasitic capacitance formed at the pn junction between the source region and drain region of the n-channel MISFET and the semiconductor substrate. Reducing the parasitic capacitance increases the signal transmission speed, and as a result, it is possible to increase the operating speed of the DRAMI. Further, supplying the substrate potential v, , can draw minority carriers generated during operation of the n-channel MISFET in the depth direction of the semiconductor substrate.

In other words, it is possible to reduce the possibility that minority carriers are captured by the information storage capacitive element of the memory cell, and to reduce the destruction of information due to the minority carriers.

Next, each main part of the above-mentioned DRAMI memory cell array 2° sense amplifier circuit 4 will be briefly explained using FIG. 2 (main part equivalent circuit diagram).

Each sense amplifier circuit SA of the sense amplifier circuit 4 has 2
It has a structure in which latched inverter circuits are used. This sense amplifier circuit SA is arranged at each intersection of complementary data lines DL, DL extending in the column direction, sense amplifier drive signal line SL extending in the row direction, and common source line C8.

The inverter circuit is composed of an n-channel MISFET and a p-channel/L/MISFET (CMOS>TE).The sense amplifier drive signal line SL is a p-channel MISFE driven by a sense amplifier drive signal φ.
It is connected to power supply potential Vcc with T interposed therebetween. The power supply potential Vcc is, for example, a circuit operating potential of 5 [V]. The common source line C8 is a drive signal φ.

An n-channel MISFET controlled by φ and an n-channel MISFET controlled by φ are interposed in parallel and connected to the reference potential Vss.

Memory cells M are arranged at intersections between complementary data lines DL (or lines) extending in the column direction of the memory cell array 2 and word lines WL extending in the row direction. The memory cell M is constituted by a series circuit of a memory cell selection MISFETQ and an information storage capacitive element C. This memory cell selection MISFETQ is composed of an n-channel. One semiconductor region of the memory cell selection MISFETQ is connected to a complementary data line DL. The other semiconductor region is connected to one electrode of the information storage capacitive element C, and the gate electrode is connected to the word line WL.

The other electrode of the information storage capacitive element C has a power supply voltage of 1/2V.
Connected to cc. This power supply voltage 1/2 Vcc has a potential of approximately 2.2 mm between the power supply voltage Vcc and the reference voltage ■ss.
It is 5 [V].

Next, we briefly explain each of the memory cell M of the DRAMI mentioned above, the p-channel MISFET constituting the sense amplifier circuit 4, etc., and the area around the sense amplifier circuit 4 using FIG. Explain.

As shown in FIG. 3, the DRAMI is composed of a p" type (or n- type) semiconductor substrate 20 made of single crystal silicon.

The DRAMI memory cell M is provided on the main surface of a p'' type well region 21 formed on the main surface of the semiconductor substrate 20, as shown on the left side of FIG. The periphery is defined by a p-type channel stopper region 24 .

N-channel MISFE for memory cell selection of memory cell M
TQ is a p-type well region 21. Gate insulating film 29. A gate electrode 30, a pair of n-type semiconductor regions 31 and a pair of n-type semiconductor regions 33, which are source and drain regions.
It is made up of. This n-channel M for memory cell selection
ISFETQ has an LDD structure. The gate electrode 30 is formed in a step of forming a second layer of gate material in the manufacturing process, and is made of, for example, a polycrystalline silicon film. The word line 30 extending through the memory cell array 2 is formed of the same conductive layer as the gate electrode 30.

The information storage capacitive element C of the memory cell M is composed of an n-type semiconductor region 25 as one electrode, a dielectric @26, and a plate electrode 27 as the other electrode.

This information storage capacitive element C has a planar structure, although it is not limited thereto. The plate electrode 27 is formed in the step of forming the first layer of gate material in the manufacturing process.
For example, it is formed of a polycrystalline silicon film. Plate electrode 2
The above-mentioned word line 3 is formed on 7 with a glabella insulating film 28 interposed therebetween.
0 is extended.

n-channel MIS for memory cell selection of this memory cell M
A glabella insulating film 3 is provided on one π-type semiconductor region 33 of the FETQ.
A complementary data line (D
L) 37 is connected. The complementary data line 37 is formed in the first layer wiring formation step in the manufacturing process, and is made of, for example, an aluminum film or an aluminum alloy film. In other words, the complementary data line 37 is formed of a conductive material having a smaller specific resistance value than the word line 30.

A shunt word line (W L ) 40 extending in the same row direction as the word line 30 extends on the memory cell array 2 . The shunt word line 40 is provided on the interlayer insulating film 38 on the complementary data line 37, and is connected to the word line 30 at a predetermined interval. Shunt word line 4
0 is formed in the second layer wiring formation step in the manufacturing process, and is made of the same conductive material as the complementary data line 37, for example. A passivation film 41 is provided on the shunt word line 40.

The p-channel MISFET QP constituting the peripheral circuits such as the sense amplifier circuit 4 is provided on the main surface of a rectangular well region 22 formed on the main surface of the semiconductor substrate 20, as shown in the center of FIG. The p-channel MISFET Qp includes an n-type well region 22, a gate insulating film 29. Gate electrode 30. It is composed of a pair of p-type semiconductor regions 32 and a pair of p-type semiconductor regions 34, which are a source region and a drain region. This p-channel MISFETQp has an LDD structure. A wiring 37 is connected to the square semiconductor region 34 which is the source region or drain region of the p-channel MISFET Qp. This wiring 3? is formed of the same conductive layer as the complementary data line 37.

Further, the n-channel MISFET constituting the peripheral circuit is an n-channel MISFET for memory cell selection of the memory cell M.
Since it has a substantially similar structure to ETQ, the explanation here will be omitted.

The region shown on the right side of FIG. 3 is the region I of FIG. 1 and the portion shown in FIG. 2, that is, the region near the periphery of the sense amplifier circuit 4. In a region near the periphery of the sense amplifier circuit 4, as shown in FIGS. 1 to 3, a substrate potential supply wiring (V
This substrate potential supply wiring 40 extending from all) 40 has a substrate potential V generated by a substrate potential generation circuit 10 disposed below the DRAM1. is configured to actively supply the p-type well region 21 and the semiconductor substrate 20 near the sense amplifier circuit 4. In the most peripheral area of DRAMI, the substrate potential supply wiring 37
or 40 extends in a ring shape, and the substrate potential vI1. is supplied.

As shown in FIG. 3, the substrate potential supply wiring 40 extending near the periphery of the sense amplifier circuit 4 crosses the complementary data line 37 extending between the sense amplifier circuit 4 and the memory cell array 2. Therefore, it is formed in the second layer wiring formation process. This substrate potential supply wiring 40 is connected to the main surface of the p-type well region 21 between a predetermined number of complementary data lines 37 with an intermediate conductive layer 37 and a p'-type semiconductor region 34 interposed therebetween. There is. The intermediate conductive layer 37 is formed in the first layer wiring formation process. The p' type semiconductor region 34 is formed in the same manufacturing process as the p' type semiconductor region 34 which is the source region and drain region of the p channel MISFET QP. Further, as shown in FIG. 1, the wiring 40 for supplying substrate potential extending near the periphery of the sense amplifier circuit 4 connects the DRAM 1 with a wire 1137 interposed between the wires 1137 and 1137 before supplying the substrate potential across the shunt word line 40. It is connected to substrate potential supply wiring 37 or 40 which most often extends to the peripheral area.

The information read operation of the DRAMI configured as described above is performed as follows. First, one of the divided parts, for example, the word line (WL) of the memory cell array (MA) 2A.
and shunt word line 40) 30 is selected. By selecting this word line 30, information on the minute potential of the memory cell M is read out to all complementary data lines (DL) 37 of the memory cell array 2A.

Next, a timing generation circuit (TG) 6 generates a sense amplifier drive signal φ2 based on a control signal RAS from outside the device. This sense amplifier drive signal φ2 drives all the sense amplifier circuits of the sense amplifier circuit 4A. By driving this sense amplifier circuit 4A, the information read out to the complementary data line 37 is amplified, and then,
The information selected by the column select decoder circuit (YDEC) 3A is output to the outside of the DRAMI through the common input/output signal line.

When driving the sense amplifier circuit 4A, 512
Since the sense amplifier circuits operate, the substrate potential v8. However, the substrate potential supply wiring 40 extends in this region, and the substrate potential V increases. Because we are actively supplying

The substrate potential can be returned to Va@ in an instant. In addition, D
Even in the most peripheral area of RAMI, the substrate potential v3.
However, since the distance to the sense amplifier circuit 4A is long, it is difficult to instantly suppress the rise in the substrate potential V a from the peripheral region side of the DRAM1 due to substrate resistance and substrate capacitance.

In this way, in DRAM1, the sense amplifier circuit 4
A substrate potential V+e is supplied near the periphery of.

With this configuration, when a plurality of sense amplifier circuits of the sense amplifier circuit 4 operate simultaneously, the p-type well region 21 (
or the substrate potential V of the semiconductor substrate 1).

Since fluctuations in can be absorbed immediately, malfunctions in information read operations such as information inversion, and malfunctions in peripheral circuits such as the sense amplifier circuit 4 and the column address decoder circuit 3 can be reduced.

As a result, it is possible to increase the operating margin during the information read operation of the DRAMI, the operating margin during the operation of the peripheral circuits, etc., thereby improving the electrical reliability of the DRAM1. In addition, since it is possible to reduce the operation timing margin during the read operation of DRAMI information, the operation timing margin during the operation of peripheral circuits, etc., the DRAMI
The operating speed can be increased.

Further, the substrate potential V is transmitted by a substrate potential supply wiring 37 or 40 formed of the same conductive layer as the complementary data line 37 of DRAM1 and the shunt word line 40.

With this configuration, the substrate potential supply wiring 37 or 40 can be formed in the process of forming the complementary data line 37 or the shunt word line 40. The corresponding amount, DRA
The number of MI manufacturing steps can be reduced.

Further, the DRAMI is connected to the substrate potential supply wiring 37.
Alternatively, 40 may be extended to other areas including the surrounding area of the sense amplifier circuit 4, and the substrate potential V may be increased. may be supplied, and the substrate potential vllll may be supplied to the DRAM.
The substrate potential supply wiring 37 or 40 may be directly supplied from the outside of I, or the substrate potential supply wiring 37 or 40 may be configured by the n◆ type semiconductor region 33 or in combination therewith.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and it goes without saying that various changes can be made without departing from the gist of the invention. It is.

For example, the present invention can be applied to a semiconductor integrated circuit device that includes at least a DRAM and other functions such as a logic circuit, and a semiconductor integrated circuit device that includes at least a DRAM and a bipolar transistor.

〔Effect of the invention〕

A brief explanation of the effects that can be obtained by one typical invention among the inventions disclosed in this application is as follows.

In a semiconductor integrated circuit device having a DRAM, electrical reliability can be improved and operation speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a DRAM that is an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the main part of the DRAM, and FIG. 3 is:
FIG. 3 is a sectional view of a main part of the DRAM. In the figure, 1...DRAM, 2...memory cell array. 4...Sense amplifier circuit, 10...Substrate potential generation circuit, 20...Semiconductor substrate, 21.22...Well region, 31.32°33.34...Semiconductor region, 3
7.40...Wiring (wiring for supplying substrate potential), v6°・
...Substrate potential.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device including a DRAM in which a sense amplifier circuit is arranged on the side of a memory cell array, characterized in that a substrate potential is supplied near the periphery of the sense amplifier circuit. Integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the substrate potential is supplied from a substrate potential generation circuit built into the DRAM. 3. The semiconductor integrated circuit device according to claim 2, wherein the substrate potential generation circuit supplies a substrate potential near the periphery of the sense amplifier circuit and also supplies a substrate potential to the periphery of the DRAM. 4. The substrate potential generation circuit generates a substrate potential near the periphery of the sense amplifier circuit by interposing a substrate potential supply wiring formed of the same conductive layer as the data line or word line extending on the memory cell array of the DRAM. 4. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device supplies: