JPS60234356A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the density of integration by a method wherein two layered single crystal silicon layers are provided on the upper part of a semiconductor substrate and then two each of MISFET are composed on an impurity region with high concentration further composing a gate electrode of the other MISFET in another impurity region to be an output part of one MISFET. CONSTITUTION:A flip-flop MISFETQ1 is composed of a gate electrode 4C, a gate insulating film 6, a channel region 9C, a source region 9D and a drain region 9B while another MISFETQ2 is composed of a gate electrode 9B, a gate insulating film 6, a channel region 4B, a source region 4A and a drain region 4C. Besides, a MISFETQS1 is composed of a gate electrode 7A, a gate insulating film 8, a channel region 9E and a source region or drain region 9B, 9F while another MISFETQS2 is composed of a gate electrode 7A, a gate insulating film 6, a channel region 4E and a source region or drain region 4C, 4F. Through these procedures, the number of wirings and connecting holes may be reduced improving the density of integration.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device. The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device in which a semiconductor element is formed in a single-crystal silicon layer.

[Background Art] Semiconductor integrated circuit devices (hereinafter referred to as SRAMs) equipped with static random access memories are becoming highly integrated in order to increase the capacity of information.

An SRAM memory cell generally has about four to six semiconductor elements, and is configured by providing predetermined wiring to these semiconductor elements.

As a result of studies on such technology, the present inventors arranged the semiconductor elements constituting the memory cell to be electrically isolated from each other, and formed wiring regions and connection holes in order to connect them. We have found a problem in that it is extremely difficult to improve the degree of integration of SRAMs because it is necessary to consider the area, the alignment margin necessary for wiring, etc.

Specifically, for example, in an SRAM with a minimum processing size of about 2 [μm], one memory cell has a thickness of 250 to 300 [μm].
It requires an area of about 64 [Kbitl].
Only a certain amount of capacity can be obtained.

Regarding high-density SRAM, for example, the magazine ``
Nikkei Electronics J], September 26, 983 issue, P.
125 and below.

[Object of the Invention] An object of the present invention is to provide technical means that can improve the degree of integration of a semiconductor integrated circuit device.

Another object of the present invention is to provide technical means that can improve the degree of integration of SRAM and increase its capacity.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, two single-crystal silicon layers are provided on the top of a semiconductor substrate with an insulating film interposed therebetween, and high-concentration impurity regions are regularly formed in the single-crystal silicon layer to form at least two MISFs.
ET, and the highly concentrated impurity region serving as the output portion of one MISFET constitutes the gate electrode of the other MISFET. This makes it possible to reduce the number of wires, connection holes, etc. that connect semiconductor elements, thereby improving the degree of integration of the semiconductor integrated circuit device.

Hereinafter, the configuration of the present invention will be explained along with examples.

In this embodiment, the present invention is implemented using two high resistance load elements and four M
The present invention is applied to an SRAM having a memory cell configured with an IS FET.

[Embodiment] FIG. 1 shows an SRAM for explaining an embodiment of the present invention.
FIG. 2 is a schematic isolateral diagram showing a memory cell of FIG.

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

In FIG. 1, WL is a word line extending in the row direction, and is used to control switching elements to be described later.

DL4 and DL are data lines provided extending in the column direction, and are used to transmit charges serving as information to memory cells to be described later.

Ql and Q2 are MI 5FETs, one end of which is connected to the power supply terminal Vcc through a high resistance load element to be described later, and the other end connected to the power supply terminal Vss, R1 and R2 are high resistance load elements, and transmit information. This is for configuring a flip-flop of a memory cell for storage.

Qs 1. Q S 2 has one end connected to data lines DL and DT.
- and the other end is connected to a pair of input/output terminals of the flip-flop, and is controlled by the word line WL.
It is an SFET and is used to configure a switching element of a memory cell.

The memory cells of the SRAM are constituted by a flip-flop having a pair of input/output terminals and a switching element, and a plurality of memory cells are arranged at predetermined intersections between the word line WL and the data lines DL, DL.

Next, a specific configuration of this embodiment will be explained.

FIG. 2 shows an SRAM for explaining one embodiment of the present invention.
Figure 3 is a plan view of the main part showing the memory cell in Figure 2.
-■ Cross-sectional view along the cutting line, Figure 4, is IV- of Figure 2.
The cross-sectional view taken along the IV cutting line, Figure 5, is from ■-■ in Figure 2.
The sectional view taken along the cutting line, FIG. 6, is VI-Vl in FIG.
FIG. 3 is a cross-sectional view taken along a cutting line.

In addition, in Fig. 2, in order to make the drawing easier to see,
An interlayer insulating film to be provided between each conductive layer is not shown.

In FIGS. 2 to 6, l represents a p-type semiconductor substrate. A Vss voltage is connected to this semiconductor substrate l.

2 is an n+ type semiconductor region extending in a predetermined direction and provided on the main surface of the semiconductor substrate 1;
s voltage is applied to it, and is used as wiring.

Reference numeral 3 denotes an insulating film provided above the main surface of the semiconductor substrate 1 and the semiconductor region 2, and is used to electrically isolate the semiconductor element provided above.

3A is a connection hole provided by selectively removing the insulating film 3 above the semiconductor region 2, and is for electrically connecting the semiconductor region 2 and the semiconductor element provided above the insulating film 3. .

Reference numeral 4 denotes a first single-crystal silicon layer provided on the insulating film 3 which is electrically connected to the semiconductor region 2 through the connection hole 3A at a predetermined portion and becomes a semiconductor element formation region;
It is for configuring semiconductor elements such as SFET.

4A is an n+ type semiconductor region that is electrically connected to the semiconductor region 2 through the connection hole 3A and provided in a predetermined portion of the short crystal silicon layer 4, and is used to constitute the source region of the MISFET of the flip-flop. be.

4B is a substantially intrinsic layer (
1) It is a semiconductor region, and the M T of a flip-flop
This is to constitute a region where the channel of the S FET is formed. This substantially intrinsic semiconductor region 4B or the substantially intrinsic semiconductor region described hereinafter may be a P-type semiconductor region.

4C is an n+ type semiconductor region provided in a predetermined portion of the single crystal silicon layer 4, and constitutes the drain region and gate electrode of a MISFET of a flip-flop, or the source region or train region of a MISFET serving as a switching element. It is for.

4D is a substantially intrinsic semiconductor region that is electrically connected to the semiconductor region 2 through the connection hole 3A and provided in a predetermined portion of the single crystal silicon layer 4, and is a high resistance load element R2 of the flip-flop.
It is for configuring.

4E is a substantially intrinsic semiconductor region provided in a predetermined portion of the single crystal silicon layer 4, and is a MISFE which becomes a switching element.
This is for forming a region where a T channel is formed.

4F is an n+ type semiconductor region provided in a predetermined portion of the single crystal silicon layer 4 and electrically connected to a conductive layer provided on the upper part, which will be described later, and is a MISFE which serves as a switching element.
This is for configuring the source region or drain region of T.

These semiconductor regions 4A to 4F are sequentially arranged and provided in the single crystal silicon layer 4.

Reference numeral 5 denotes an insulating film provided above the insulating film 3 between the semiconductor element formation regions, that is, between the single crystal silicon layers 4, and is used to electrically isolate the semiconductor elements. This insulating film 5 may be a silicon oxide film formed by selectively thermally oxidizing the first single crystal silicon layer.

Reference numeral 6 denotes an insulating film provided on the single crystal silicon layer 4, and is mainly used to constitute a gate insulating film of the MI S FET.

7A is a conductive layer provided above the intrinsic semiconductor region 4E through the insulating film 6 or under the intrinsic semiconductor region of the second single crystal silicon layer through the insulating film described later, and serves as a switching element. This is for configuring the gate electrode of the MI5FET.

A conductive layer 7B is electrically connected to the conductive layer 7A in a predetermined direction, extends in that direction, and is provided on the insulating film 5, and is used to constitute a word line WL.

8 is an insulating film provided so as to cover the conductive layers 7A and 7B, and mainly serves as a switching element.
It is used to constitute the gate insulating film of the FET.

Reference numeral 9 denotes an insulating film 5 which is electrically connected at a predetermined portion to a conductive layer provided on the upper part thereof to be described later and becomes a semiconductor element forming region.
, 6.8 is a second single crystal silicon layer provided on top of the silicon layer, and is used to configure a semiconductor element such as a MISFET.

9A is a substantially intrinsic semiconductor region provided in a predetermined portion of the single-crystal silicon layer 9 and electrically connected to a conductive layer provided on the top thereof, which will be described later. It is something.

9B is an n'' type semiconductor region provided in a predetermined portion of the single crystal silicon layer 9, and is
It is for configuring the drain region and its gate electrode of an ET, or the source region or train region of a MISFET serving as a switching element.

9C is a substantially intrinsic semiconductor region provided in a predetermined portion of the single crystal silicon layer 9, and is used to constitute a region where a channel of a MISFET of a flip-flop is formed.

9D is an n+ type semiconductor region provided in a predetermined portion of the single crystal silicon layer 9 and electrically connected to a conductive layer provided on the upper part thereof, which will be described later, and is used to constitute a source region of a MISFET of a flip-flop. be.

9E is a substantially intrinsic semiconductor region provided in a predetermined portion of the single crystal silicon layer 9, and is a MISFE which becomes a switching element.
This is for forming a region where a T channel is formed.

9F is an n+ type semiconductor region provided in a predetermined portion of the single crystal silicon layer 9 and electrically connected to a conductive layer provided on the upper portion, which will be described later, and serves as a switching element.
This is for configuring the source region or drain region of the FET.

These semiconductor regions 9A to 9F are sequentially arranged and provided in the single crystal silicon layer 9.

The M I S F E T Q s of the flip-flop includes a semiconductor region 4C which becomes a gate electrode, and an insulating film 6 which becomes a gate insulating film. A semiconductor region 9G becomes a region where a channel is formed, and a semiconductor region 9D becomes a source region.

It is constituted by a semiconductor region 9B which becomes a drain region.

The flip-flop MISFET Q 2 includes a semiconductor region 9B which becomes a gate electrode, and an insulating film 6 which becomes a gate insulating film. A semiconductor region 4B serves as a region where a channel is formed, and a semiconductor region 4A serves as a source region.

It is constituted by a semiconductor region 4C which becomes a drain region.

M I S F E T Q that becomes a switching element
s + represents a conductive layer 7A that will become a gate electrode, and an insulating film 8 that will become a gate insulating film. It is composed of a semiconductor region 9E that becomes a region where a channel is formed, and semiconductor regions 9B and 9F that become a source region or a drain region.

M I S F E T Q that becomes a switching element
S2 includes a conductive layer 7A that will become a gate electrode, and an insulating film 6 that will become a gate insulating film. It is composed of a semiconductor region 4E that becomes a region where a channel is formed, and semiconductor regions 4C and 4F that become source or drain regions.

Reference numeral 10 denotes an insulating film provided above the insulating film 5 or above the insulating film 8 between the semiconductor element forming regions, that is, between the single crystal silicon layers 9, for electrically isolating the semiconductor elements. This insulating film 10 may be a silicon oxide film formed by selectively thermally oxidizing the second single crystal silicon layer.

Reference numeral 11 denotes an insulating film provided above the single crystal silicon layer 9 and the insulating film 10, and is used to electrically isolate the conductive layer provided above from the semiconductor element.

11A is a connection hole provided by selectively removing the insulating film 1O211 above the single crystal silicon layer 4 and the insulating film 11 above the single crystal silicon layer 9, and is electrically connected to the conductive layer provided above the insulating film 11. It is for making a connection.

12A is the semiconductor region 4F via the connection hole 11A.

This is a conductive layer that is electrically connected to the insulating film 11 and extends in a direction intersecting the conductive layer 7B, and is used to form the data lines DL, DL.

12B is the semiconductor region 9A via the connection hole 11A.

This is a conductive layer that is electrically connected to the insulating film 11 and extends in a direction intersecting the conductive layer 7B, and is electrically connected to the insulating film 11.
This is for configuring wiring to which voltage or Vss voltage is connected.

Note that this embodiment is shown in FIGS. 2 to 6.

Although one memory cell of the SRAM has been illustrated and explained, the memory cell array includes memory cells of m-ml and IV-I.
It may be configured by mirror-reversing (mirror image relationship) in the column direction along the V line and mirror-reversing in the row direction along the line connecting the connection holes 11A in the column direction.

For example, if the S1'tAM according to this embodiment is formed with a minimum processing size of about 2 [μm], the area of one memory cell can be configured to about 60 to 80 [μm2], and it can achieve a remarkable high degree of integration. can be achieved.

Therefore, it is possible to increase the capacity of the SRAM by approximately 1 Mbj, t.

[Effects] As explained above, according to the novel technical means disclosed in the present application, the following effects can be obtained.

(1) Two single-crystal silicon layers are provided on the top of the semiconductor substrate with an insulating film interposed therebetween, and high-concentration impurity regions are regularly formed in the single-crystal silicon layer to form at least two MISFEs.
By configuring the gate electrode of the other MISFET in the highly concentrated impurity region that forms the output section of one MISFET, it is possible to reduce the number of wiring lines, the number of connection holes, etc. that connect semiconductor elements. Therefore, the degree of integration of the semiconductor integrated circuit device can be improved.

(2) According to (1) above, it is possible to reduce the number of wiring lines connecting semiconductor elements, the number of connection holes, etc., so the memory cell area can be reduced and the degree of integration of SRAM can be improved. can.

(3) Using the semiconductor region provided in a part of the semiconductor substrate, the power supply potential and reference potential (ground potential) are applied to the MIS FET.
Since fixed potentials such as , etc. are supplied, the single crystal silicon layer on the substrate can be effectively used for forming elements, and the degree of integration can be improved.

Above, the invention made by the present inventor has been specifically explained using examples. However, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist of the invention. Of course.

For example, in the embodiment described above, the present invention is applied to an SRAM, but the present invention may also be applied to a semiconductor integrated circuit device having a logic function that configures a predetermined circuit using two or more MISFETs.

Further, in the above embodiment, the present invention is applied to an SRAM, and a MISFET and a resistance element are explained as semiconductor elements. A capacitive element may be formed by providing a highly doped impurity region in the upper single crystal silicon layer.

[Brief explanation of the drawing]

FIG. 1 shows an SRAM for explaining one embodiment of the present invention.
FIG. FIG. 2 shows an SRAM for explaining one embodiment of the present invention.
FIG. 3 is a plan view of main parts showing a memory cell of FIG. Figure 3 is a sectional view taken along section line ■--■ in Figure 2. Figure 4 is a sectional view taken along IV-IV section line in Figure 2. Figure 5 is a sectional view taken along section line V-V in Figure 2. FIG. 6 is a cross-sectional view taken along the line Vl--Vl in FIG. 2. In the figure, WL, word line, DL, DI-, ... data line, Q+, Q2, Qs t, QS2-MI 5F
ET, ■cc, Vss...power supply terminal, RI, R2...
High resistance load element, 1... semiconductor substrate, 2, 4A to 4
F, 9A to 9F/semiconductor region, 3, 5, 6, 8, 10
゜ii...Insulating film, 3A, IIA... Connection hole, 4,
9. Single crystal silicon layer, 7A, 7B, 12A, 12B.
...It is a conductive layer. Figure 1 Figure 2 Figure 3 Figure 4/(P-), Vδ3

Claims (1)

[Claims] 1. A first single-crystal silicon layer is provided on the substrate with an insulating film interposed therebetween, and the first single-crystal silicon layer is sequentially arranged on the first single-crystal silicon layer.
A conductivity type semiconductor region, a second conductivity type or substantially intrinsic semiconductor region, and a first conductivity type semiconductor region are provided, and a second single crystal silicon layer is provided on the first single crystal silicon layer with an insulating film interposed therebetween. a first conductivity type semiconductor region, a second conductivity type or substantially intrinsic semiconductor region, and a first conductivity type semiconductor region are provided in the second single crystal silicon layer, and
A first conductivity type semiconductor region of one of the second single crystal silicon layers is arranged and provided above a second conductivity type or substantially intrinsic semiconductor region of the first single crystal silicon layer; A semiconductor region of the first conductivity type of one of the first single crystal silicon layers is provided under a second conductivity type or substantially intrinsic semiconductor region of the second single crystal silicon layer. Semiconductor integrated circuit device. 2. The first conductivity type semiconductor region constitutes a source region, drain region, or gate electrode of a MISFET, and the second conductivity type or substantially intrinsic semiconductor region constitutes a region forming a channel thereof. A semiconductor integrated circuit device according to claim 1, characterized in that: 3. The first single crystal silicon layer and the second single crystal silicon layer provided with the first conductivity type semiconductor region and the second conductivity type or substantially intrinsic semiconductor region constitute two MTSFETs. , one first conductivity type semiconductor region is connected to one M
Becomes the gate electrode of I S FET and the other MISF
3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is configured as a source region or a drain region of an ET.