JPH0210865A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacity and to accelerate an operating speed of a semiconductor integrated circuit device by integrally composing the collector region of a bipolar transistor with the source or drain region of the same conductivity type MISFET as that of the collector region. CONSTITUTION:An n-channel MISFETQn for driving a current absorbing bipolar transistor Tr2 of an inverter with a saturation preventive wiring is composed on the main face of a p-type well region 5A in a region surrounded by an isolating region. The MISFETQn is composed of a pair of n-type semiconductor regions 13 and a pair of n<+> type semiconductor regions 15 used mainly as a p-type well region 5A, a gate insulating film 11, a gate electrode 12 and source, drain regions. The saturation preventive wiring n<+> type semiconductor region 9B of the collector region of the current absorbing bipolar transistor Tr2 of the inverter with the saturation preventive wiring is composed integrally with the other n<+> type semiconductor region 15 of the n-channel MISFETQn used for driving.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and in particular to a technique that is effective when applied to a mixed semiconductor integrated circuit device having bipolar transistors and complementary MISFETs. be.

[Conventional technology]

The inventor has proposed a DRMA with a large capacity of l [Mbit].
(Dynamic Random Access Me
mory) is currently under development. This DRAM under development is a so-called mixed semiconductor integrated circuit device (Bi-CMO3) in which a bipolar transistor and a complementary MISFET (CMO8) are mixed on the main surface of the same semiconductor substrate.

Output stages that require driving capability, such as the output stage circuit of the reference clock signal generation circuit of the DRAM, are comprised of inverter circuits with saturation prevention connections.

This inverter circuit with anti-saturation wiring is composed of a complementary MISFET on the input side and two npn type bipolar transistors on the output side.

One of the current discharging bipolar transistors has its base electrode connected to the output of the complementary MISFET, and the complementary type M
Driven by ISFET. The collector electrode of the current discharging bipolar transistor is connected to the power supply voltage terminal,
The emitter electrode is connected to the output signal terminal.

The other current sinking bipolar transistor has its base electrode connected to one semiconductor region of the n-channel MISFET, and is driven by this n-channel MISFET.

A collector electrode of the current sinking bipolar transistor is connected to the output signal terminal, and an emitter electrode is connected to the reference voltage terminal. The other semiconductor region of the n-channel MISFET is connected to the collector electrode of the current sinking bipolar transistor to prevent saturation of the output signal.

The above-mentioned bipolar transistor has an inter-element isolation insulating film and a p-type semiconductor region for element isolation (isolation region).
A vertical structure is formed on the main surface of the semiconductor substrate within a region defined around the semiconductor substrate.

In other words, a bipolar transistor includes an n-type collector region, a p-type base region provided on its main surface, and an n-type emitter region provided on its main surface. n
The type collector region has a buried type collector region and a semiconductor region for raising the collector potential. The buried collector region is formed with high impurity concentration to reduce collector resistance. The collector potential raising semiconductor region is formed to raise the collector current to the surface of the semiconductor substrate, and is formed with a high impurity concentration.

n-channel MISF of the complementary MISFETs mentioned above
ET is a semiconductor substrate (
p-type well region). An n-channel MISFET mainly includes a channel formation region, a gate insulating film, a gate electrode, a source region, and a drain region.

Also, n-channel MISF of complementary MISFET
The ET is formed on the main surface of the semiconductor substrate (n-type well region) within a region surrounded by the element isolation insulating film. An n-channel MISFET is mainly composed of a channel forming region, a gate insulating film, a gate electrode, a source region, and a drain region.

Electrical connections are made between the respective semiconductor elements of the above-mentioned inverter circuit with anti-saturation connections by wiring, for example, aluminum wiring.

For this type of DRAM, for example.

Nikkei McGraw-Hill, Nikkei Microdevices, 1988
February issue, pages 79 to 84.

[Problem to be solved by the invention]

In the above-mentioned inverter circuit with anti-saturation connection, a collector resistor is inserted to prevent forward current from flowing between the base and collector of the current sinking bipolar transistor when the node potential of the output signal terminal rises. Specifically, the collector resistor is inserted between the connection portion between the collector electrode of the current sinking bipolar transistor and the other semiconductor region of the n-channel MISFET, and the output signal terminal.

The current-sinking bipolar transistor of the inverter circuit with saturation prevention wiring, which is currently being developed by the present inventor, has an n-type semiconductor for saturation prevention wiring at a position in the front corner of a semiconductor region for raising the collector potential, with a base region and an emitter region interposed therebetween. The area is arranged. That is, the collector resistor is formed in the collector region between the collector potential raising semiconductor region and the saturation prevention connection semiconductor region.

In the inverter circuit with saturation prevention wiring configured in this manner, not only the area occupied by the current sinking bipolar transistor increases by the amount corresponding to the semiconductor region for the saturation prevention wiring described above, but also the bipolar transistor and the MI 5FET are different elements. Since the occupied area for separating the data increases, there is a problem in that the degree of integration of the DRAM is reduced.

In addition, since the inverter circuit with saturation prevention wiring connects each semiconductor element with wiring, the connection area for connecting semiconductor elements and wiring and the area corresponding to mask misalignment in the manufacturing process increase. There was a problem that the degree of integration was reduced.

The object of the present invention is to provide bipolar transistors and MISF
An object of the present invention is to provide a technology that can improve the degree of integration in a mixed semiconductor integrated circuit device having an ET.

Another object of the present invention is to provide a technique that can achieve the above object by reducing the area required for separating semiconductor elements in the mixed semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that can achieve the above object by reducing the area required for connections between semiconductor elements in the mixed semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of increasing the degree of integration, reducing parasitic capacitance, and increasing operating speed in the mixed semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In a mixed semiconductor integrated circuit device (Bi-CMO3), a collector region of a bipolar transistor and a source region or a drain region of a MISFET having the same conductivity type as the collector region are integrally formed.

Further, the collector region of the bipolar transistor that is integrated with the source region or drain region of the MISFET is formed inside the buried collector region.

[For production]

According to the above-mentioned means, it is possible to eliminate the element isolation region between the bipolar transistor and the MISFET, and also to eliminate the connection area for connecting the two with wiring, so that the element isolation region and the connection area can be eliminated. The degree of integration of the mixed semiconductor integrated circuit device can be improved by an amount corresponding to .

Further, since a semiconductor region (epitaxial layer) having a lower impurity concentration than the collector region and the buried collector region of the integrated portion is not interposed between the collector region and the buried collector region,
Collector resistance can be reduced, and the operating speed of the mixed semiconductor integrated circuit device can be increased. Furthermore, since it is possible to reduce the pn junction capacitance between the collector region and the element isolation semiconductor region of the integrated portion, the parasitic capacitance added to the collector region can be reduced and the mixed semiconductor integrated circuit device It is possible to increase the operating speed.

Hereinafter, the configuration of the present invention will be described together with an embodiment in which the present invention is applied to a mixed type semiconductor integrated circuit device having a DRAM.

In addition, in all the times for explaining the example.

Components having the same function are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 3 (chip layout diagram) shows the configuration of a hybrid semiconductor integrated circuit device (Bi-CMO8) having a DRAM, which is an embodiment of the present invention.

As shown in FIG. 3, a mixed semiconductor integrated circuit device 1 having a DRAM is a mixed semiconductor integrated circuit device 1 comprising a silicon chip (silicon substrate) made of single crystal silicon and having a rectangular plane. The DRAM of device 1 is 1 [Mbi
It has a large capacity of tl.

A plurality of external terminals (ponding pads) BP are arranged at the outermost portion of the mixed semiconductor integrated circuit device 1 . Specifically, the external terminals BP are arranged at each corner of the rectangle and at the center of the long side of the rectangle. Each of the plurality of external terminals BP receives an address signal A, a select signal CE, a row address strobe signal RAS,
It is configured to apply a write enable signal WE, a data input signal Din, a data output signal Dout, a column address strobe signal CAS, a select signal GE, a reference voltage V0, a power supply voltage Vco, and the like. As the reference voltage v0, for example, the circuit ground potential 0 [V]
use. For example, a circuit operating potential of 5 [V] is used as the power supply voltage Vcc.

A plurality of memory cell arrays (memory mats) MA are arranged in the central portion of the mixed semiconductor integrated circuit device @1. This DRAM is constructed using a folded bit line method (two-intersection method). In this embodiment, a total of eight memory cell arrays MA are arranged, four on the upper side and four on the lower side of the rectangular shape shown in FIG. In other words, memory cell array MA is divided into eight parts.

In each divided memory cell array MA, a Y decoder circuit YDEC and an input/output circuit I10 are arranged in the center portion. A sense amplifier circuit SA is arranged at one end of the memory cell array MA near the Y decoder circuit YDEC. This sense amplifier circuit SA is composed of an n-channel MISFET. Memory cell array M
A sense amplifier circuit SA is arranged at the other end opposite to the one end of A. This sense amplifier circuit SA is p
It is composed of channel MISFET.

Four memory cell arrays M arranged on the upper side of a rectangular shape
An X decoder circuit XDEC and a word driver circuit WD are arranged below each of the circuits A. An X decoder circuit XDEC and a word driver circuit WD are provided above each of the four memory cell arrays MA arranged on the lower side of a rectangular shape.
is located.

In each of the divided memory cell arrays MA, a plurality of memory cells M are arranged at the intersections of complementary data lines DL and word lines WL. The memory cell M is constituted by a series circuit of an n-channel MISFET for memory cell selection and a capacitive element for information storage. This memory cell M is 1 [
bit] information is written.

The memory cell selection MISFET of the memory cell M is
The gate electrode is connected to the word line WL, one semiconductor region is connected to the complementary data line DL, and the other semiconductor region is connected to one electrode of the information storage capacitive element. The other electrode of the information storage capacitive element has a power supply voltage of 1/2 Vcc
is being applied. The power supply voltage 1/2 V, , is the intermediate potential between the power supply voltage Vcc and the reference voltage v, , approximately 2,5
[V]. The information storage capacitive element of this embodiment has a so-called planar structure. Further, the information storage capacitive element is not limited to the above-mentioned structure, and may be configured in a stacked horizontal structure in which a lower layer electrode, a dielectric film, and an upper layer electrode are sequentially laminated on a semiconductor substrate, for example.

The complementary data lines DL are configured to extend in the column direction. The complementary data line DL is connected to the aforementioned sense amplifier circuit SA and is also connected to an input/output selection M (not shown).
The input/output signal m(
I10 line). MISFE for input/output selection
T is the Y decoder circuit YD with the Y select signal line interposed
Connected to EC. The word line WL is configured to extend in the row direction. The word line WL is connected to an X decoder circuit XDEC with a word driver circuit WD interposed therebetween.

Peripheral circuits AC are arranged above the memory cell array MA arranged above the mixed semiconductor integrated circuit device 1, below the memory cell array MA arranged below, and between the upper and lower memory cell arrays MA, respectively. Peripheral circuits AC include reference clock signal generation circuits such as row address strobe related circuits (CRAS related circuits) and column address strobe related circuits (CAS related circuits), data input/output related circuits, and write enable related circuits (WE related circuits). circuit), an address system circuit, a main amplifier MA, a power supply circuit, etc.

This mixed semiconductor integrated circuit device 1 includes an X decoder circuit
Direct peripheral circuits such as DEC, Y decoder circuit YDEC, word driver circuit WD, and the first stage circuit of the peripheral circuit AC are composed of complementary MISFETs (CMO8). Further, a part of the direct peripheral circuit and the output stage circuit of the peripheral circuit AC are composed of bipolar transistors.

For example, the select signal (reference clock signal) CE that is first input to the mixed semiconductor integrated circuit device 1 is the peripheral circuit A.
It is input to the column address strobe system circuit (CAS system circuit) of C. As shown in Figure 4 (equivalent circuit diagram), the column address strobe circuit is composed of a multi-stage inverter structure in which multiple inverter circuits are connected in series for signal waveform shaping and driving force enhancement. . The column address strobe circuit uses select signal C.
When F is input to the first-stage inverter circuit 2A, the reference clock signal C2 is transmitted through each of the inverter circuits 2B to 2D.
and inverter circuits 2B, 2C, 2E.

A reference clock signal C□ is generated through each of the 2Fs.

The first stage circuit and middle stage circuit (2A, 2
B, 2C, 2E) are CMOs shown in Figure 5 (equivalent circuit diagram)
It is composed of an S inverter circuit.

On the other hand, among the inverter circuits 2A to 2F, the final stage circuits (output stage circuits 2D and 2F) are
It consists of an inverter circuit with anti-saturation connections shown in FIG. 6 (equivalent circuit diagram).

The CMOS inverter circuit, as shown in FIG.
It is composed of an n-channel MISFET Qn and a p-channel MISFETQp. MISFET
The respective gate electrodes of Qn and Qp are connected to the input signal terminal Pin, and the respective drain regions are connected to the output signal terminal P ou
connected to t. The source region of p-channel MISFETQp is connected to power supply voltage vcc. The source region of the n-channel MI 5FETQn is at the reference voltage V. It is connected to the.

As shown in FIG. 6, the inverter circuit with anti-saturation connection includes three n-channel MISFETQn, one p-channel MI5FETQp, and two npn-type bipolar
It is composed of a transistor Tr and Tr2.

One of the two current discharging bipolar transistors Tr is one of the p-channel MISFETs Qp whose collector region is used for the power supply voltage Vcc, the emitter region is used for the output signal terminal P out, and the base region is used for driving. are connected to the respective semiconductor regions. In the base region of this current discharge bipolar transistor Tr, there is an n-channel MISFET for removing the charge.
One semiconductor region of Q n is connected. Said p
The other semiconductor region of the channel MISFET QP is connected to the collector region of the current discharging bipolar transistor Tr, and is configured to prevent the current discharging bipolar transistor Tr from being saturated. The other semiconductor region of the n-channel MISFETQn is at a reference voltage V. It is connected to the. Each gate electrode of MISFETQp and Qn is connected to an input signal terminal Pin.

The other of the two current sinking bipolar transistors Tr2 has a collector region connected to the output signal terminal Pout, an emitter region connected to the reference voltage V, and a base region connected to one semiconductor region of the n-channel MISFET Qn used for driving. are connected to each other. One semiconductor region of an n-channel MISFETQn for removing the charge is connected to the base region of the current sinking bipolar transistor Tr2, as described above. n for the drive
The other semiconductor region of the channel MISFETQn is connected to the collector region of the current sinking bipolar transistor Tr2, and is configured to prevent the current sinking bipolar transistor Tr2 from being saturated. The gate electrode of this n-channel MISFETQn is connected to the input signal terminal Pin. The other semiconductor region of the n-channel MISFET Qn, which removes the charge from the base region, is connected to the base voltage v,1. This n-channel MISFETQn is connected to one semiconductor region of a p-channel MISFETQp that drives a current discharge bipolar transistor Tr.

The collector region of the current sinking bipolar transistor Tr, specifically the collector region and the driving transistor n
A collector resistor R is inserted between the connection portion of the channel MISFETQn with the other semiconductor region and the output signal terminal P out. The collector resistor R is configured to prevent forward current between the base and the collector of the current sinking bipolar transistor Tr.

The specific structure of this inverter circuit with anti-saturation wiring is as follows.
It is constructed as shown in FIG. 1 (a sectional view of the main part) and FIG. 2 (a plan view of the main part). 1 and 2 show the current sinking bipolar transistor Tr in the region surrounded by the dashed line shown in FIG. 6, and the n-channel transistor M that drives it.
I S F E T Q n is shown.

In the mixed semiconductor integrated circuit device 1, as shown in FIGS. 1 and 2, an n-type epitaxial layer 4 is laminated on the main surface of a p-type semiconductor substrate 3 made of single crystal silicon.

The current sinking bipolar transistor Tr2 of the inverter circuit with anti-saturation connection is formed on the main surface of the semiconductor substrate 3 in a region surrounded by a separation region. The isolation region is composed of a 3°p type buried semiconductor region 5 on the semiconductor substrate, a p type semiconductor region 7 for element isolation, and an element isolation insulating film 8.

The p-type buried semiconductor region 5 is provided between the semiconductor substrate 1 and the epitaxial layer 4.

The p° type buried semiconductor region 5 is formed in the same layer as the n° type buried semiconductor region (buried collector region) 6, and is formed in self-alignment with respect to the n° type buried semiconductor region (buried collector region) 6. The p-type semiconductor region 7 for element isolation is provided on the main surface of the epitaxial layer 4. The element isolation insulating film 8 is provided on the main surface of the epitaxial layer 4 .

The current sinking bipolar transistor Tr2 is mainly composed of an n-type collector region, a p-type base region, and an n-type emitter region.

The n-type collector region is an n-type buried semiconductor region 6.
．． Epitaxial layer 4, n° type semiconductor region (first collector region) 9A for raising collector potential, and n for saturation prevention connection.
An a n'-type buried semiconductor region 6 composed of a °-type semiconductor region (second collector region) 9B is provided between the semiconductor substrate 3 and the epitaxial layer 4. This n-type buried semiconductor region 6 is provided over substantially the entire area of the current sinking bipolar transistor Tr, and is configured to reduce collector resistance. The collector potential raising Go-shaped semiconductor region 9A is configured such that its bottom surface is in contact with the Go-shaped buried semiconductor region 6, and is configured to raise the collector potential to the main surface of the epitaxial layer 4. An n° type semiconductor region 15, which is used as a source region or a drain region of an n channel MISFETQn, is provided on the main surface of this collector potential raising n' type semiconductor region 9A. The n-type semiconductor region 9B for saturation prevention connection is provided at a position facing the collector potential raising semiconductor region 9A with the p-type base region as the center. This n° type semiconductor region 9B for saturation prevention connection is formed in the same manufacturing process as the n″ type semiconductor region 9A for raising the collector potential, and similarly, the bottom surface is formed in the n° type buried semiconductor region 6. A collector resistor R is formed by the epitaxial layer 4 between the n-type semiconductor region 9A for raising the collector potential and the n-type semiconductor region 9B for saturation prevention connection. .

n for raising the collector potential of the n-type collector region.

type semiconductor region 9A, n-type semiconductor region 9 for saturation prevention connection
Each of B is formed in the region where the n° type buried semiconductor region 6 is formed. In other words, each of the n-type semiconductor region 9A for raising the collector potential and the n-type semiconductor region 9B for saturation prevention connection is securely in contact with the Go-shaped buried semiconductor region 6 on the bottom surface, and It is configured to be separated from the p° type buried semiconductor region 5 of the region.

The p-type base region is composed of a p-type semiconductor region 1o provided on the main surface of the epitaxial layer 4.

The n-type emitter region is a go-type semiconductor region 1 provided on the main surface of the p-type semiconductor region 10, which is the p-type base region.
It consists of 5.

An n-channel MISFET that drives the current sinking bipolar transistor Tr2 of the inverter circuit with anti-saturation connection.
Qn is formed on the main surface of the P-type well region 5A within a region surrounded by one isolation region. p-type well region 5A
is provided on the p° type buried semiconductor region 5. The n-channel MISFET Qn mainly includes a p-type well region (channel forming region) 5A, a gate insulating film 11, a gate electrode 12, a pair of n-type semiconductor regions 13 used as source and drain regions, and a pair of n It is made up of a type semiconductor region 15.

The n-type semiconductor region 13 with a low impurity concentration is provided on the channel formation region side of the Go-type semiconductor region 15 with a high impurity concentration, and the n-channel MISFETQn is connected to the LD D (L i
Ghtly is constructed in a structure (once opened drain). The n-type semiconductor region 13 is formed in self-alignment with the gate electrode 12. The green semiconductor region 15 is a sidewall spacer 1 formed on the sidewall of the gate electrode 12.
It is formed in self-alignment with respect to 4.

For example, two layers of aluminum alloy interconnections extend in the upper layer of each of the current sinking bipolar transistors Tr2 and n-channel MISFETQn, although they are shown in a simplified manner. This aluminum alloy wiring is configured to electrically connect semiconductor elements.

The n-type semiconductor region 9B for saturation prevention connection in the collector region of the current sinking bipolar transistor Tr2 of this inverter circuit with saturation prevention connection is an n-type semiconductor region 9B used for driving.
Channel MI 5FETQn other Go-type semiconductor region 1
It is configured integrally (shared) with 5. This n° type semiconductor region 9 for connection to prevent saturation: IB and the n° type semiconductor region 1
5 and the same potential, the above-mentioned integrated structure is possible.

As shown in FIG. 2, the n° type semiconductor region 9B for saturation prevention wiring is arranged in the row direction (same direction as the gate width direction).
A portion of the periphery is formed by an inter-element isolation insulating film 8 formed in a size approximately equal to at least the amount of mask misalignment in the manufacturing process compared to the n-type buried semiconductor region (buried collector region) 6. is formed within a defined area.

That is, the n-type semiconductor region 9B for saturation prevention connection is formed by the ion implantation method using the inter-element isolation insulating film 8 as a mask for introducing impurities. Further, the n-type semiconductor region 9B for saturation prevention connection is separated from the gate electrode 12 by a predetermined dimension in the column direction (same direction as the gate length direction) to prevent impurities from entering the channel formation region of the n-channel MISFETQn. has been done.

In this way, in the inverter circuit with saturation prevention wiring of the mixed semiconductor integrated circuit device 1, the n° type semiconductor region 9 for saturation prevention wiring of the current sinking bipolar transistor Tr2
N-channel MI of the same conductivity type as B (collector region)
By integrally configuring one n° type semiconductor region 15 which is the source region or drain region of S F E T Q
Isolation region between r2 and n-channel MISFETQn (
Interelement isolation insulating film 8 and element isolation p° type semiconductor region 7
) can be eliminated, so the degree of integration of the mixed semiconductor integrated circuit device 1 can be improved by an amount corresponding to this isolation region. In the DRAM mounted on the mixed semiconductor integrated circuit device [1] of this embodiment, the inverter circuit with anti-saturation connection is used in about 20 to 40% of the total number of inverter circuits, so the present invention is particularly useful. It is valid.

In the inverter circuit with anti-saturation connection, the go-type semiconductor region 9B for anti-saturation connection of the current sinking bipolar transistor Tr and the go-type semiconductor region 15 of the n-channel MISFETQn are integrally configured to connect them. Since the wiring can be eliminated, the connection area with the wiring and the margin area for mask alignment when connecting with the wiring can be eliminated, and the degree of integration of the mixed semiconductor integrated circuit device 1 can be improved.

Further, a go-type semiconductor region 9B for saturation prevention connection of the current sinking bipolar transistor Tr2, which is integrated with the n°-type semiconductor region 15 of the n-channel MISFETQn, is formed inside the n-type buried semiconductor region 6. By doing so, the epitaxial layer 4 having a lower impurity concentration compared to these is not interposed between the n° type semiconductor region 9B for saturation prevention connection and the n type buried semiconductor region (buried collector region). , the collector resistance can be reduced, and the operating speed of the mixed semiconductor integrated circuit device 1 can be increased.

Further, the saturation prevention connection n-type semiconductor region 9B is n°
By forming it inside the buried semiconductor region 6 of the mold,
Since the pn junction capacitance between the saturation prevention connection n° type semiconductor region 9B and the p° type buried semiconductor region 5 can be reduced, the parasitic capacitance added to the collector region can be reduced, and the mixed semiconductor The operating speed of the integrated circuit device 1 can be increased.

The aforementioned current sinking bipolar transistor Tr.

As shown in FIG. 7 (plan view of main part), the Go-type semiconductor region 9B for saturation prevention connection is formed by using a photoresist mask without using the inter-element isolation insulation 1I18, and forming an n-type buried semiconductor region 9B. It may also be formed inside the type semiconductor region 6.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but it goes without saying that the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. be.

For example, one aspect of the present invention is S (S tatic) RAM
, ROM (Read Only Memory)
The present invention can be widely applied to mixed semiconductor integrated circuit devices having memory circuits and logic circuits such as the above.

〔Effect of the invention〕

A brief explanation of the effects of typical inventions disclosed in this application is as follows.

The degree of integration of a mixed semiconductor integrated circuit device can be improved.

Further, in the mixed semiconductor integrated circuit device, it is possible to improve the degree of integration and increase the operating speed.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of an inverter circuit with saturation prevention wiring of a mixed semiconductor integrated circuit device having a DRAM, which is an embodiment of the present invention. FIG. 2 is a main part of the inverter circuit with saturation prevention wiring. FIG. 3 is a chip layout diagram of the mixed semiconductor integrated circuit device, and FIGS. 4 to 6 are equivalent circuit diagrams of peripheral circuits of the DRAM. FIG. 7 is a plan view of main parts of another example of the inverter circuit with the saturation prevention wiring. In the figure, Tr,...Bipolar transistor, Qn, Qp-MISFET, R-...Collector resistance,
1...Mixed semiconductor integrated circuit device, 2A to 2F...
Inverter circuit, 5.8... Embedded semiconductor region, 7.
... Semiconductor region for element isolation, 8... Inter-element isolation insulating film, 9A... Semiconductor region for raising potential, 9B... Semiconductor region for saturation prevention connection, 13.15... Semiconductor region .

Claims (1)

[Scope of Claims] 1. In a mixed semiconductor integrated circuit device having a bipolar transistor and a MISFET, a collector region of the bipolar transistor and a source region and a drain region of the MISFET having the same conductivity type as the collector region. A semiconductor integrated circuit device characterized in that one semiconductor region and one semiconductor region are integrally configured. 2. The bipolar transistor and MISFET are:
The semiconductor integrated circuit device according to claim 1, comprising an inverter circuit with anti-saturation connection. 3. In the bipolar transistor of the inverter circuit with anti-saturation connection, a base region and an emitter region are arranged between a semiconductor region for raising the collector potential and a semiconductor region for anti-saturation connection arranged at a distance therefrom. A semiconductor integrated circuit device according to claim 2, characterized in that: 4. MISFET of the inverter circuit with anti-saturation connection
Claim 3 is characterized in that one semiconductor region is configured integrally with a semiconductor region for saturation prevention connection of the bipolar transistor, and the other semiconductor region is connected to the base region of the bipolar transistor. 2. The semiconductor integrated circuit device described in 2. 5. The collector potential raising semiconductor region and the saturation prevention wiring semiconductor region of the bipolar transistor are electrically connected by a buried collector region, and the collector potential raising semiconductor region and the saturation prevention wiring semiconductor region are 5. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device is formed inside the buried collector region.