JP3047605B2 - Dynamic RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic random access memory (DRAM) in which memory cells are formed in island regions formed on a substrate surface, so-called wells.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, a back gate voltage (well bias voltage) is applied to a well in which a MOS transistor is formed. The back gate voltage is used to positively reverse the pn junction between the source of the MOS transistor formed in the well and the well.

As described above, when the back gate voltage is applied to the well, even if the source voltage of the MOS transistor formed in the well fluctuates slightly due to the noise signal,
The bias state between the source of the MOS transistor formed in the well and the well becomes forward, so that minority carriers can be prevented from being injected into the well from the source of the MOS transistor.

In particular, in a DRAM, for example, when minority carriers are injected into a well from a MOS transistor in a peripheral circuit portion, this is absorbed by a storage electrode of a memory cell formed in the well, and stored data is destroyed. Therefore, injection of minority carriers into a well in which a memory cell is formed must be absolutely avoided.

[0005] Therefore, it is necessary to apply a back gate voltage to a well in consideration of the noise signal level.
In the RAM, since the power supply voltage is reduced,
The noise signal level on the chip has also been reduced, and the bias voltage has tended to be smaller than in the past.

Here, from the viewpoint of power consumption and refresh characteristics, the back gate voltage for a well in which a memory cell is formed has a small value, preferably zero
Bias voltage, i.e. ground voltage for p-well, n
If it is a well, it is desirable to bias to the internal power supply voltage.

That is, in the access state, since a large current flows through the sense amplifier, the power consumption of the back gate voltage generation circuit mounted on the chip is inconspicuous. However, in the standby state, the current consumption of the entire chip is on the order of microamps. Since the power consumption becomes smaller, the power consumption of the back gate voltage generation circuit becomes conspicuous. Therefore, in terms of power consumption, it is desirable that the back gate voltage be a small value, preferably a zero bias voltage.

The refresh cycle in a DRAM is inversely proportional to the back gate voltage. The smaller the back gate voltage, the longer the data retention time of the storage capacitor and the longer the refresh cycle. Therefore, also from the viewpoint of refresh characteristics, it is desirable that the back gate voltage be a small value, preferably a zero bias voltage.

In this case, the threshold voltage of the MOS transistor forming the transfer gate of the memory cell needs to be adjusted according to the back gate voltage. For example, when an nMOS transistor is formed in a p-type well,
In the case of no adjustment, the back gate voltage is -1.5.
[V] is preferable, and even if it is deeper,
Even if it is shallow, the refresh characteristics deteriorate.

Here, assuming that the back gate voltage is set to zero bias voltage from the beginning, if the MOS transistor forming the transfer gate of the memory cell is formed so as to have an appropriate threshold voltage, the back gate voltage can be reduced. Can be a zero bias voltage.

[0011]

However, the back gate voltage at the portion where the memory cell is formed is simply reduced to zero.
If the bias voltage is set, only the diffusion potential is applied to the pn junction between the storage electrode and the well.
Even when the MOS transistor of the peripheral circuit slightly changes the voltage of the well due to signal noise or the like, the pn junction between the storage electrode and the well is in a forward bias state, and the refresh characteristic of the memory cell is improved. There was a problem of worsening.

Further, the cell plate is capacitively coupled to the storage electrode, and the voltage change of the cell plate becomes almost the same as the voltage change of the storage electrode. Therefore, when the back gate voltage of the portion where the memory cell is formed is simply set to the zero bias voltage and the voltage of the cell plate changes, the pn between the storage electrode and the well is reduced.
There is a problem that the junction is in a forward bias state, minority carriers are injected into the well from the storage electrode, and the stored data may be destroyed.

In view of the above, according to the present invention, the back gate voltage of a well in which a memory cell is formed is set as a zero bias voltage to reduce power consumption and improve refresh characteristics. Fluctuation of the well voltage due to the peripheral circuit due to signal noise and the like, and accumulation due to the forward bias state of the pn junction between the storage electrode and the well in which the memory cell is formed due to the voltage fluctuation of the cell plate. DR that can avoid data destruction
It aims to provide AM.

[0014]

SUMMARY OF THE INVENTION A DRAM according to the present invention
Is to form a memory cell in a well dedicated to a memory cell which is electrically separated from a well of a peripheral circuit and connected via a resistor to a voltage source capable of supplying a zero bias voltage.

[0015]

In the present invention, the well in which the memory cell is formed is a well dedicated to the memory cell, and is electrically separated from the well of the peripheral circuit. Even if the voltage of the well changes, the well dedicated to the memory cell is not affected by this, and the pn junction between the storage electrode and the well dedicated to the memory cell does not enter a forward bias state.

Therefore, it is possible to avoid destruction of stored data due to a forward bias state of a pn junction between a storage electrode and a well due to a change in a well voltage due to a peripheral circuit due to signal noise or the like.

In the present invention, the well in which the memory cell is formed is connected via a resistor to a voltage source capable of supplying a zero bias voltage. The formed well enters a floating state.

As a result, when the cell plate voltage fluctuates, the voltage fluctuation is transmitted to the well via the parasitic capacitance between the cell plate and the well in which the memory cell is formed, and the well in which the memory cell is formed. Also, the voltage fluctuates similarly to the cell plate voltage, and the storage electrode and the well in which the memory cell is formed do not become a forward bias.

Therefore, the voltage variation between the storage electrode and the well dedicated to the memory cell is caused by the voltage fluctuation of the cell plate.
Destruction of stored data due to the forward bias state of the n-junction can be avoided.

When a well dedicated to a memory cell is formed in an opposite conductivity type well connected to a cell plate voltage source for supplying a predetermined voltage to a cell plate of a storage capacitor of the memory cell, It is possible not to be affected by the voltage fluctuation.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment and a second embodiment of the present invention will be described below with reference to FIGS.

First Embodiment FIG. 1 FIG. 1 is a sectional view showing a main part of a first embodiment of the present invention.
In the figure, 1 is an n-type silicon substrate, 2 is a peripheral circuit section, and 3 is a memory cell array section.

In the peripheral circuit section 2, reference numeral 4 denotes a pad for a power supply voltage Vcc supplied from the outside, for example, a pad for Vcc to which 3 [V] is input, 5 denotes a pad for grounding, and 6 denotes a substrate 1
N ⁺ diffusion layer for making contact with the substrate 1
Is biased to 3 [V] via the n ⁺ diffusion layer 6.

Reference numeral 7 denotes a step-down circuit for stepping down a power supply voltage Vcc of 3 [V] supplied from the outside to an internal power supply voltage Vint of 2 [V]. This step-down circuit 7 comprises a pMOS transistor 8. I have. Incidentally, in this pMOS transistor 8, p ⁺ diffusion layer constituting the source 9, 10 p ⁺ diffusion layer forming a drain, 11 is a gate made of polysilicon.

Reference numeral 12 denotes an internal power supply voltage using circuit which uses the internal power supply voltage Vint output from the step-down circuit 7 as a power supply voltage. In the internal power supply voltage using circuit 12, 13 is a p-type well, and 14 is p-type well. A p ⁺ diffusion layer for making contact with the p-type well;
Are biased to 0 [V] via the p ⁺ diffusion layer 14.

Reference numeral 15 denotes a pMOS transistor;
N is an nMOS transistor, the pMOS transistor 15, p ⁺ diffusion layer constituting the source 17, 18 is p ⁺ diffusion layer forming a drain, 19 denotes a gate made of polysilicon, the nMOS transistors 16, 20 forming a drain ^{A +} diffusion layer, 21 is an n ⁺ diffusion layer serving as a source, and 22 is a gate made of polysilicon.

In the memory cell array section 3, 2
3 is a p-type well, 24 is a p ⁺ diffusion layer for making contact with the p-type well 23, 25 is a resistor, 26 is an nMOS
A p-type well 23, which is a transistor, is grounded via a parallel circuit of a resistor 25 and an nMOS transistor 26.

STX is a starter signal for preventing the input / output circuit from operating until the power supply rises to a predetermined voltage when the power supply is turned on. It is kept at the H level until the power supply voltage rises to the predetermined voltage, and is kept at the L level after the power supply voltage rises to the predetermined voltage.

Therefore, in the first embodiment,
When the power is turned on, the nMOS transistor 26 is turned on and the p-type well 23 is grounded via the nMOS transistor 26 until the power supply voltage rises to a predetermined voltage. [V].

Reference numeral 27 denotes a storage capacitor, reference numeral 28 denotes a cell plate, reference numeral 29 denotes a cell plate voltage generating circuit for generating 1 [V] as a cell plate voltage Vpr, reference numeral 30 denotes an internal power supply voltage line, and reference numerals 31 and 32 denote resistors. is there.

Further, 33 is an nMOS transistor constituting the transfer gate 34 is n ⁺ diffusion layer forming the drain (or source), 35 forms a source (or drain) n ⁺
The diffusion layer 36 is a word line made of polysilicon.
The n ⁺ diffusion layer 34 also functions as a storage electrode of the storage capacitor 27. Reference numeral 37 denotes a bit line.

In the first embodiment, the peripheral circuit 2
Is electrically separated from the p-type well 13 of the memory cell array section 3 so that electrons are
Even if the voltage is injected into the p-type well 13 from the source of the transistor 16 and the voltage of the p-type well 13 fluctuates, the p-type well 23 is not affected by this, and the pn between the storage electrode 34 and the p-type well 23 is not affected. Destruction of stored data due to a forward biased state of the junction can be avoided.

In the first embodiment, when the internal power supply voltage Vint changes, the cell plate potential Vpr also changes.
7, the voltage of the storage electrode 29 changes.

If the p-type well 23 is completely grounded without passing through the resistor 25, the internal power supply voltage Vint
When the voltage of the storage electrode 34 drops due to the drop, the pn junction between the storage electrode 34 and the p-type well 23 is in a forward bias state.

In this case, if the storage capacitor 27 stores data "0", electrons are injected from the storage electrode 34 into the p-type well 23, and the stored data becomes "1".
May change to

However, in the first embodiment, p
Since the type well 23 is grounded via the resistor 25, the p-type well 23 substantially responds to a voltage change.
Becomes floating.

As a result, when the cell plate voltage Vpr drops due to the drop of the internal power supply voltage Vint, the parasitic capacitance C _PW between the cell plate 28 and the p-type well 23 causes
The potential of the p-type well 23 also drops in conjunction with the cell plate potential Vpr, and the pn between the storage electrode 34 and the p-type well 23 is reduced.
The junction does not become forward biased, but maintains a reverse bias.

Therefore, according to the first embodiment, destruction of stored data due to the forward bias state of the pn junction between the storage electrode 34 and the p-type well 23 due to the voltage fluctuation of the cell plate 28. Can be avoided.

When the internal power supply voltage Vint drops sharply and continues for a long time, if the time constant created by the resistor 25 is short, the potential of the p-type well 23 becomes
The transient drop state is restored to 0 [V], and in this process, the bias state between the storage electrode 34 and the p-type well 23 becomes a forward bias, and electrons are injected from the storage electrode 34 into the p-type well 23. Resulting in.

On the other hand, if the time constant created by the resistor 25 is longer than the refresh cycle, rewriting to the storage capacitor 27 is performed before the potential of the p-type well 23 recovers from the transient drop state to 0 [V]. As a result, the pn junction between the storage electrode 34 and the p-type well 23 does not enter a forward bias state. Therefore, it is preferable that the resistance 25 is set to a resistance value such that the time constant with the parasitic capacitance around the p-type well 23 is longer than the refresh cycle.

When the p-type well 23 is grounded via the resistor 25, the current flowing through the p-type well 23 and the resistance 25
However, since the nMOS transistor 33 only transfers the accumulated charge, a large current does not flow, a small amount of current flows through the p-type well, and the resistance 2
There is no problem even if the p-type well 23 is grounded via 5.

As described above, according to the first embodiment,
The back gate voltage of the p-type well 23 is set to zero [V], which is a zero bias voltage, to reduce power consumption and improve refresh characteristics. Fluctuation of well voltage due to the part 2,
Due to the voltage fluctuation of the cell plate 28, the storage electrode 34
The destruction of the stored data due to the forward bias state of the pn junction between the p-type well and the p-type well 23 can be avoided.

The cell plate 28 and the p-type well 23
May be intentionally inserted between the power supply voltage Vcc and the potential of the p-type well 23 to easily follow the potential Vpr of the cell plate 28. , Since the substrate 1 is n-type and has the power supply voltage Vcc, the voltage of the p-type well 23 is modulated via the junction capacitance C _WS between the substrate 1 and the p-type well 23. Therefore, there is no need to intentionally enter a capacity.

However, since the voltage change of the cell plate 28 is generally half that of the change of the internal power supply voltage Vint, when the well potential is modulated through the junction capacitance C _WS , the change of the junction potential becomes excessive. May cause changes.

That is, when the power supply voltage Vcc supplied from the outside rises sharply, the potential of the p-type well 23 rises, and the potential of the storage electrode 34 increases with the rise of the potential of the cell plate 28. If this happens, the bias state between the storage electrode 34 and the p-type well 23 will be in the forward direction.

Particularly, in such a situation, as in the first embodiment, a step-down circuit 7 is provided to step down the power supply voltage Vcc supplied from the outside in the chip, and use this step-down voltage as the internal power supply voltage. It is remarkable if you do. This is because the step-down voltage Vint can be made very stable by circuit design, but the external voltage may fluctuate greatly.

As described above, in the first embodiment,
When the power supply voltage Vcc supplied from the outside increases rapidly, it will raise the voltage of the p-type well 23 via the junction capacitance C _WS between the substrate 1 and the p-type well 23, the storage electrode 34 and the p-type well 23 There is a disadvantage that the gap may be forward biased. A second embodiment described below solves this inconvenience.

Second Embodiment FIG. 2 FIG. 2 is a sectional view showing a main part of a second embodiment of the present invention.
In the figure, 38 is a p-type silicon substrate, 39 is a peripheral circuit portion, 4
0 is a memory cell array unit.

In the peripheral circuit section 39, reference numeral 41 denotes a pad for a power supply voltage Vcc supplied from the outside, for example, a pad for Vcc to which 3 [V] is input; 42, a pad for grounding;
Is ap ⁺ diffusion layer for making contact with the substrate 38, and the substrate 38 is connected to 0 [V] through the p ⁺ diffusion layer 43.
Biased.

Reference numeral 44 denotes 3 [V] supplied from the outside.
Is reduced to the internal power supply voltage Vint of 2 [V].
Is an n-type well, 46 is an n ⁺ diffusion layer for making contact with the n-type well 45, and the n-type well 45 is biased to 3 [V] via the n ⁺ diffusion layer 46.

Reference numeral 47 denotes a pMOS transistor for performing a step-down operation, and reference numeral 48 denotes a p ⁺ diffusion layer serving as a source.
Reference numeral 9 denotes ap ⁺ diffusion layer serving as a drain, and reference numeral 50 denotes a gate made of polysilicon.

An internal power supply voltage use circuit 51 uses the internal power supply voltage Vint output from the step-down circuit 44 as a power supply voltage. In the internal power supply voltage use circuit 51, 52 is an n-type well and 53 is an n-type well. This is an n ⁺ diffusion layer for making contact with the mold well 52, and the n well 52 is biased at 2 [V] via the n ⁺ diffusion layer 53.

54 is a pMOS transistor, 55
Is an nMOS transistor, in the pMOS transistor 54, 56 is a p ⁺ diffusion layer forming a source, 57 is a p ⁺ diffusion layer forming a drain, 58 is a gate made of polysilicon, and in an nMOS transistor 55, 59 is an n ^{A +} diffusion layer, 60 is an n ⁺ diffusion layer serving as a source, and 61 is a gate made of polysilicon.

In the memory cell array section 40,
62 is a p-type well, 63 is ap ⁺ diffusion layer for making contact with the p-type well 62, 64 is a resistor, 65 is an nMO
This is an S transistor, and the p-type well 62 is grounded via a parallel circuit of a resistor 64 and an nMOS transistor 65.

As described in the first embodiment, STX is a starter signal for preventing the input / output circuit from operating when the power is turned on until the power supply rises to a predetermined voltage. In operation, when the power supply is turned on, the level is set to H level until the power supply voltage rises to a predetermined voltage, and is set to L level after the power supply voltage rises to the predetermined voltage.

Therefore, also in the second embodiment,
When the power is turned on, the nMOS transistor 26 is turned on and the p-type well 23 is grounded via the nMOS transistor 26 until the power supply voltage rises to a predetermined voltage. [V].

Reference numeral 66 denotes a storage capacitor, 67 denotes a cell plate, 68 denotes a cell plate voltage generation circuit for generating 1 [V] as a cell plate voltage Vpr, 69 denotes an internal power supply voltage line, and 70 and 71 denote resistors. is there.

[0058] Further, 72 is an nMOS transistor constituting the transfer gate, n ⁺ diffusion layers forming the drain (or source) 73, 74 form a source (or drain) n ⁺
The diffusion layer 75 is a word line made of polysilicon.
Note that the n ⁺ diffusion layer 73 also functions as a storage electrode of the storage capacitor 66. Reference numeral 76 denotes a bit line.

Reference numeral 77 denotes an n-type well, and 78 denotes an n ⁺ diffusion layer for making contact with the n-type well 77.
In this example, the n ⁺ diffusion layer 78 is connected to the cell plate 67, and the n-type well 77 is biased to the cell plate voltage Vpr.

Also in the second embodiment, the p-type well 6
2 is dedicated to a memory cell and is not shared with a peripheral circuit. Therefore, it is possible to avoid the destruction of the stored data due to the forward bias state of the pn junction between the storage electrode 73 and the p-type well 62 due to the influence of the peripheral circuit.

In the second embodiment, when the internal power supply voltage Vint changes, the cell plate potential Vpr also changes.
6, the voltage of the storage electrode 73 changes.

Here, in the second embodiment, since the p-type well 62 is grounded via the resistor 64,
In response to a voltage change, the p-type well 62 becomes substantially floating.

As a result, when the cell plate voltage Vpr drops due to the drop of the internal power supply voltage Vint, the parasitic capacitance C _PW between the cell plate 67 and the p-type well 62 causes
The potential of the p-type well 62 also drops in conjunction with the cell plate potential Vpr, and the pn between the storage electrode 73 and the p-type well 62 is reduced.
The junction does not become forward biased, but maintains a reverse bias.

Therefore, according to the second embodiment, the destruction of the stored data due to the forward bias state of the pn junction between the storage electrode 73 and the p-type well 62 due to the voltage fluctuation of the cell plate 67. Can be avoided. The resistance of the resistor 64 is preferably such that the time constant with the parasitic capacitance around the p-type well 62 is larger than the refresh cycle, as in the case of the first embodiment.

In the second embodiment, the p-type well 62 is formed in the n-type well 77 to which the cell plate voltage Vpr is supplied as a bias voltage.
The cell plate 67 is not affected by the voltage fluctuation of the substrate 38.
Is affected only by this voltage.

That is, for example, even if the voltage of the substrate 38 rises sharply, the p-type well 62 does not rise suddenly, and the bias state between the storage electrode 73 and the p-type well 62 does not become forward. Therefore, the destruction of the stored data due to the voltage fluctuation of the substrate 38 can be avoided.

As described above, according to the second embodiment,
The back gate voltage of the p-type well 62 is set to 0 [V], which is a zero bias, so as to reduce power consumption and improve refresh characteristics. In addition, it is possible to avoid the destruction of stored data due to the forward bias state of the pn junction between the storage electrode 73 and the p-type well 62 due to the well voltage fluctuation caused by the cell 39 and the voltage fluctuation of the cell plate 67. Destruction of stored data due to voltage fluctuation of the voltage 38 can be avoided.

In the above embodiment, the case where the transistor forming the transfer gate of the memory cell is constituted by an nMOS transistor has been described. However, in the present invention, the transistor forming the transfer gate of the memory cell is constituted by a pMOS transistor. The case can also be applied.

In this case, the well forming the memory cell is an n-type well, and the n-type well is connected to the internal power supply voltage line via a resistor. When a well for forming a memory cell is formed in a well to which a cell plate voltage is supplied, the well is made p-type.

[0070]

According to the present invention, the back gate voltage of the well in which the memory cell is formed is set to zero bias voltage to reduce power consumption and improve refresh characteristics. The well in which the memory cell is formed is a well dedicated to the memory cell, and is connected via a resistor to a voltage source capable of supplying a zero bias voltage. The voltage between the storage electrode and the well in which the memory cell is formed due to a change in the well voltage or a change in the voltage of the cell plate.
Destruction of stored data due to the forward bias state of the n-junction can be avoided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a main part of a first embodiment of the present invention.

FIG. 2 is a sectional view showing a main part of a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 27 storage capacitor 28 cell plate 33 nMOS transistor forming transfer gate 66 storage capacitor 67 cell plate 72 nMOS transistor forming transfer gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 G11C 11/407 H01L 21/8242

Claims (4)

(57) [Claims] 1. A well of a peripheral circuit is electrically separated from a well of a peripheral circuit.
And a memory cell formed in a well dedicated to the memory cell connected to a voltage source capable of supplying a zero bias voltage via a resistance element.
M. 2. The memory cell-dedicated well is formed in an opposite conductivity type well connected to a cell plate voltage source for supplying a predetermined voltage to a cell plate of a storage capacitor of the memory cell. The dynamic RAM according to claim 1, wherein 3. The resistance element according to claim 1, wherein a time constant with respect to a parasitic capacitance connected to the resistance element is set to a resistance value that is longer than a refresh cycle.
Or the dynamic RAM according to 2. 4. A switch element controlled to be in a conductive state for a predetermined time after power-on and to be in a non-conductive state after the predetermined time has passed, is connected in parallel to the resistor. The dynamic RAM according to claim 1, 2 or 3, wherein