JPH08139851A - Image sensor - Google Patents

Abstract

PURPOSE: To realize an amplification type MOS image sensor capable of reading original information at a high speed with high S/N. CONSTITUTION: The sensor is provided with a photo diode 1, inverting amplifier stages 7, 8, a bright state output amplifier FET 14, a bright state output transfer switch 9, a reset switch 6 resetting the photo diode 1, a dark state output amplifier FET 16, a dark state output transfer switch 10, a bright state output read FET 15 and a dark state output read FET 17 reading in parallel outputs of the bright state amplifier FET 14 and the dark state output amplifier FET 16, a simultaneous pulse generating circuit 19, an output switch drive flip-flop circuit 31 and a chip changeover output switch pair 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type MOS image sensor capable of reading original information with high sensitivity, high S / N and high speed.

[0002]

2. Description of the Related Art There are CCD type and MOS type image sensors capable of high-speed reading, and the MOS type is CC type.
While it is more cost effective than the D type, it is disadvantageous in terms of sensitivity and S / N. Therefore, in recent years, an amplification type MOS has been improved in sensitivity by adding an amplification function inside.
A report on an image sensor has been made (Japanese Patent Laid-Open No. Hei 3)
-110962).

The structure of the conventional example will be described with reference to FIG. 5 showing the circuit structure of one pixel. The photodiode 1 is connected to the gate electrode of the first amplification FET 2 and is also connected to the reset power supply via the reset switch 6, the drain electrode of the first amplification FET 2 is connected to the power supply, and the source electrode thereof is the second amplification FET 4 Of the load FET3 and the drain electrode of the load FET3.
The capacitance 20 is a capacitance associated with the cathode terminal of the photodiode 1, and includes the cathode diffusion junction capacitance of the photodiode 1, the gate oxide film capacitance of the first amplification FET 2, the source or drain diffusion capacitance of the reset switch 6, and the like.
The drain electrode of the second amplification FET 4 is connected to the power supply, and the source electrode thereof is connected to the drain electrode of the readout FET 5. The source electrode of the read FET 5 is connected to the signal output line 12. The current value of load FET3 is FET21 and FET2
It is a mirror of the current value determined by 2.

Next, FIG. 5 and FIG. 6 which is a timing diagram.
The operation of the above conventional example will be described with reference to FIG. In FIG.
CK1 and CK2 are shift register driving clock pulse pairs (not shown), AP is a pulse applied to the read gate terminal 23 in FIG. 5, and RP is a pulse applied to the reset gate terminal 24 in FIG. V (12) is shown in FIG.
7 shows how the output voltage of the signal output line 12 changes.

Immediately after the reset switch 6 is turned on,
The cathode potential of the photodiode 1 decreases according to the amount of incident light. After the lapse of the optical information storage period, a read pulse AP is applied to the gate terminal 23 by a shift register (not shown), the common read gate terminal 23 of the read FETs 5 and 21 is turned on, and the potential of the photodiode 1 is lowered according to the amount of light. The cathode potential, that is, the bright output is output to the source electrode of the first amplification FET2 as a follower, and the follower output voltage is output to the second amplification FET4.
And is amplified and output to the signal output line 12 via the read FET 5.

Next, after the output period required for reading the bright output is elapsed, the reset pulse RP is applied to the reset gate terminal 24 while the read FET 5 remains turned on. The reset switch 6 is turned on, and the cathode potential of the photodiode 1 is reset to the power supply potential. Subsequently, the reset switch 6 is opened, and the optical information storage period starts again from this moment. However, it is obvious that the photodiode 1 has practically no optical information storage immediately after the reset, which is dark. It can be regarded as a state of time. Therefore, at this time, the cathode potential of the photodiode 1 becomes the first
Amplifier FET2, second amplifier FET4 and read FET5
The output that is amplified by the follower and appears on the signal output line 12 can be treated as a dark output.

Next, after the output period required for reading the dark output is elapsed, the read FE of the selected pixel is performed.
T5 returns to the off state. Subsequently, the reading of the bright output of the pixel in the next stage, the reset, and the reading of the dark output are successively performed.

As described above, continuous reading of the dark output and the bright output for one pixel in time series is the same as when the CCD sensor is read by the correlated double sampling method. If the voltage difference between V (bright) and V (dark) in V (12) in FIG. 6 is detected in the subsequent stage, fixed pattern noise due to variations in the element parameters of the first amplification FET 2 and the second amplification FET 4 is removed. To obtain a high S / N output signal.

For later discussion, the time response of the output signal will be described with reference to the timing diagram of FIG. As is apparent from the timing diagram, one clock period is used in a time-sharing manner for the bright output read period, the reset pulse RP application period, and the dark output read period. Furthermore, in order to avoid noise in the output signal due to the rising and falling of the clock pulses CK1 and CK2, the period during which the state of CK1 and CK2 is stable at “H” or “L” level It is necessary to secure enough for the data sampling period.

[0010]

In the above-mentioned prior art, high-speed output signal reading becomes difficult due to the following reasons, especially in the case of driving a low voltage power supply of about 5V. When the output signal is read at high speed, one clock period is shortened, and the reset pulse application period must be shortened in order to secure the read period for the bright output and the dark output. In order for the response output to the reset state of the photodiode 1 to appear promptly on the source terminal of the first amplification FET 2 and the signal output line 12 in FIG. 5, a fast response of the follower circuit is required, and the bias current value must be increased. I have to. The value of the capacitance 20 associated with the cathode terminal of the photodiode 1 needs to be made as small as possible in order to improve its voltage response sensitivity.
The transconductance of 2 is small.

FIG. 7 shows a first standard MOS process.
Amplification FET 2 (gate width 7 μm, gate length 3 μm) and load FET 3 (gate width 70 μm, gate length 3 μm)
In the case of, the current value flowing through the load FET3 is 0.1
The relationship between the gate terminal potential (Vin) and the source terminal potential (Vo) of the first amplification FET 2 when the FET 22 and the FET 21 are set to be μA, 1 μA, 10 μA, 100 μA and 1 mA, respectively, in FIG. A, B,
Shown as C, D and E. Current value is 100 μA (D)
In the case of Vo, the potential of Vo drops by 2.4 V more than Vin, and the dynamic range becomes narrower as the low-voltage power supply is driven. The nonlinear response area is also increasing. Needless to say, further narrowing of the dynamic range is considered considering the output through the second amplification FET 4. Load F
If the current value of ET3 is about 10 μA (C), the dynamic range can be relatively secured.

However, if the photo-response voltage amplitude of the cathode potential of the photodiode 1 is 2 V, the response time is 40 nsec if the capacitance value associated with the gate terminal of the second amplification FET 4 having a large current driving capability is 200 fF. 5 MH
When one clock period is 200 ns during z reading, it becomes difficult to secure the reading period for bright output and dark output.

As described above, it is difficult for the image sensor of the conventional example to achieve both high sensitivity and high speed driving.
Further, since a simple increase in speed leads to an extremely narrow dynamic range, it is difficult to maintain a high S / N even if the exposure amount is increased.

[0014]

An image sensor according to the present invention comprises a photodiode, an inverting amplifier stage for amplifying the terminal potential amplitude of the photodiode, and a bright output amplifier F.
ET, a bright output transfer switch for transmitting the bright output of the inverting amplification stage to the gate of the bright output amplification FET, a reset switch for resetting the terminal potential of the photodiode, and a dark output amplification FET, A dark output transfer switch for transmitting the dark output of the inverting amplification stage to the gate of the dark output amplification FET, a bright output read FET for reading the output of the bright output amplification FET, and the dark output amplification A dark output read FET for reading the output of the FET is provided in each pixel stage, a scanning circuit for generating a pulse for driving the bright output read FET and the dark output read FET, and the bright output transfer switch. And a simultaneous pulse generation circuit that generates pulses for driving the output switch during dark and the reset switch at the same time. That.

Further, a dummy reset switch for applying a pulse having a phase opposite to the pulse applied to the reset switch to the photodiode is provided.

Further, each pair of the bright output amplification FET and the dark output amplification FET, and the bright output read FET and the dark output read FET are arranged so as to have a common center of gravity.

Further, it is assumed that the FET having the common center of gravity array has a gate shape in which the gate length becomes longer in the vicinity of the boundary of the element isolation region.

[0018]

In each pixel stage, the amplitude of the terminal potential of the photodiode is amplified by the inverting amplification stage. The bright outputs of the inverting amplification stages are transmitted to the gates of the bright output amplification FETs all at once via the bright output transmission switches and stored, and then the photodiodes are reset all together, and then the inverting amplification stages are reset. The dark outputs are simultaneously transmitted to the gates of the dark output amplification FETs via the dark output transmission switch and stored. After these simultaneous data sampling, each photodiode enters the accumulation period, and simultaneously outputs the two outputs of the bright output amplification FET and the dark output amplification FET, which are paired in each pixel, at the same time. This is done through the read FET and the dark output read FET. A high S / N ratio can be achieved by handling a differential output between the bright output and the dark output, and high-speed reading can be performed by simultaneously reading the bright output and the dark output.

Further, when the dummy reset switch is provided, the reset switch cancels the field-through voltage fluctuation exerted on the inverting amplification stage.

Further, each pair of the bright output amplifier FET and the dark output amplifier FET, and the bright output reading FE
The characteristics of T and the dark output readout FET are highly consistent due to the common center of gravity arrangement, and S / of the differential output between the bright output and the dark output
Improve N.

Further, the gate shape in which the gate length of the FET becomes longer in the vicinity of the boundary of the element isolation region is F due to variations in effective gate length and crystal defects in the vicinity of the boundary of the element isolation region.
The contribution to the ET characteristic variation is suppressed, the matching is further improved when the common center of gravity is arranged, and the S / N of the differential output is further improved.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. Although the conventional example is shown as an NMOS integrated circuit, a CMOS integrated circuit is used in the first embodiment. FIG. 1 is a circuit diagram of an image sensor according to the first embodiment of the present invention. This figure shows a circuit for three pixels. Reference numeral 1 is a photodiode, 6 is a reset switch for resetting the terminal potential of the photodiode 1, 7 is an inverting amplification driving FET in which a gate electrode is connected to the anode of the photodiode 1, and 8 is a source electrode of the drain electrode of the reset switch 6. The source electrode of the inverting amplification load FET 9 connected to the
2 is a bright output transfer switch, 10 is a dark output transfer switch whose source electrode is connected to the inverting amplification output line 32, 11 is a scanning circuit, and 14 is its gate electrode is a bright output transfer switch 9. A bright output amplifier FET connected to the drain electrode, 15 is a bright output read FET whose drain electrode is connected to the source electrode of the bright output amplifier FET 14, and 16 is a drain of the dark output transfer switch 10 whose gate electrode is dark. Dark output amplifier FET connected to the electrode,
Reference numeral 17 is a dark output readout FET whose drain electrode is connected to the source electrode of the dark output amplification FET 16, and 18 is inverting amplification driving F by turning on / off the reset switch 6.
A dummy reset switch for canceling the feedthrough voltage fluctuation applied to the gate of ET7, 19 outputs a pulse to the reset switch 6 of each pixel all at once, and outputs a pulse to the bright output transfer switch 9 of each pixel all at once. , A simultaneous pulse generation circuit for simultaneously outputting pulses to the dark output transfer switch 10 of each pixel, 25 is a chip changeover switch pair, 2
6 is a light output terminal, 27 is a dark output terminal, 31 is a flip-flop circuit for driving the chip changeover switch pair 25,
Reference numeral 32 is an inverting amplification output line.

Inversion amplification drive FET 7 and inversion amplification load FE
T8 constitutes an inverting amplifier circuit, but its gate size is small in length and width in order to avoid a decrease in the gate potential fluctuation amplitude due to the parasitic capacitance of the inverting amplification driving FET 7.
Therefore, the current driving capability of the inverting amplifier circuit is small. Therefore, since the response speed of the inverted amplification output accompanying the reset of the photodiode 1 is low as in the conventional example, it is preferable to reset all the pixels simultaneously during the blanking period.

The operation performed during the blanking period will be described below in order. The anode potential of the photodiode 1, that is, the gate potential of the inverting amplification driving FET 7 rises according to the exposure amount obtained during the exposure period, and the amplified potential drop of the amplitude fluctuation appears on the inverting amplification output line 32. . The fluctuation speed of the light intensity during the exposure period is usually about 100 μsec, which is slow, and there is no problem with the response speed.

In the blanking period, firstly, the bright output transfer switches 9 are turned on by the pulse from the simultaneous pulse generation circuit 19 and the output value of the inverting amplification output line 32 is changed to the gate of the bright output amplification FET 14. Communicate to and accumulate. After turning off the bright output transfer switch 9, secondly, the reset switch 6 is turned on all the pixels by the pulse from the simultaneous pulse generation circuit 19 to reset the photodiode 1. Since a reset period of about several microseconds can be ensured in the blanking period, the inverting amplification output based on the reset anode potential of the photodiode 1 can be output to the inverting amplification output line 3 even in the inverting amplification circuit having a small response speed.
2 can be obtained. Here, in order to simplify the circuit, the reset operation is performed by short-circuiting the input and output terminals of the inverting amplifier circuit, but the gate terminal of the inverting amplifier driving FET 7 may be short-circuited to a fixed potential prepared in advance.
By applying a reset pulse having a phase opposite to that of the pulse applied to the gate of the reset switch 6 to the gate of the dummy reset switch 18, the feed-through voltage fluctuation exerted on the gate terminal of the inverting amplification drive FET 7 by the reset switch 6 is canceled. This is an effective method to bring the inverting amplification output to a level within a predetermined range.

After the reset switch 6 is turned off, thirdly, a pulse from the simultaneous pulse generation circuit 19 causes the dark output transfer switches 10 to be turned on at the same time for each pixel to output the output value of the inverting amplification output line 32 in the dark. It is transmitted to the gate of the amplification FET 16 and accumulated. Immediately after the reset switch 6 is turned off, each pixel starts the operation of accumulating the next data. The output transmission switch 10 at dark is turned off, and the various operations during the blanking period are completed.

The scanning period begins following the blanking period. Read pulses are sequentially output from the scanning circuit 11 to turn on the bright output read FET 15 and the dark output read FET 17 for each pixel stage to obtain a pair of output signals at the bright output terminal 26 and the dark output terminal 27. . This paired output signal becomes an input signal to the differential amplifier circuit in the latter stage (not shown), and finally becomes a high S / N output signal.

In other words, in the present embodiment, the image sensor circuit configuration is such that the signals are simultaneously transmitted and reset in each pixel like the CCD or the like, thereby making it possible to use an inverting amplifier circuit having a slow response operation but a high amplification factor. Also, instead of the time series reading of the bright output and the dark output used in the conventional example, the bright output and the dark output are simultaneously read in parallel and the differential between the two is taken in the subsequent stage. High-speed reading that is more than twice that of the example is possible.

The chip changeover switch pair 25 receives the pulse from the flip-flop circuit 31 and turns on at the same time when the scanning and reading of the first pixel stage starts, and turns off at the same time when the scanning and reading of the last pixel stage ends. In order to maintain the read speed by avoiding an increase in the load capacitance of the common source line of the bright output read FET 15 and the dark output read FET 17, when a plurality of the configurations shown in FIG. is there.

Next, FIG. 2 is a block diagram of an image sensor in the second embodiment of the present invention. This figure also shows a circuit for three pixels. In this figure, the numbers, names and functions of the respective parts are the same as those in FIG. However,
FIG. 2 shows an image sensor including an NMOS integrated circuit as in the conventional example. Therefore, the difference from FIG. 1 is that all FETs are NMOSFETs,
Along with this, the connections are changed in polarity including the pulse, and the cathode terminal of the photodiode 1 is connected to the gate electrode of the inverting amplification driving FET 7. The scanning circuit 11, the simultaneous pulse generation circuit 19, the flip-flop circuit 31, etc. are naturally enhancement type NMOSs.
It is composed of a FET and a depletion type NMOSFET.

By adopting the configuration of FIG. 2, the following advantages are added to the advantages obtained in the first embodiment. That is, the NMOS integrated circuit has an advantage that the process cost is lower than that of the CMOS integrated circuit. Further, the potential of the inverting amplification output line 32 of the first embodiment in the dark time is the maximum output potential and decreases with exposure, whereas in the second embodiment, conversely, the inverting amplification output line 32 in the dark time. Is the lowest output potential, which rises with exposure. That is, the output current level flowing through the bright output terminal 26 and the dark output terminal 27 in the dark is lower in the second embodiment than in the first embodiment. Therefore, the second embodiment is caused due to the characteristic mismatch between the bright output amplification FET 14, the dark output amplification FET 16, the bright output read FET 15, and the dark output read FET 17, as compared with the first embodiment.
The differential output value between the bright output terminal 26 and the dark output terminal 27 in the dark is small, and a better S / N is realized.

It should be noted that while changing the above polarity, NMO
An image sensor of a PMOS integrated circuit can be realized by replacing the SFET with a PMOSFET.

By the way, in the above embodiment, high S / N
In order to achieve this, it is necessary that the bright output amplification FET 14, the dark output amplification FET 16, the bright output read FET 15 and the dark output read FET 17 forming a pair in each pixel stage have good element parameter matching. Is.
That is, the poor matching of the parameters of the FETs forming the pair becomes fixed pattern noise.

Therefore, in order to improve the matching of the device parameters, each FET is divided into a plurality of unit FETs, and the unit FETs of the FETs to be paired are cross-arranged with respect to each other with respect to the mask layout. FE that should do
Match the geometric centroids of Ts. Such examples are shown in FIGS. 3 (a), (b), (c), and (d).

FIG. 3A is a simple circuit notation. When the two FETs shown here are paired and the element parameter matching is required, each FET is divided into two parts, for example. 4 unit FETs as shown in 3 (b)
Consists of. In FIGS. 3A and 3B, terminals having the same symbol correspond to each other. The circuit diagram layout of each unit FET in FIG. 3B almost corresponds to the geometrical layout in the on-chip layout. Since the actual semiconductor process has a process gradient and changes depending on the position within the chip or wafer, the device parameters are FE.
T itself depends on the local position in the semiconductor substrate in which it is formed. Therefore, two Fs adjacent to each other
The device parameters are not sufficiently matched even between ETs.

P. R. Gray and R.G. G. Me
Yer co-authored “Analysis and Design”
of Analog Integrated Cir
cuits, 2nd ed. ", John Wiley
& Sons, Inc. According to the description on pages 393 and 709, a method for eliminating the adverse effect of the process gradient and improving the device parameter matching between two FETs is presented.

That is, as shown in FIG. 3B, the FETs whose terminals are completely connected in common are diagonally arranged, and the geometrical centers of gravity of the FETs that form a pair and have matching element parameters are matched with each other. To do. The equivalent coordinates on which the device parameters of the composite FET to which each terminal is commonly connected can be regarded as the barycentric coordinates of the coordinates of the unit FET group forming the same, and the device parameters of the composite FET can be considered to depend on the equivalent coordinates. Therefore, by matching the equivalent coordinates of other composite FETs with this equivalent coordinate, both composite FEs can be obtained.
The matching of element parameters between T can be improved well. The device parameter of the composite FET is the average value of the device parameters of the unit FETs that compose it.

In FIG. 3B, each FET has two unit FEs.
Although the case of being divided into T is shown, the consistency is further improved by adopting a configuration of further divided unit FETs if the design allows complexity.

FIG. 3C is a drawing in which the bright output amplification FET 14 and the dark output amplification FET 16 and the bright output read FET 15 and the dark output read FET 17 which are paired in FIGS. 1 and 2 are extracted and drawn. Equivalent to. This is also read for the amplification FETs 14 and 16 FE
FIG. 3D shows a state in which each FET is divided into two in order to match the element parameters of the FETs that should be paired with each other with respect to T15 and T17 as well. In FIGS. 3C and 3D, terminals having the same symbol correspond to each other. The circuit diagram layout of the unit FETs in FIG. 3D also substantially corresponds to the geometrical layout in the on-chip layout. Also in FIG. 3D, the unit FETs constituting each amplification FET are diagonally arranged, and the geometrical centers of gravity of the amplification FETs to be paired are made to coincide with each other to achieve matching of element parameters. In addition, the device parameters of each read FET are similarly matched.

In FIG. 3D, each FET has two unit FEs.
Although the case of division into T has been shown, if the complexity is allowed, the configuration can be further improved by adopting a configuration in which the unit FET is further divided. Amplification FET for light output
3 (b), since good matching is required only for the read FET and the dark output amplifier FET and read FET that belong to the same pixel and pair.
By dividing the FET into unit FETs and arranging them as illustrated in (d), it is easy to satisfy the requirement of matching the element parameters of the paired FETs,
An image sensor with high sensitivity and high S / N can be easily realized.

Another requirement for device parameter matching is good accuracy of the length and width of the effective gate of the FET. The effective gate size is determined by the mask that determines the element isolation region and the mask that determines the gate layer pattern. Inside the element isolation region, the gate length is determined to be a uniform value from the mask that determines the gate layer pattern, but near the element isolation region boundary, the gate length, the oxide film thickness below it, the effective gate length vary, and crystal defects also occur. It is easy to occur. Since one FET is considered as a parallel connection of FETs divided into small parts each having a small gate width, the gate length of the divided FETs in the vicinity of the element isolation region boundary, which may cause element parameter mismatch, is made longer than that of the other FETs. By reducing the contribution rate to the device, it is possible to suppress variations in device parameters and improve S / N when used in a differential input stage. In addition, such patterns are
Not limited to the FET, it can be applied to all kinds of FETs such as MESFET and JFET.

F in FIGS. 4A, 4B, 4C and 4D
An example of a plan view of ET is shown. 28 is a gate, 29 is an element isolation region boundary, and 30 is a window for electrically connecting the source or drain to a wiring pattern (not shown). FIG.
4A and 4B show a single FET in FIG.
(D) is a plan view of a two-stage series-connected FET.
By using together with the above common center of gravity configuration,
It is possible to realize a high S / N image sensor by improving element parameter matching.

[0043]

As described above, according to the present invention, a highly sensitive and high S / N amplification type MOS image sensor capable of high-speed reading can be realized at a low process cost.

Further, when the dummy reset switch is provided, it is possible to cancel the field-through voltage fluctuation which the reset switch exerts on the inverting amplification stage, and the inverting amplification output can be kept within a predetermined range.

When the paired FETs are arranged so as to have a common center of gravity, the matching of the element parameters is improved to eliminate fixed pattern noise, and the differential output between the bright output and the dark output is obtained. The S / N of can be improved.

By increasing the gate length of the FET near the boundary of the element isolation region, the matching of element parameters can be improved and the S / N ratio of the differential output can be further improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of three pixels of an image sensor according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of three pixels of an image sensor according to a second embodiment of the present invention.

FIG. 3 is a geometrical layout diagram of paired FETs used in an embodiment.

FIG. 4 is a plan view of an FET according to an example.

FIG. 5 is a circuit configuration diagram of one pixel of a conventional image sensor.

FIG. 6 is a timing diagram illustrating the operation of the conventional image sensor.

FIG. 7 is an input / output characteristic diagram of the first amplification FET of the conventional image sensor.

[Explanation of symbols]

 1 ... Photodiode 6 ... Reset switch 7 ... Inversion amplification drive FET 8 ... Inversion amplification load FET 9 ... Bright output transfer switch 10 ... Dark output transfer switch 11 ... Scanning circuit 14 ... Bright output amplification FET 15 ... Bright output read FET 16 ... Dark output amplification FET 17 ... Dark output read FET 19 ... Simultaneous pulse generation circuit 25 ... Chip changeover switch pair 26 ... Bright output terminal 27 ... Dark output terminal 28 ... Gate 29 ... Element isolation region boundary 31 ... Flip-flop circuit

Claims (6)

[Claims] 1. A photodiode, an inverting amplification stage for amplifying a terminal potential amplitude of the photodiode, a bright output amplification FET, and a bright output of the inverting amplification stage is transmitted to a gate of the bright output amplification FET. A bright output transfer switch, a reset switch for resetting the terminal potential of the photodiode, a dark output amplification FET, and a dark output for transmitting the dark output of the inverting amplification stage to the gate of the dark output amplification FET. Output transmission switch and the light output amplification FE
A bright output read FET for reading the output of T and a dark output read FET for reading the output of the dark output amplification FET are provided in each pixel stage, and the bright output read FET and the dark output read FET are provided.
And a simultaneous pulse generation circuit for generating pulses for driving the bright output transfer switch, the dark output transfer switch, and the reset switch at the same time for each pixel stage. An image sensor characterized in that 2. The image sensor according to claim 1, wherein the image sensor comprises only an NMOS or a PMOS. 3. The image sensor according to claim 1, wherein the photodiode is reset by a short circuit between the input and output terminals of the inverting amplifier circuit. 4. The image sensor according to claim 1, further comprising a dummy reset switch for applying a pulse having a phase opposite to that of the pulse applied to the reset switch to the photodiode. 5. The pair of bright output amplification FET and dark output amplification FET, and the bright output read FET and the dark output read FET, which are paired, are arranged so as to have a common center of gravity. The image sensor according to any one of claims 1 to 4. 6. The image sensor according to claim 1, wherein each FET has a gate shape having a longer gate length near the boundary of the element isolation region.