JPH0448861A - Image sensor - Google Patents

Abstract

PURPOSE:To reduce dispersion at a dark state and to prevent decreasing the S/N by using a CMOS transmission gate switch as a reset MOSFET switch to make a gate-drain capacitance of an N-channel MOSFET equal to a gate- drain capacitance of a P-channel MOSFET. CONSTITUTION:A switch of CMOS transmission gate structure in which a P- channel MOSFET and an N-channel MOSFET are connected in parallel is employed for a reset switch. The fluctuation of an anode level of a photo diode is much reduced by designing a gate-drain capacitance of the N-channel MOSFET to be equal to a gate-drain capacitance of the P-channel MOSFET in the CMOS transmission gate switch. Thus, a video signal is delayed to take a difference from a read signal at reset, then a dark state output and its dispersion are much reduced and a video signal with low FPN and high S/N is obtained.

Description

[Detailed Description of the Invention] Industrial Application Field Image sensors are used as the core devices of image input devices.
Low afterimage Conventional technology for image sensors that enable high-sensitivity reading Amplification type MOS, which has an amplification function for each pixel, is used as an image sensor to achieve high resolution and high S/N The image sensor is provided with an amplification function for each pixel by MO
By connecting to the gate of the SFET, the drain current is increased or decreased based on the gate potential modulation of the MOSFET according to the amount of carriers generated by the incident light. Although it can be reset to a constant potential after reading is completed by a reset switch connected to the gate terminal, the disadvantage of this type of image sensor is that each pixel has the MOSFET.
This is due to variations in the characteristics of the ET, which causes the S/N to deteriorate.
Variation in SFET amplification factor gII and the above MOSFET
The former causes variations in sensitivity, and the latter does not cause much of a problem as a video signal because it occurs mostly at the white level, where there is a large amount of light (the latter occurs at the black level, where there is little light, that is, in the dark). This is a very serious problem for video signals because the variation becomes noticeable in the output.The authors are currently applying for Japanese Patent Application No. 2-7386 as a method to reduce this dark output variation. Figure 2 (a) shows a summary of the
, (b) In this figure (a), 1 is a photodiode, 2 is an amplification MOSFET, 3 is a signal readout MOSFET, 4 is a reset MOSFET, 5
is a constant voltage source line, 6 is a signal readout line, 7
8 is a reset voltage source line where the gate potential of the amplification MOSFET is reset, and 8 is a readout MOSFET to which a readout pulse is applied to read out the signal from the main pixel.
9 is the gate terminal of a reset MOSFET to which a reset pulse is applied to reset the gate potential of the amplification MOSFET. This diagram (b) drives the pixel shown in this diagram (a). This is an example of the timing diagram, and is drawn assuming N-channel MOSFETs as the signal readout MOSFET and reset MOSFET. 4Yn is the readout pulse timing of this pixel, Rn is the reset pulse timing of this pixel, 1
0 is a period related to one pixel, and its breakdown is 11 video signal readout periods and 12 reset output readout periods. However, there is a delay in the output signal in each of the periods 11 and 12 above. If the difference is taken, the output variation in the dark period will be eliminated.In other words, in the dark period, the gate potential of the amplification MOSFET in the period shown by 11 and the period shown by 12 will be equal, and the delay difference output will be zero. Problems to be Solved by the Invention However, there are the following problems in the dark output removal method in the conventional example. In the period indicated by "H level here"
Level that turns off using L” level as a switch) I<
The 'H' level is used as the on level to connect the gate terminal of the reset MOSFET and the amplification MOSFET.
Since there is a parasitic capacitance between the gate terminal of the photodiode, that is, the anode terminal of the photodiode, the anode terminal potential of the photodiode is set to the voltage level of the reset voltage source line 7 during period 12. The anode terminal potential of the photodiode has already dropped slightly after the moment when the voltage changes to the "L" level. Therefore, the dark signal output read in period 11 and the reset signal output read in period 12 are not substantially equal.For this reason, even if the delay difference output is taken, it will not become zero (~ The amount of variation in the anode terminal potential of the diode is considered to be almost constant between each pixel, so even if the delay difference output is not zero, if the delay difference output is equal between each pixel, a simple offset output will appear and there will be no problem. However, in reality, there are variations in the gm of the amplifying MOS FETs. Even if the amount of variation in the anode terminal potential of the photodiode is the same between each pixel, the drain current value will not be constant between each pixel and will eventually Means to solve the problem In the above problem, an N-channel MOSFET is used as a switch to reset the anode potential of the photodiode, that is, the gate potential of the amplification MOSFET. As a result of using one, the anode potential of the photodiode fluctuates. In other words, the reset is performed with a single pulse. Since it is supposed to take the delay difference between the output drain currents that are included as they are, there is no residual output variation during the dark period. Therefore, the reset MO
A CMOS transmission gate switch is used as the SFET switch, and the design is made so that the capacitance between the gate and drain of the N-channel MOSFET and the capacitance between the gate and drain of the P-channel MOSFET in the CMOS switch are equal. 1. The fluctuations in the anode potential of the photodiode can be made extremely small by 4.
Operation The present invention has the above-mentioned configuration, and the reset CMOS
When the switch changes from the on state to the off state, the main reset CMO is applied to the anode potential of the photodiode.
The fluctuation in the negative direction caused by the N-channel MOSFET in the S switch through parasitic capacitance and the P-channel MOSFET
The fluctuation in the positive direction given by the SFET through the parasitic capacitance is exactly canceled out, and the fluctuation in the anode potential of the photodiode at the moment when the reset switch turns off can be made extremely small in total. The influence of gm variations of each amplifying MOS FET on the delay difference output can be extremely minimized, and dark-time variations can be reduced to prevent a drop in S/N. An image sensor according to an embodiment of the invention will be described with reference to the drawings.
MOSF for amplification even in the circuit diagram and timing diagram for each pixel
Even if a CMOS transmission gate switch is used as a reset switch to set the ET gate potential to the reset voltage value, the parts indicated by numbers 1 to 12 in this figure are the same numbers as in the above-mentioned figure 2. The signal readout pulse and reset pulse that are equal and input to the gate terminal 8 of the signal readout MOSFET and the gate terminal 9 of the reset MOSFET, respectively, are Y in FIG. 2(b).
Since it is equal to n and Rn, explanation and illustration are omitted.
The one indicated by 13 in the figure (a) is a reset MOSFET similar to 4 (it has a different conductivity type from 4, and by connecting it in parallel with 4 as shown in this figure) The pulse input to the gate of the reset MOSFET 13 forming the CMOS transmission gate switch is the reset pulse input to the gate terminal 9 of the reset switch 4, which is inverted by the inverter 14, as shown in Figure (b).
Indicated by Rn'.

Next, we will explain the operation of the image sensor of the present invention, and the operation timing diagram is shown in FIG. There is a period 11 and a reset output readout period 12 in which a reset pulse that resets the potential of the photodiode is input in addition to the readout pulse and the video signal at the time of reset is read out.Mu video signal readout pulse Yn and reset pulse Rn, R
By using a half-pit shift signal such that n' has a period in which the operation period is shared with each other, the output signal from one shift register can be used as a read pulse or a reset pulse without any complicated processing. The advantage of the design is that it is thick (~ MO for amplification for each pixel)
Sensors with SFET have high speed, low afterimage, and high sensitivity readout.
occurs and degrades the S/N.In order to eliminate this, it may be possible to perform subtraction processing between the readout at reset and the delayed video signal to remove the FPN.A MOSFET with a single reset switch At the time of reset, the reset switch is on, so the gate terminal potential of the amplifying MOSFET 2 is equal to the potential of the reset voltage source line 7. However, when this reset switch is off, the reset pulse potential fluctuation is caused by capacitive coupling to the amplifying MOSFET 2. Unlike the potential of the reset voltage source line 7, the gate potential of the MOSFET for amplification when reading out video signals in the dark also remains the same.Therefore, even after delay subtraction processing of the drain current output, the dark output remains the same. appears, and there may be variation (FPN) in its value due to non-uniformity of the amplification factor gm of each pixel.a The image sensor of the present invention has a P-channel MOSFET and an N-channel MOSFET connected in parallel as a reset switch. Using a switch with a CMO8 transmission gate configuration, it is extremely simple to make the reset pulses input to the two gate terminals of the CMOS transmission gate switch complementary to each other.Therefore, the reset pulses input to the two gate terminals are very simple. The capacitively coupled potential fluctuations each applies to the gate terminal of the amplification MOSFET have opposite polarities and cancel each other out. By designing the CMOS transmission gate switch so that the capacitance between the gate and drain of the N-channel MOSFET and the capacitance between the gate and drain of the P-channel MOSFET are equal, fluctuations in the anode potential of the photodiode can be made extremely small. Therefore, if the video signal is delayed and the difference from the reset readout signal is taken, the dark output and its variations can be suppressed to an extremely low level, and a video signal with low FPN and high S/N can be obtained.
Figures (a) and (b) show a circuit diagram of an amplified MOS image sensor of the present invention having a plurality of pixels and a timing chart of scanning signals. 1 to 5 and 7, 13 in this figure (a).
The part indicated by the number 14 is the same as the part with the same number in FIG. A readout line, 15 is a shift register for sequentially reading optical information of a plurality of pixels, 16 is a start pulse input terminal of the shift register to start scanning, 17 is a clock pulse input terminal of the shift register. , 18 is a carry pulse output terminal for transmitting a scanning signal to the start pulse input terminal of the next stage image sensor when a plurality of image sensors shown in this figure are arranged in series to form a long image sensor. Ah, L 19A to 19L are shift register output terminals, 19A only reads out the video signal of the first pixel, rows t and X, 19L only resets the last pixel, and the others reset and read out adjacent pixels. 20A to 2OL in this figure (b) are 19A in this figure (a), respectively.
It represents the signal of the shift register output terminal of ~19L, and the "H" level is the level at which the signal readout switch and reset switch can be turned on. Next, the operation of the image sensor shown in Fig. 3 will be explained. Also input a start pulse with a predetermined pulse width to 16 and output it to the output terminals 19A-19L of the shift register at 2 in the timing diagram.
Even if a scanning signal such as 0A to 2OL in which the pulses overlap in time appears, the first half of the time when 2OA is "H" is the video signal readout output of the first pixel, and the second half is the output when the first pixel is reset. There is a wind leak in the output line 6A.Following this, the output line 6A has the video signal readout output of the 3rd pixel, the output of the 3rd pixel at reset, the video signal readout output of the 5th pixel, the output at the time of reset of the 5th pixel, and the following. The video signal readout output of even-numbered pixels and the reset output are sequentially output to the output lines of 6B. By designing the difference between the gate and drain capacitance of the N-channel MOSFET and the gate-drain capacitance of the P-channel MOSFET in the CMOS transmission gate switch to be equal, the capacitance of the anode of the photodiode can be reduced. Although it is possible to extremely minimize the coupling potential fluctuation, it is also possible to extract a low fixed pattern noise (FPN) and high S/N video signal from the output lines 6A and 6B, which suppresses the dark output and its variations to an extremely low level. In this embodiment, the anode terminal of the photodiode is common to the gate terminal of the amplification MOSFET, but even if the cathode terminal is common to the gate terminal of the amplification MOSFET, the effectiveness of the present invention will not change. What?
, % Furthermore, the effectiveness of the present invention remains the same regardless of whether the conductivity type of each MOSFET is N-channel or P-channel.
When T is an N-channel type and its gate terminal is common to the anode terminal of the photodiode, and when the amplification MOS
If the FET is a P-channel type and its gate terminal is common to the cathode terminal of the photodiode, both exhibit positive output characteristics. In other words, the larger the incident light is, the thicker the output current is t%. If the gate terminal is common to the anode terminal of the photodiode, both exhibit negative output characteristics. In other words, the larger the incident light, the smaller the output current 1.%
In the case of a negative type, the dark output current is larger than the bright output current, so the influence of the gm variation of the amplification MOSFET becomes large, and the dark output variation when the present invention is not used is extremely severe. Therefore, although a positive type is preferable as a combination of a photodiode and an amplification MOSFET, when applying the present invention, a sensor configuration using a positive type combination will result in a better dark output. Although variations can be reduced, the Mbozi type sensor configuration essentially means that both a P-channel MOSFET and an N-channel MOSFET can be formed on the same semiconductor substrate. According to the present invention, the fixed pattern noise of the amplified MOS image sensor can be suppressed to an extremely low level, and it is possible to reduce the fixed pattern noise of the amplified MOS image sensor. High speed, low afterimage, readout not only with high sensitivity but also with high S/N. Therefore, the image sensor of the present invention is extremely useful as an image input device and has great industrial effects.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are one embodiment of the present invention.
Circuit diagram and timing chart for each pixel Figure 2 (a) and (b)
) is a circuit diagram and timing diagram for one pixel of a conventional amplification type MOS image sensor. Figures 3 (a) and (b) are a circuit diagram and scanning signal of an amplification type MOS image sensor of the present invention having multiple pixels In the timing diagram, 1...photodiode, 2... MOSF for amplification
ET, 3...MOS FET for signal readout,
4... MOSFET for reset, 5... Constant voltage source line, 6,6 6B... Rice for signal readout 7... Reset voltage source line, 8... Gate terminal of signal readout MOSFET, 9...・MO for reset
SFET gate terminal, 10...1 in the timing diagram
Period 11JL related only to pixels 11...Video signal readout morning drive 12...Output readout morning drive at reset 13...Reset MOSFET of opposite conductivity type to reset MO5EPET4, 14...Inverter 15.
...Shift register 16--Start pulse input terminal, 17...Clock pulse input terminal, 18...
Carry pulse output terminal, 19A-19L...Shift register output terminal, 20A-20L...Signal wave appearing at shift register output terminal 19A-19L Name of agent Patent attorney Shigetaka Awano 1 person Photo die 1- 4- Reset W @ 165FET 71 MCISFET for diode increase % H1lfigW field L jlM 65 FET MO5FET for cut (b)

Claims (2)

[Claims] (1) Each pixel is a photodiode and MOSFET for amplification
, video signal readout MOSFET, reset MOS
It is an amplification type MOS image sensor consisting of an FET and a shift register for generating a scanning signal, and there is a period in which only the MOSFET for reading out the video signal is turned on according to the scanning signal and outputting the video signal, and then a period in which only the MOSFET for reading out the video signal is turned on and then in addition to the MOSFET for reading out the video signal is turned on. In an image sensor configured to sequentially read out the above two types of output signals for each pixel, in order to extract the difference between the two output signals for each pixel, the reset MOSFET is also turned on and a period for obtaining a reset output is provided. An image sensor characterized in that the reset MOSFET is a CMOS transmission gate switch in which two MOSFETs of different conductivity types are connected in parallel. (2) The image sensor according to claim 1, wherein the conductivity type of the semiconductor of the terminal of the photodiode commonly connected to the gate electrode of the amplification type MOSFET is different from the conductivity type of the channel of the amplification type MOSFET. .