JPH08242330A - Image sensor and fixed pattern noise removing system - Google Patents

Abstract

PURPOSE: To suppress a fixed pattern noise and to obtain a high SN ratio at high sensitivity by executing differential I/V conversion for bright and dark signal currents outputted from a pair of common signal lines and obtaining a difference between the first half output voltage and latter half output voltage of an access pulse. CONSTITUTION: Signal voltage immediately before reset and signal voltage immediately after the reset which appear on individual electrodes of all photodiodes 1a are amplified by a picture element amplifier and the amplified voltage levels are respectively stored by respective sampling means as bright signal voltage and dark signal voltage. In a reading period, signal currents based upon a pair of stored signal voltage levels are successively outputted to a bright signal common signal line 9 and a dark signal common signal line 10 through a pair of access MOS-FETs 5a, 5b is accordance with an access pulse outputted from a shift register 8. Differential I/V conversion for the bright and dark signal currents outputted from the lines 9, 10 is executed to find out a difference between the first half output voltage and latter half output voltage of the access pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor capable of reading original information at high speed and high gradation and its amplifier.

[0002]

2. Description of the Related Art With the development of information and communication equipment, the need for an image sensor as an input device has increased. I
With the development of C and LSI, seeds for manufacturing image sensors have been developed, and CCD image sensors and MOS image sensors have been developed and put into practical use. The focus of development is high resolution, S / N improvement, high speed, simplification of circuits including peripherals, and cost reduction. Normal MO these days
Amplified MO that can be manufactured by S-IC process and has high sensitivity
Development of S image sensor is active.

As shown in FIG. 5, a conventional amplification type MOS image sensor (Japanese Patent Laid-Open No. 3-110962 and Japanese Patent Laid-Open No. 4-126445) uses a photodiode 30, a V / I conversion MOS-FET 31, and an access. MOS-FET 32, reset MOS-FET 33 for photodiode 30, reset pulse generation NAND
Gate 34, shift register 35, reset power supply 36,
An image signal output line 37 and a reset timing pulse input terminal 38 are provided. Reference numerals 39 and 40 respectively denote a start pulse input terminal and a clock pulse input terminal of the shift register, 41 denotes an output terminal of a transmission pulse between chips when a long sensor is formed with a multi-chip configuration, and 42. Is the positive power line. An operation timing chart of this amplification type MOS image sensor is shown in FIG. Y1,
Y2 and Y3 to Yn are access pulses output from the shift register 35, and RS is a reset timing pulse. The reset pulse of each pixel is generated by taking the NAND of RS and the access pulse. In each pixel, the signal voltage after discharge from the individual electrode of the photodiode 30 due to the photocurrent, that is, the bright signal voltage immediately before the reset, and the signal voltage before discharge due to the photocurrent immediately after the reset are the V-I conversion MOS-FET 31. Is output to the gate of. Access pulses Y1 and Y from the shift register 35
2. Access MOS-FE sequentially according to Y3 to Yn
By making T32 and subsequently the reset MOS-FET 33 conductive, a time-series image signal can be obtained at the image signal output line 37.

In this sensor, for each photodiode, the signal current amplified by the V-I conversion MOS-FET 31 arranged close to it is accessed by the access MOS-FET 3.
Random noise can be made extremely small because it is output via 2. However, due to the nature of the circuit, the offset signal is output even in the dark, and the VI conversion MOS-FET 31 and the access MOS-FET 3 are output.
The offset signal becomes non-uniform due to the variation in the characteristics of 2 between the pixels, which causes fixed pattern noise (FPN).
There is a drawback that Therefore, the FPN is reduced by taking the difference signal between the bright signal based on the potential of the individual electrode of the photodiode immediately before the reset and the dark signal based on the potential of the individual electrode of the photodiode immediately after the reset outside the chip. In this method, it is necessary to perform three kinds of operations of a bright signal output, a reset operation, and a dark signal output during the reading cycle of one pixel, which is an obstacle to high-speed reading. The image sensor of FIG. 5 is called an amplification type MOS image sensor and can obtain an amplified current signal, but the signal voltage sensitivity itself of the pixel portion is not amplified. Therefore, the sensitivity is insufficient for use in the low exposure range.
With this type of sensor, a method of increasing the signal voltage sensitivity by attaching a voltage amplifier between the individual electrode of the photodiode 30 and the gate of the V / I conversion MOS-FET 31 can be considered. A response speed that is approximately three times the pixel read cycle is required, and it is difficult to attach such a high-speed amplifier to each pixel.

[0005]

In the conventional amplification type MOS image sensor, in order to enable FPN correction, there are three types of output timings of a bright signal and a dark signal and a reset timing during a read clock cycle of one pixel. Timing was needed. This was an obstacle to high-speed reading. In addition, in the conventional amplification type MOS image sensor, the signal voltage based on the potential of the individual electrode of the photodiode is output through the follower circuit and current-amplified, but the signal voltage from the pixel is not amplified. Therefore,
The sensitivity is insufficient for use in the low exposure range.

[0006]

An image sensor includes a photodiode and a reset switch, a pixel amplifier, a means for sampling and retaining an image signal (bright signal) immediately before reset output from the pixel amplifier, and an image signal (dark signal) immediately after reset. Signal) sampling and holding means, a pair of V / I conversion and access MOS-FETs that operate by receiving the held bright signal and dark signal at their gates, set to a voltage close to the dark signal in the latter half of the access pulse M for a pair of sets
A plurality of pixels composed of OS-FETs, a shift register for generating an access pulse, a power supply for setting, a common signal line for bright signals which is commonly connected to the source electrodes of access MOS-FETs on the bright signal side, The common signal line for dark signals is formed by commonly connecting the source electrodes of the access MOS-FETs on the dark signal side. After the first pair of bright and dark signal currents are output from the common signal line for bright signal and the common signal line for dark signal respectively in the first half of the access pulse of each pixel, and in the latter half of the access pulse, the setting MOS-FET. Are turned on to output a second pair of signal currents based on the set voltage from the common signal line for bright signals and the common signal line for dark signals, respectively, and pair with the difference signal of the pair of first signal currents. The difference of the difference signals of the second signal current that forms the output signal.

[0007]

The signal voltage immediately before reset and the signal voltage immediately after reset appearing on the individual electrodes of all the photodiodes are voltage-amplified by the pixel amplifier and then held as the bright signal voltage and the dark signal voltage by the respective sampling means. This operation is performed simultaneously for all pixels before the reading period. Therefore, it is possible to spend several clock cycles for the operation of the pixel amplifier, and a simple low-power-consumption, low-speed, high-gain amplifier can be configured. In the read period, a pair of access MOS-FETs are supplied with a signal current based on the pair of held signal voltages according to the access pulse from the shift register.
Are sequentially output to the bright signal common signal line and the dark signal common signal line. However, at the timing of the latter half of the access pulse, the setting MOS-of each pixel is
It is assumed that the FET is turned on and the correction signal of each pixel is output. As described above, the fixed pattern noise is generated by performing the differential I / V conversion on the bright and dark signal currents output from the pair of common signal lines and obtaining the difference between the output voltage of the first half and the output voltage of the second half of the access pulse. It becomes possible to dramatically control.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an equivalent circuit of the image sensor according to the first embodiment of the present invention, and particularly shows three pixels. FIG. 1 shows a signal detection unit 1, a pair of MOS-FETs 2a and 2b for sampling a bright signal and a dark signal, capacitors 3a and 3b for holding the bright signal and the dark signal, and a held bright signal and a dark signal. A pair of voltage-current converting MOS-FETs 4a and 4b which operate upon receipt of the gate
And a pair of access MOS-FETs 5a and 5b
And a pair of setting MOS-FETs 6a and 6b,
A plurality of pixels including a NAND gate 7 for generating a set pulse, a shift register 8 for generating an access pulse, and a bright signal side access MOS-FE
A common signal line 9 for bright signal, which is formed by commonly connecting the sources of T (5a and equivalent MOS-FET) between pixels,
A common signal line 10 for dark signals, which is formed by commonly connecting the sources of access MOS-FETs (5b and equivalent MOS-FETs) on the dark signal side between pixels, and a power supply 11 for setting.
Etc. In this figure, MOS-FETs 1b, 1
c, 1d, 2a, 2b, 6a and 6b are P-channel type, and the MOS-FETs 4a, 4b, 5a and 5b are N-channel type. The signal detection unit 1 is a photodiode 1a
And drive MOS-FET 1b and load MOS
An inverting amplifier composed of -FET 1c and a reset MOS-FET 1d for the photodiode 1a,
After the signal voltage appearing on the individual electrode of the photodiode 1a is amplified by the inverting amplifier, the drive MOS-FET
It is output to the drain of 1a. Terminals 12 and 13 are clock pulses for operating the shift register,
A start pulse input terminal, 14 is an output terminal of a transmission pulse between chips when a long sensor is formed with a multi-chip configuration, and by connecting this terminal to a start terminal 13 of the next stage, A serial image signal can be obtained. Reset MOS-FET at intervals of storage time
By conducting 1d, the input and output terminals of the inverting amplifier are short-circuited, and the individual electrode of the photodiode is
The voltage is reset to a voltage uniquely determined by the constants of the FETs 1b and 1c. In the prototype sample, the reset voltage was about 3.2V. Immediately before the reset pulse, a signal based on the terminal voltage of the photodiode after discharge by the photocurrent, that is, a bright signal voltage is output to the drain of the drive MOS-FET 1b, and the sample MOS-FET 2a becomes conductive and held in the capacitor 3a. It Immediately after the reset pulse, the signal based on the terminal voltage of the photodiode before the discharge due to the photocurrent, that is, the dark signal voltage is the driving MOS.
-Sample MOS output to the drain of FET1b
-The FET 2b becomes conductive and is held by the capacitor 3b.
In the IC, the capacitor generally occupies a large area, but since the capacity of the terminal to be output is small in this circuit, it is possible to substitute the parasitic capacity for the capacitors 3a and 3b, so that the chip area is reduced. Is convenient for.

FIG. 2 is an operation timing chart of the image sensor according to the first embodiment of the present invention.
S, bright signal sample pulse SP1, dark signal sample pulse SP2, clock pulse CK applied to shift register, start pulse ST, access pulses Y1, Y2, Yn from shift register and common signal line 9 for bright signal The output bright signal current Is and the output dark signal current In from the dark signal common signal line 10 are shown. As can be seen from the circuit in FIG. 1, SP1, R
S and SP2 are applied to all pixels at the same time before reading, and the bright signal voltage and the dark signal voltage are respectively applied to the capacitors 3a.
And 3b. In the first half of the access pulse, the access MOS-FETs 5a and 5b are turned on, and the signal current Isi based on the bright signal voltage held in the capacitor 3a from the bright signal common signal line 9 and the dark signal common signal line 10 are obtained.
Outputs a signal current Ini based on the dark signal voltage held in the capacitor 3b. The set pulse of each pixel is formed by a NAND gate from a clock pulse and an access pulse, and a pair of set MOS-FETs 6 are provided.
applied to the gates of a and 6b, the setting MOS-FET conducts in the latter half of the access pulse, and a voltage Vset close to the holding voltage in the dark state is applied to the gates of the pair of V / I conversion MOS-FETs 4a and 4b. When applied, the common signal line 9 for bright signals and the common signal line 10 for dark signals output respective signal currents Isd and Ind in a state close to a dark signal.
If Vset is equal to the gate voltage of the MOS-FET 4a in the dark state, Ini = Ind.

Next, the principle of fixed pattern noise (FPN) removal will be described. FPN is a pair of M for V / I conversion
OS-FETs 4a and 4b and a pair of access MOSs
-It is caused by the mismatch of the element characteristics of the FETs 5a and 5b. The device characteristic mismatch is caused by a dimensional mismatch of gate width / gate length (W / L) and non-uniformity of the doping concentration of the well diffusion layer. Figure 3 is V / I
Conversion MOS-FET (for example, 4a) and access MO
In a series circuit of S-FET (for example, 5a), V / I
For the voltage Vg applied to the gate of the conversion MOS-FET, the current output to the source of the access MOS-FET is converted into the gate width / gate length (W / L) of the MOS-FET.
Is plotted as a parameter. The inset is a partially enlarged view of this characteristic diagram. Curve a is the gate voltage V
The output current from the Is terminal with respect to g is shown, and the curve b also shows the output current from the In terminal with respect to the gate voltage Vg. In this figure, the gate length of the MOS-FET on the Is terminal side is that of the In terminal side. It shows a case where the gate length is 5% smaller. In the prototype sample, the output voltage of the inverting amplifier is about 3.2 V when there is no discharge due to the photocurrent of the photodiode immediately after reset. In the dark state, since there is no discharge due to the photocurrent of the photodiode, there is no fluctuation in the voltage of the individual electrode of the photodiode, and thus the output voltage of the inverting amplifier is maintained at 3.2V. On the other hand, in the bright state, the voltage of the individual electrode of the photodiode increases, the output voltage of the inverting amplifier decreases, and the output current Is decreases along the curve a due to the discharge by the photocurrent. The fixed pattern noise refers to a signal variation between pixels in a dark state, and in the case of FIG. 3, the difference between Is and In is 14 μA. From the current sensitivity of 9 mA / lx.s in the prototype sample,
Exposure amount 0.025 lx. The S / N at s is 24 dB. Since S / N = 40 dB is required for practical gradation expression, it cannot be used as it is for applications requiring gradation. Only by improving the MOS process, the characteristic variation of the paired MOS-FET is S / N = 40 dB.
It is difficult to suppress it to a certain degree.

In the first embodiment of the present invention, in each pixel, a pair of V / I conversion MOSs are provided in the latter half of the access pulse.
By setting the gate of the FET to the holding voltage at the dark signal, the correction currents of Is and In of each pixel are obtained. That is, in the first half of the access pulse, the paired MOS
-A signal current including a mismatch between Is and In due to FET characteristic variations is output, and I is output in the latter half of the access.
The mismatch components of s and In are output. Hereinafter, the principle of FPN correction will be described using the linear approximation (refer to the inset in FIG. 3) near the output voltage of the inverting amplifier and 3.2 V. When the signal currents from the Is terminal and the In terminal in the first half of the access pulse are Isi and Ini, respectively, Isi = (gm + Δgs) · Vs + ΔIst (1) Ini = (gm + Δgn) · Vn + ΔInt (2) become. Therefore, Vs and Vn are the bright signal holding voltage,
It is a dark signal holding voltage. Δgs and Δgn represent the difference in the slope of the straight line, and ΔIst and ΔInt represent the difference in the intercept from the horizontal axis. With the set voltage as Vset, the signal currents from the Is terminal and the In terminal in the latter half of the access pulse are Isd and Ind.
Then, Isd = (gm + Δgs) · Vset + ΔIst (3) Ind = (gm + Δgn) · Vset + ΔInt (4) In the present invention, since the Vset voltage is set to a value close to the dark signal holding voltage, it can be written as Vset = Vn + ΔVn. When Equations (3) and (4) are modified using this relationship, Isd and Ind are approximately represented by the following equations.

Isd = (gm + Δgs) · Vn + (gm + Δgs) · ΔVn + ΔIst (5) Ind = (gm + Δgn) · Vn + (gm + Δgn) · ΔVn + ΔInt (6) That is, in the image sensor of the present invention, the signal current due to the characteristic mismatch in the dark state can be obtained from the Is terminal and the In terminal.

These signal currents are input to the differential amplifier. The output signal of the differential amplifier in the first half of the access pulse is Isi-Ini = (gm + Δgs) · Vs− (gm + Δgn) · Vn + ΔIst−ΔInt (7) The output signal of the differential amplifier in the latter half of the access pulse is Isd−Ind = (Δgs−Δgn) · Vn + ΔIst−ΔInt + (Δgs−Δgn) · ΔVn (8) The difference signal between the differential output signal in the first half of the access pulse and the differential output signal in the latter half of the access pulse is represented by the following equation.

(Isi−Ini) − (Isd−Ind) = (gm + Δgs) · (Vs−Vn) − (Δgs−Δgn) · ΔVn (9) When the Vset voltage is equal to the dark signal holding voltage , That is, Δ
When Vn = 0, the differential signal of the differential output signals is proportional to the difference between the bright signal holding voltage and the dark signal holding voltage, and the I / V conversion MOS
The FPN correction is perfect, independent of the characteristics of the -FET and the access MOS-FET. However, Vset
If there is a difference of ΔVn between the voltage and the dark signal holding voltage,
Although the error of the second term of Expression (9) occurs, this term is an extremely small value because it is a square value of a minute value, and it is considered that the correction effect is sufficient. In fact, the sensor chip has a large number of pixels, and the MOS that constitutes the inverting amplifier of each pixel
-Differences in the characteristics of the FETs 1b and 1c cause variations in the dark signal voltage at the output terminal of the inverting amplifier between pixels. Therefore, it is impossible to set the gate voltage of the I / V conversion MOS-FETs of all the pixels on the chip to each dark signal voltage with one set voltage Vset. When the output voltage of the inverting amplifier fluctuates to 3.2 V plus or minus 0.1 V, that is, when ΔVn = 0.1 V, the correction error is 1 μA as shown in the inset in FIG. The correction current according to the invention reduced the error current from 14 μA to 1 μA. Therefore, the F after correction at an exposure dose of 25 mlx.s
The PN is 47 dB, and reading is possible that is sufficient for practical gradation expression.

FIG. 4 is an equivalent circuit of the FPN correction amplifier used in the image sensor of the present invention in the second embodiment of the present invention, which comprises an I / V conversion circuit 20, a differential amplifier 21, a clamp circuit 22, and a buffer 23. There is. 24
Is an input terminal for the control signal of the clamp SW. The I / V conversion circuit 20 is a circuit that converts a pair of signal currents Is and In output from the image sensor chip into a voltage, and can be easily configured by, for example, a pair of grounded base transistors, a resistor, a bias power supply, and the like. . If the conversion impedance of the I / V conversion circuit is Z, the converted signal voltage V
It can be written that s = Z · Is and Vn = Z · In. The differential amplifier 21 amplifies the difference between the pair of signal voltages converted into the voltage, and Vout.f = in the first half of the access pulse.
A signal voltage of Z · (Isi−Ini) is output, and a signal voltage of Vout.b = Z · (Isd−Ind) is output in the latter half of the access pulse. The second half Vout.b is the correction signal, and Vo
The clamp circuit 22 is a circuit for calculating ut.f-Vout.b. That is, the clamp SW is turned on at the time of outputting Vout.f to store Vout.f in the capacitor, and turned off at the time of outputting Vout.b, and the difference signal, that is, the corrected signal is stored in the buffer 2
3 input terminals can be obtained. A correction signal with a low impedance is output from the output terminal of the buffer 23.

[0016]

As described above, the present invention outputs the dark level correction signal in the latter half of the access pulse of each pixel in the simultaneous capture type image sensor, and the fixed pattern noise (FPN) is easily generated by the correction operation. It becomes possible to reduce. Further, the FPN correction amplifier used in the image sensor of the present invention can also be configured by a simple circuit. Therefore, the present invention can provide an image sensor having a high sensitivity and a large S / N, and has a great industrial effect as a high performance reading device.

[Brief description of drawings]

FIG. 1 is a diagram showing an equivalent circuit of an image sensor according to a first embodiment of the present invention.

FIG. 2 is a timing diagram of the image sensor according to the first embodiment of the present invention.

FIG. 3 is an explanatory view showing the cause of FPN and countermeasures.

FIG. 4 is a circuit diagram of an FPN correction amplifier according to a second embodiment.

FIG. 5 is a diagram showing an equivalent circuit of an amplification type MOS image sensor in a conventional example.

FIG. 6 is an operation timing chart of the amplification type MOS image sensor.

[Explanation of symbols]

 1 signal detection unit 1a photodiode 1b drive MOS-FET 1c load MOS-FET 1d reset MOS-FET 2a, 2b pair of sample MOS-FETs 3a, 3b pair of holding capacitors 4a, 4b pair of V / I-conversion MOS-FETs 5a, 5b A pair of access MOS-FETs 6a, 6b A pair of set MOS-FETs 7 NAND gates 8 Shift register 9 Common signal line for bright signal 10 Common signal line for dark signal 11 Power supply for set 12 input terminal of clock pulse 13 input terminal of start pulse 14 output terminal of transmission pulse between chips 20 I / V conversion circuit 21 differential amplifier 22 clamp circuit 23 buffer circuit 30 photodiode 31 V / I conversion MOS-FET 32 Access MOS-FE T 33 Reset MOS-FET 34 Reset pulse generation NAND gate 35 Shift register 36 Reset power supply

Claims (7)

[Claims] 1. A photodiode, a reset switch, a pixel amplifier, a means for sampling and holding an image signal (bright signal) immediately before reset output to the output terminal of the pixel amplifier, and a sample image signal (dark signal) immediately after reset. Holding means, a pair of V / I conversion and access MOSs which operate by receiving the held bright signal and dark signal at their gates
Field effect transistor (MOS-FET), a pair of V
/ I conversion MOS-FET has a plurality of pixels each including a pair of setting MOS-FETs for setting the gate to a voltage close to a dark signal, a shift register for generating an access pulse, a setting power supply, and a bright signal side. MO for access
Common signal line for bright signal formed by commonly connecting the source electrodes of S-FETs, access MOS-FET for dark signal side
An image sensor, comprising a common signal line for dark signal, which is formed by commonly connecting source electrodes of the above. 2. A pixel amplifier is an inverting amplifier which is an enhancement MOS transistor in which an individual electrode of a photodiode is connected to an input gate electrode, and a reset switch is a drain of a driving MOS-FET of the inverting amplifier.
The image sensor according to claim 1, wherein the photodiode and the amplifier are reset at the same time by connecting between the gates. 3. A transfer MOS means for sampling and holding an image signal immediately before and immediately after resetting.
-It consists of FET and voltage holding capacitor, and turns on the transfer MOS-FET according to the sample pulse.
The image sensor according to claim 1, wherein 4. The first pair of bright and dark signal currents are respectively output from the bright signal common signal line and the dark signal common signal line in the first half of the access pulse of each pixel, and then in the latter half of the access pulse. By setting the setting MOS-FET to be conductive, the second signal based on the setting voltage from the bright signal common signal line and the dark signal common signal line, respectively.
A pair of signal currents is output, and a difference between a difference signal between a pair of first signal currents and a pair of second signal currents is used as an output signal. 5. The image sensor according to claim 1, wherein
The fixed pattern noise elimination method according to claim 4, wherein the setting voltage is set to a voltage value near the center of the output voltage of the pixel amplifier of each pixel. 6. A pair of I / V converters, differential amplifiers, clamp circuits which operate by receiving respective signal currents from the image signal line for bright signal and the image signal line for dark signal of the sensor according to claim 1. Fixed pattern noise elimination amplifier consisting of a buffer circuit. 7. A clamp circuit comprises a capacitor and a MOS-FE.
7. The fixed pattern noise elimination amplifier according to claim 6, comprising a clamp switch made of T, turning on the switch in the first half of the access pulse of each pixel, and outputting the image signal corrected in the latter half.