JP3011625B2 - Image sensor with amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor with an amplifier for reading an original document, in which an amplifier is built in the same chip.

[0002]

2. Description of the Related Art In order to increase the S / N ratio of a sensor module, simplify peripheral circuits, and reduce the influence of external noise, various attempts have been made to integrate a sensor and an amplifier as signal sources on the same Si chip. Made in the sensor. For example, a CCD image sensor has a built-in FDA amplifier to realize high gain and low noise. Bi
-The BASIS image sensor manufactured by the CMOS process incorporates an operational amplifier using a bipolar transistor that can be manufactured by the same process and achieves high gain and simplification of peripheral circuits (Television Society of Japan, Vol. 47, PP
1177). Further, an image sensor that is less expensive than a CCD image sensor or a BASIS image sensor has been developed and put into practical use by a standard CMOS process whose process is simple. Using a phototransistor as a pixel,
There is a MOS image sensor that outputs an image signal to a common signal line from an emitter electrode of a phototransistor via an access MOS-FET in accordance with a scanning pulse from a scanning circuit. There is also an amplifying MOS image sensor in which a pixel is configured by a photodiode and an amplifying MOS-FET, and operates by receiving a signal voltage from the photodiode at a gate of the amplifying MOS-FET. However,
No amplifier is built in these MOS image sensors yet.

Generally, an amplifier section is often formed by a bipolar process because a high-speed differential amplifier circuit can be easily formed. In order to integrate the sensor and the amplifier into one chip, it is necessary to create the sensor unit and the amplifier unit that generate signals by the same IC process.
Therefore, the amplifier incorporated in the MOS image sensor must be configured with a MOS-FET. Further, in the amplification type MOS image sensor, since the output terminals of a large number of pixels are connected to the common signal line via the access MOS-FET, the capacitance of the common signal line becomes considerably large. When the input capacitance is large, it can be easily inferred that a grounded-gate amplifier is appropriate as an amplifier for amplifying a signal at high speed.

[0004] MOS when a grounded gate amplifier is connected
FIG. 6 shows an example of the image sensor. The image sensor unit 1 includes a pixel 6 including a photodiode 2, an amplification MOS-FET 3, an access MOS-FET 4, and a reset MOS-FET 5 for the photodiode 2, a NAND gate 7, a common signal line 8, and a reset power supply 9. And a scanning circuit 10. The NAND gate 7 has a reset MOS-FET at an intermediate timing of the scanning pulse.
Generate a reset pulse to turn 5 on. As a result, a bright signal is output in the first half of the scan pulse, and a dark signal is output in the second half of the scan pulse. The amplifier section 40 includes a drive MOS-FET 21 and a load MOS-FET 22
, A source resistor 25, and a gate bias power supply 35.

[0005] The power supply voltage is set to 5 V, and the amplification MOS-FE
Ratio of gate width W and gate length L of T3 W / L = 150 μm
/ 3 μm, W / L of access MOS-FET4 = 10
FIG. 7 shows the relationship between the input signal voltage Vs and the output voltage Vout using the voltage value Vg of the gate bias voltage source 35 as a parameter, where 0 μm / 3 μm. That is, FIG. 7 shows that the input signal Vs is input to the gate of the amplification MOS-FET 3.
Output voltage of the common-gate amplifier section 40 with respect to Vs
The pressure Vout is plotted. Curves ao and bo are Vo to Vs when Vg = 1.5V and 1.7V, respectively.
Indicates ut. a1 and a2 indicate Vout characteristics with respect to Vs when Vg = 1.5 V and the gate length fluctuates by ± 10% due to process fluctuation. b1 and b2
Shows Vout characteristics with respect to Vs when Vg = 1.7 V is set and the gate length fluctuates by ± 10%.

In FIG. 7, when Vg = 1.5 V, the active operating range is 2.3 V to 3.1 V, and when Vg = 1.7 V, the active operating range is 2.8 V to 3.6 V. It has become
In other voltage regions, the gain is significantly reduced. V
The upper limit (approximately 4.2 V) of the amplitude of out on the high voltage side is a state in which Vs is too high and the drive MOS-FET 21 is close to OFF, and Vout is determined only by the load MOS-FET 22. As for the lower limit of the amplitude on the low voltage side (about 0.25 V), Vs becomes too low and the drive M
The signal current to the source of the OS-FET 21 is extremely reduced, and as a result, the drain current becomes too large and the drain is stuck at a low voltage.

As described above, the conventional amplifier is active.
Operating range is narrow, and the voltage axis depends on the bias voltage Vg.
Along with each other and compose each pixel
There is a large shift due to changes in the characteristics of the MOS-FET.
You. Increasing bias in amplifier section
The allowable range of the voltage Vg becomes narrow. This amplifier section is stable
Vg must be set accurately to operate
PixelToMOS-FET3 for access, MO for access
It is necessary to minimize the variation of S-FET4To
However, it is very difficult in practice. Therefore, a stable amplifier section
It is difficult to integrate them on the same chip,
The peripheral circuit becomes complicated in the di-sensor,
Amplifying the sensor signal.

[0008]

As described above, the conventional gate-grounded amplifier comprising a MOS-FET has a narrow active operating range, and its input / output characteristics are as follows.
It greatly varies depending on the gate bias voltage Vg applied to the gate of ET. Also, the MOS-F constituting each pixel
The input / output characteristics fluctuate according to the ET characteristic variations. Therefore, it is difficult to set an optimal gate bias voltage for all pixels. Generally, compared to a bipolar transistor, a MOS-FET has a greater variation in its threshold voltage Vt, transconductance gm, and the like.
Therefore, it has been difficult to create a high-sensitivity image sensor with an amplifier that operates in a wide dynamic range using the conventional circuit.

An object of the present invention is to provide an image sensor with an amplifier having a high gain and a wide dynamic range.

[0010]

In order to solve the above-mentioned problems, an image sensor with an amplifier according to the present invention comprises a pixel, a photodiode, an amplifying MOS- FET, and an access MO.
An S-FET and a reset MOS-FET,
The photodiode through a reset MOS-FET
Of the individual electrodes to the reset power supply at regular intervals
Switch and scan pulse via access MOS-FET
Image signals proportional to the bright and dark signals
An image sensor that outputs from the communication line
Of the driving MOS-FET and the driving MOS-FET.
A load MOS-FET connected to the drain,
Gate voltage connected to the gate of the MOS-FET
Capacitor, gate of the drive MOS-FET
MOS-FE for amplifier set connected between the gate and drain
T, connected to the source of the drive MOS-FET
Source resistance and drain of the drive MOS-FET
Self-biased gate consisting of a clamp circuit connected to
A common amplifier line, and the common signal line
Connected to the source of the live MOS-FET,
A signal is output from an output terminal of the loop circuit.
You.

Furthermore, a source follower circuit is connected to the drain of the drive MOS-FET, and an amplifier set MOS-FET is connected between the output terminal of the source follower circuit and the gate of the drive MOS-FET, and the dynamics of the amplifier section are changed. It is configured to expand the range.

[0012]

With the above arrangement, in the self-biased gate grounded amplifier section, the amplifier setting M is set at the output timing of the bright signal output from the image sensor section in the first half of the scanning signal.
By turning on the OS-FET, an optimum gate voltage according to the image signal level can be applied to the gate voltage holding capacitor. In other words, the optimum gate voltage is automatically and sequentially applied to the gate of the driving MOS-FET even with respect to the variation in the characteristics of the elements. The difference between the bright signal and the dark signal is a substantial image signal. Subsequently, at the timing of the dark signal output from the image sensor unit in the latter half of the scanning signal, the amplifier setting MOS-FE
By turning off T, an output voltage based on the previously set optimal gate voltage is obtained from the drain of the driving MOS-FET. When an amplifier-setting MOS-FET is provided between the drain and the gate of the driving MOS-FET, the active operating range of the amplifier output voltage is from Vg to Vg.
−Vt. When an amplifier setting MOS-FET is provided via a source follower circuit, and the voltage shift of the source follower circuit is Vgs, the active operation range is Vg +
Vgs to Vg-Vt. With this, MOS-FE
A stable gate grounded amplifier is created at T, and the amplifier can be built into a MOS image sensor having a large signal line capacitance. This amplifier is most suitable for a MOS image sensor in which a bright signal current and a dark signal current are alternately output in pixel order, and can satisfy both conditions of increasing the gain of the amplifier and expanding the dynamic range.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an equivalent circuit of an image sensor with an amplifier according to the first embodiment of the present invention. 1, the image sensor with an amplifier is divided into an image sensor unit 1 and an amplifier unit 20. The image sensor unit 1 includes an amplifying MOS-F that operates by receiving a voltage of a photodiode 2 and an individual electrode (anode) of the photodiode 2 at a gate.
ET3, access MOS-FET4, reset MO for returning the voltage of the anode of the photodiode 2 to the initial state
A pixel 6 including an S-FET 5 and the like, and a NAND gate 7
, A common signal line 8, a reset power supply 9, and a scanning shift register 10. In this embodiment, the amplification MOS-FET 3 and the access MOS-FET 4
Is an n-channel type FET, and a reset MOS-FE
T5 is also an n- channel FET. Terminals 11, 1
Reference numeral 2 denotes a start pulse and a clock pulse input terminals for operating the scanning shift register 10, and 1
3 is an output terminal of the transmission pulses between chips for creating a long sensor in a multi-chip configuration, this pin next stage chip
It is possible to obtain a serial signal between chips by connecting to the start terminal 11.

The amplifier section 20 is a driving MOS-FET.
21, a load MOS-FET 22, an amplifier set MOS-FET 23, and a gate voltage holding capacitor 2
4, a source resistor 25 and a capacitor 26 forming a clamp circuit, and a MOS-FET 2 for a clamp switch.
7 and a buffer circuit 28. The source of the driving MOS-FET 21 is a source resistor 25, and the gate of the driving MOS-FET 21 is a gate voltage holding capacitor 24 and an amplifier setting MOS-FET 23.
Is formed on the drain of the driving MOS-FET 21, the source of the load MOS-FET 22 and the other electrode of the amplifier setting MOS-FET 23, and further , a clamp circuit is formed on the drain terminal 29 of the driving MOS-FET 21. A clamp switch MOS-FET 27 is connected via a capacitor 26, and a buffer circuit 28 is connected to an output terminal of the clamp circuit.

The image sensor unit 1 and the amplifier unit 20 are formed on the same chip by a CMOS process. A constant current source may be used instead of the source resistor 25. In this embodiment, a MOS-FET having a high input impedance
Taking advantage of the above feature, the capacitor is used as a bias power supply that can sequentially set a capacitor to a desired voltage value. The capacitance value of the gate voltage holding capacitor 24 is 0.5 to 10 pF.
Is formed by MOS junction. The source resistor 25 is formed of a diffusion resistor or a polycrystalline Si film, and has a thickness of several hundred to several kohms. 14 is a positive power supply terminal, 15 is a reset pulse input terminal, 30 is an output terminal, and 31 is an amplifier set pulse (A
S) is an input terminal. The common signal line 8 of the image sensor unit 1 is connected to the driving MOS-FET 2 of the amplifier unit 20.
An image signal is input by connecting to one source. Basically, the drive MOS-FET 21 constitutes a constant current circuit together with the gate voltage holding capacitor 24 and the source resistor 25, and when a signal current is input to the source, M
The drain current of the OS-FET 21 decreases, and as a result, the voltage drop of the load MOS-FET 22 decreases and the output voltage increases.

FIG. 2 shows the operation timing of the image sensor with an amplifier of this embodiment. CK and ST are a clock pulse and a start pulse of the scanning shift register 10 constituting the scanning circuit, respectively. SH1, SH2 to SHn
Is a scanning pulse output from the scanning shift register 10. RS is a reset pulse input to the terminal 15. The anode voltage Vp1 indicates the voltage of the anode terminal of the photodiode 2 of the first pixel. Is the signal current appearing on the common signal line 8, AS may amplifiers to be applied to the terminal 31
Se Ttoparusu, Vo1 signal voltage output to the drain terminal 29 of the driver MOS-FET 21, Vo2 is the output signal voltage output clamping circuit from the output terminal 30 via a buffer circuit. In each pixel, the scanning pulse SH
1, M reset at an intermediate point of the access timing by NAND output SH2~SHn and cell Ttoparusu AS
The OS-FET 5 is turned on, and the anode of the photodiode 2 is reset to the voltage of the reset power supply 9. Since the charge stored at the time of reset is discharged by photocurrent,
Vp1 increases in proportion to the amount of light. Therefore, in each pixel, the amplification MOS-FET 3 and the access MOS-F
The signal current Is corresponding to the voltage of the anode terminal of the photodiode 2 is sequentially output to the common signal line 8 via the ET 4 according to the scanning pulse from the scanning shift register 10 as a scanning circuit. In the signal current Is from each pixel, a bright signal current Ip is output to the common signal line 8 immediately before reset, and a dark signal current Id is output immediately after reset.

The amplifier section 20 operates by receiving the signal current Is from the common signal line 8 at the source of the driving MOS-FET 21. Timing pulses such as the reset pulse RS and the amplifier set pulse AS in FIG. 2 can be generated inside the chip using the delay function of the gate circuit. The signal current Is appearing on the common signal line 8
Consists of an alternating signal of the bright signal current Ip and the dark signal current Id.
In the image sensor of FIG. 1, since the anode potential of the photodiode 2 increases in proportion to the exposure amount, Ip> Id. By turning on the amplifier-setting MOS-FET 23 at the timing of the bright signal current Ip using the amplifier set pulse AS, the gate of the drive MOS-FET 21 is self-biased to the drain voltage at the time of the bright signal current, and thereafter, the gate voltage It is held by the holding capacitor 24. Here, the amplifier set pulse AS is "
L "turns on the amplifier-setting MOS-FET 23. The amplifier-setting MOS-FET 23 is turned off at the input timing of the dark signal current Id using the amplifier set pulse AS, so that it is based on the gate potential held in the capacitor 24. An output voltage, that is, an amplified voltage signal Vo1 proportional to Id-Ip for each pixel can be obtained at the terminal 29. The signal Vo1 output from the terminal 29 is obtained by using the amplifier set pulse AS to determine the timing of the bright signal current Ip. By turning on the clamping MOS-FET 27 with
An output signal Vo2 having a determined DC voltage level is obtained and output via the buffer circuit 28.

FIG. 3 shows a MOS-FET 23 for an amplifier set.
Is turned on, that is, the output voltage Vo1 and the gate bias voltage Vg of the amplifier at the time of setting the bias voltage are
This is plotted as a function of the signal voltage Vs input to the gate of OS-FET3. The output voltage Vo1 and the bias voltage Vg appearing at the drain terminal 29 of the driving MOS-FET 21 over a wide voltage range of Vs.
Is between the upper and lower amplitude limits shown in FIG.
It is in the active operating area where linearity is guaranteed. When the amplifier set MOS-FET 23 is ON, the change in Vo1 with respect to Vs is small because the drive MOS-FET 23
This is due to the fact that negative feedback is applied from the drain to the gate of the FET 21, which is convenient for setting the bias. A reference output signal Vo1 equal to the bias voltage Vg is output from the terminal 29 at the timing of the bright signal current Ip, and an amplified output voltage Vo1 proportional to Id-Ip is output at the timing of the dark signal current Id. Dark signal current Id
At the timing of (1), the amplifier-setting MOS-FET 23 is OFF, so that the negative gain is not applied from the drain to the gate of the driving MOS-FET 21, so that the gain becomes high. Since Ip> Id, the output signal Vo2 is output in the negative direction. In order for this amplifier to exhibit linear characteristics, the drive MOS-FET 21 needs to be in a saturated operation state. From this condition, the dynamic range of the output signal Vo2 is about Vg to Vg-Vt. Thus, Vt is the threshold voltage of the driving MOS-FET 21.

FIG. 4 is an equivalent circuit of an image sensor with an amplifier according to the second embodiment of the present invention. 4, the image sensor unit 1 is the same as that of the first embodiment (FIG. 1). The amplifier section 20 includes a driving MOS-FET 21,
Load MOS-FET 22 and amplifier set MOS-
The FET 23 includes an FET 23, a gate voltage holding capacitor 24, a source resistor 25, and a source follower circuit 32. The amplifier-setting MOS-FET 23 includes a gate of the drive MOS-FET 21 and a source follower circuit 32.
And is controlled by an amplifier set pulse AS input from a terminal 31. The source follower circuit 32 is composed of a follower MOS-FET 33 and a current load MOS-FET 34.
The gate of the S-FET 33 is an input terminal of the source follower circuit 32 and is connected to the drain terminal 29 of the drive MOS-FET 21.
Is the output terminal of the source follower circuit 32,
It is connected to one electrode of the amplifier set MOS-FET 23. A capacitor 2 forming a clamp circuit at the drain terminal 29 of the driving MOS-FET 21
6, the buffer circuit is connected to the clamp switch MOS-FET 27 and the output terminal of the clamp circuit.

The amplifier set MOS-FET 23 is used at the timing of the bright signal current Ip using the amplifier set pulse AS.
Is turned on, the driving MOS-FET 2
One gate is self-biased from the drain voltage at the time of the bright signal by a voltage shift by the source follower circuit 32, that is, a voltage lower by Vgs, and thereafter the gate voltage is held by the gate voltage holding capacitor. Therefore,
Vgs is a gate-source voltage of the follower MOS-FET 33. MOS-FE for amplifier setting at input timing of dark signal current Id using amplifier set pulse AS
By turning off T23, an output voltage based on the gate voltage held by the capacitor 24 can be obtained at the terminal 29.

FIG. 5 shows a MOS-FET 23 for an amplifier set.
Is a plot of the amplifier output voltage Vo1 and the bias voltage Vg as a function of the signal voltage Vs when the power supply is turned on. Over a wide voltage range of Vs, the output voltage Vo1 has a high-voltage side saturation value and a low-voltage saturation value. It is in the area where linearity is guaranteed. As described above, when the amplifier-setting MOS-FET 23 is ON, the change of Vo1 with respect to Vs becomes small because negative feedback is applied from the drain of the driving MOS-FET 21 to the gate via the source follower circuit 32. This is convenient for setting the bias. A reference output signal higher than the bias voltage Vg by Vgs is output from the output terminal 29 at the timing of the bright signal current Ip, and an amplified output signal proportional to Id-Ip is output at the timing of the dark signal current Id. At the timing of the dark signal current Id, the amplifier-setting MOS-FET 23 is OFF, so that no negative feedback is applied to the driving MOS-FET 21, so that the gain is high. Since Id <Ip, the output signal Vo2 is output in the negative direction with reference to Vg + Vgs. In this embodiment, the drain voltage Vo1 of the driving MOS-FET 21 is
Is higher than the gate voltage Vg of the MOS-FET for follower.
Since the Vgs is set higher by 33 Vgs, the dynamic range is approximately Vg + Vgs to Vg-Vt, and the dynamic range is wider than that of the circuit of FIG.

[0022]

As described above, according to the present invention, a self-biased gate grounded amplifier is built in an image sensor that outputs a bright signal and a dark signal alternately for each pixel.
The optimum bias voltage can be set for each pixel, and an image sensor with an amplifier having a high gain and a wide dynamic range can be realized. The industrial effect is extremely large as a high-performance, low-cost image reading element. .

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of an image sensor with an amplifier according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of the image sensor with an amplifier according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram illustrating an output voltage Vo1 and a gate bias voltage Vg of an amplifier with respect to an input signal voltage when a bias voltage is set in the first embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of an image sensor with an amplifier according to a second embodiment of the present invention.

FIG. 5 is a characteristic diagram illustrating an output voltage Vo1 and a gate bias voltage Vg of an amplifier with respect to an input signal voltage when a bias voltage is set according to the second embodiment of the present invention.

FIG. 6 is a diagram illustrating a conventional M-type amplifier connected to a grounded gate amplifier.
It is an equivalent circuit of an OS image sensor.

FIG. 7 is a characteristic diagram showing an output voltage with respect to an input signal voltage using a bias voltage as a parameter in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image sensor part 2 Photodiode 3 Amplification MOS-FET 4 Accessing MOS-FET 5 Reset MOS-FET 6 Pixel 7 NAND gate 8 Common signal line 9 Reset power supply 10 Scanning shift register 20 Amplifier part 21 Drive MOS- FET 22 Load MOS-FET 23 Amplifier setting MOS-FET 24 Gate voltage holding capacitor 25 Source resistance 26 Capacitor forming a clamp circuit 27 Clamp switch MOS-FET 28 Buffer circuit 30 Output terminal 31 Amplifier set pulse input terminal 32 Source follower circuit 33 MOS-FET for follower 34 MOS-FET for current load

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/028

Claims (4)

(57) [Claims] 1. A pixel comprising a photodiode and an amplifying MOS
A field effect transistor (MOS-FET), an access MOS-FET, and a reset MOS-FET,
To switch the individual electrodes in the reset power supply at intervals of a predetermined accumulation time of the photodiode through a MOS-FET for the reset sequentially according scan pulse through the MOS-FET for the access, an image signal proportional to the bright signal and the dark signal Sensor unit for outputting the same from a common signal line , a driving MOS-FET, and the driving MOS-FE
T load MOS-FET connected to the drain of the de <br/> gate voltage holding capacitor connected to the gate of the live for MOS-FET, an amplifier set connected between the gate and the drain of the drive for the MOS-FET MOS-F for
ET, is connected to the source of the drive for the MOS-FET
And a self-bias the gate-grounded amplifier unit consisting of the clamping circuit is connected to the drain of the MOS-FET for the source resistance and the drive, the said common signal line
Connected to the source of the drive MOS-FET,
An image sensor with an amplifier, wherein a signal is output from an output terminal of the amplifier circuit . 2. The gate voltage of the drive MOS-FET is self-biased to the drain voltage by turning on the amplifier-set MOS-FET at the timing of a bright signal output in the first half of the scan pulse. MOS for amplifier setting at the timing of dark signal output to
By OFF of -FET, bright signal and the dark signal amplifier with an image sensor of claim 1, wherein the benzalkonium are sequentially outputs the amplified signal from the output terminal proportional to the difference signal. 3. A pixel comprising a photodiode and an amplifying MOS.
-FET, access MOS-FET, reset MO
Constituted by S-FET, and switch the individual electrodes in the reset power supply at intervals of a predetermined accumulation time of the photodiode through a MOS-FET for the reset, MOS for access
Sequentially according to the scan pulse through -FET, and an image sensor unit which outputs an image signal proportional to the light signal and the dark signal from the common signal line, drive for MOS-FET, the de
Load M connected to drain of live MOS-FET
OS-FET, the gate voltage holding capacitor connected to the gate of the drive for the MOS-FET, a source follower circuit connected to the drain of the drive for the MOS-FET, said dry <br/> an output terminal of the source follower circuit Bed for MOS-FET amplifier set for MOS-FET connected between the gate of source of the drive for the MOS-FET
MOS for the source resistance and the drive was connected to the over scan
And a self-bias the gate-grounded amplifier unit consisting of the clamping circuit connected to the drain of -FET, the common signal
Connect the line to the source of the drive MOS-FET
And outputting a signal from an output terminal of the clamp circuit . 4. The gate voltage of the drive MOS-FET is self-biased to the output voltage of the source follower circuit by turning on the amplifier-set MOS-FET at the timing of a bright signal output in the first half of the scan pulse, By turning off the amplifier setting MOS-FET at the timing of the dark signal output in the latter half of the scanning pulse,
Bright signal and the amplifier with the image sensor according to claim 3, wherein the benzalkonium are sequentially outputted from the amplified signal an output terminal proportional to the difference signal of the dark signal.