JPH08125807A - Image sensor with amplifier - Google Patents

Abstract

PURPOSE: To realize a MOS image sensor in which a self-bias type common gate amplifier is built in. CONSTITUTION: The image sensor is made up of an amplification type MOS image sensor section 1 and a self-bias common gate amplifier section 20, and the amplifier section 20 is made up of a driving MOS-FET 21, a load MOSFET 22, an amplifier setting MOS-FET 23 connected between a drain and a gate of the driving MOS-FET 21, a gate voltage holding capacitor 24 and a source resistor 25. A common signal line 8 from the image sensor section 1 is connected to a source of the driving MOS-FET 21 to make the amplifier setting MOS-FET 23 conductive in a timing of a bright signal to set a gate potential to an optimum value automatically and to make the amplifier setting MOS-FET 23 nonconductive in a timing of a dark signal to extend a dynamic range at a high gain.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor with an amplifier for reading originals, which amplifier is built in the same chip.

[0002]

2. Description of the Related Art Various attempts have been made to integrate a sensor as a signal source and an amplifier on the same Si chip in order to improve the S / N ratio of a sensor module, simplify the peripheral circuit, and reduce the influence of external noise. Done in the sensor. For example, a CCD image sensor has a built-in FDA amplifier to realize high gain and low noise. Bi
・ The BASIS image sensor manufactured by the CMOS process has a built-in bipolar transistor operational amplifier that can be manufactured by the same process, and achieves high gain and simplification of peripheral circuits (Journal of the Television Society, Vol.47, PP).
1177). Further, a standard CMOS process, which is simple in process, has developed and put into practical use an image sensor which is lower in price than CCD image sensors and BASIS image sensors. Phototransistors are used as pixels,
There is a MOS image sensor that outputs an image signal from an emitter electrode of a phototransistor to a common signal line via an access MOS-FET according to a scanning pulse from a scanning circuit. There is also an amplification type MOS image sensor in which a pixel is composed of a photodiode and an amplification MOS-FET, and a signal voltage from the photodiode is received by the gate of the amplification MOS-FET to operate. However,
No amplifier is built in these MOS image sensors yet.

Generally, the amplifier section is often manufactured by a bipolar process because a high-speed differential amplifier circuit can be easily constructed. In order to integrate the sensor and the amplifier into one chip, it is necessary to form the sensor unit for generating a signal and the amplifier unit in the same IC process.
Therefore, the amplifier built in the MOS image sensor must be composed of MOS-FETs. Further, in the amplification type MOS image sensor, since the output terminals of many pixels are connected to the common signal line via the access MOS-FET, the capacitance of the common signal line becomes considerably large. When the input capacitance is large, it can be easily inferred that a grounded gate amplifier is suitable as an amplifier for amplifying a signal at high speed.

MOS when a grounded gate amplifier is connected
An example of the image sensor is shown in FIG. The image sensor unit 1 includes a pixel 2, a NAND gate 7, a common signal line 8, and a reset power supply 9 which are composed of a photodiode 2, an amplification MOS-FET 3, an access MOS-FET 4, and a reset MOS-FET 5 of the photodiode 2. And a scanning circuit 10. The NAND gate 7 is a reset MOS-FET at the intermediate timing of the scanning pulse.
A reset pulse for turning ON 5 is generated. As a result, a bright signal is output in the first half of the scan pulse, and a dark signal is output in the second half of the scan pulse. The amplifier section 40 includes a drive MOS-FET 21 and a load MOS-FET 22.
, A source resistance 25, and a gate bias power supply 35.

Amplification MOS-FE with a power supply voltage of 5V
Ratio of gate width W and gate length L of T3 L / W = 150 μm
/ 3 μm, W / L of access MOS-FET 4 = 10
FIG. 7 shows the relationship between the output voltage Vout and the input signal voltage Vs with the voltage value Vg of the gate bias voltage source 35 as a parameter when 0 μm / 3 μm. That is, in FIG. 7, the input signal Vs is input to the gate of the amplifying MOS-FET 3 and the output voltage of the grounded ground amplifier section 40 is plotted. Curves ao and bo are Vg = 1.5V,
Vout with respect to Vs in the case of 1.7V is shown. a1 and a2 are set to Vg = 1.5V, and show Vout characteristics with respect to Vs when the gate length fluctuates by plus or minus 10% due to process fluctuation. b1 and b2 are set to Vg = 1.7V, and show Vout characteristics with respect to Vs when the gate length fluctuates within plus or minus 10%.

In FIG. 7, when Vg = 1.5V, the active operating range is 2.3V to 3.1V, and when Vg = 1.7V, the active operating range is 2.8V to 3.6V. Has become
The gain is significantly reduced in other voltage regions. V
The upper limit of the amplitude on the high voltage side of out (about 4.2 V) is such that Vs becomes too high and the drive MOS-FET 21 becomes close to OFF, and Vout is determined only by the load MOS-FET 22. At the lower limit of the amplitude on the low voltage side (about 0.25V), Vs becomes too low, and the drive M
The signal current to the source of the OS-FET 21 is extremely reduced, and as a result, the drain current becomes too large and the drain sticks to a low voltage.

As described above, the amplifier in the conventional example has a narrow active operation range, and is greatly shifted along the voltage axis by the bias voltage Vg, and is largely shifted by the characteristic change of the MOS-FET forming each pixel. There is. As the gain of the amplifier section increases, the allowable range of the bias voltage Vg becomes narrower. In order to operate this amplifier part stably, Vg must be set accurately and
Amplifying MOS-FET3 in pixel, MO for access
It is necessary to minimize the variation of S-FET4,
Very difficult in practice. Therefore, it is difficult to embed a stable amplifier unit in the same chip, and the peripheral circuit is complicated in the MOS image sensor, but the sensor signal is amplified by the external amplifier.

[0008]

As described above, the conventional gate-grounded amplifier section composed of the MOS-FET has a narrow active operation range, and its input / output characteristics are the drive MOS-F.
It greatly varies depending on the gate bias voltage Vg applied to the gate of ET. In addition, the MOS-F that constitutes each pixel
The input / output characteristics fluctuate according to the ET characteristic variations. Therefore, it is difficult to set the optimum gate bias voltage over all pixels. Generally, in a MOS-FET, variations in threshold voltage Vt, mutual conductance gm, etc. are larger than in a bipolar transistor.
Therefore, it is difficult to make a high-sensitivity image sensor with an amplifier that operates in a wide dynamic range using the conventional circuit.

An object of the present invention is to provide an image sensor with an amplifier having a high gain and a wide dynamic range.

[0010]

In order to solve the above problems, in an image sensor with an amplifier of the present invention, a pixel is a photodiode, an amplification MOS-FET, and an access MO.
It is composed of S-FET and reset MOS-FET, and the individual electrode of the photodiode is switched to the reset power supply through the reset MOS-FET at a constant accumulation time interval, and sequentially according to the scan pulse through the access MOS-FET. , An image sensor unit in which an image signal proportional to a bright signal and a dark signal is output from a common signal line, a drive MOS-FET, a load MOS-FET, and a drive M.
Gate voltage holding capacitor connected to the gate of OS-FET, amplifier MOS-FET connected between the gate and drain of drive MOS-FET, source resistance of drive MOS-FET and drive MOS
-It consists of a self-biased gate grounded amplifier unit consisting of a clamp circuit connected to the drain of the FET. By connecting the common signal line to the source of the drive MOS-FET, the image signal is input to the amplifier unit and clamped from the drain terminal. The image signal is output through a circuit and a buffer circuit.

Further, a source follower circuit is connected to the drain of the drive MOS-FET, an amplifier set MOS-FET is connected between the output terminal of the source follower circuit and the gate of the drive MOS-FET, and the dynamic part of the amplifier section is connected. It is configured to expand the range.

[0012]

With the above structure, in the self-biased gate grounding amplifier section, the amplifier set M is set at the output timing of the bright signal output from the image sensor section in the first half of the scanning signal.
By turning on the OS-FET, an optimum gate voltage according to the image signal level can be applied to the gate voltage holding capacitor. That is, the optimum gate voltage is sequentially and automatically applied to the gate of the drive MOS-FET even with respect to variations in device characteristics. Subsequently, in the latter half of the scanning signal, the amplifier set MOS is set at the timing of the dark signal output from the image sensor unit.
-By turning off the FET, the output voltage based on the optimum gate voltage set previously is output to the drive MOS-FE.
Obtained from the drain of T. MOS-FET for drive
MOS-FET for amplifier set between drain and gate of
, The active range of the amplifier output voltage is Vg
~ Vg-Vt. When a MOS-FET for amplifier set is attached through a source follower circuit, the active operating range is V when the voltage shift of the source follower circuit is Vgs.
Expand to g + Vgs to Vg-Vt. This allows MOS-F
A stable grounded gate amplifier is created by ET, and the amplifier can be built in a MOS image sensor having a large signal line capacitance. This amplifier is most suitable for a MOS image sensor in which a bright signal current and a dark signal current are alternately output in a pixel order, and it is possible to satisfy both conditions of increasing the gain of the amplifier and expanding the dynamic range.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings. 1 is an equivalent circuit of an image sensor with an amplifier according to a first embodiment of the present invention. In FIG. 1, the image sensor with an amplifier is divided into an image sensor section 1 and an amplifier section 20. The image sensor unit 1 is an amplification MOS-F that operates by receiving the voltage of the photodiode 2 and the individual electrode (anode) of the photodiode 2 at its gate.
ET3, access MOS-FET4, reset MO for returning the voltage of the anode of the photodiode 2 to the initial state
A pixel 6 including an S-FET 5 and a NAND gate 7
, A common signal line 8, a reset power supply 9, and a scanning shift register 10. In this embodiment, the amplification MOS-FET 3 and the access MOS-FET 4 are
Is an n-channel FET, and reset MOS-FE
T5 is a p-channel FET. Terminals 11, 1
Reference numeral 2 is an input terminal for a start pulse and a clock pulse for operating the scanning shift register 10, respectively.
Reference numeral 3 is an output terminal of a transmission pulse between chips when a long sensor is formed with a multi-chip configuration. By connecting this terminal to the start terminal 11 in the next stage, a serial signal can be obtained between the chips.

The amplifier section 20 is a drive MOS-FET.
21, a load MOS-FET 22, an amplifier set MOS-FET 23, and a gate voltage holding capacitor 2
4, a source resistor 25 and a capacitor 26 forming a clamp circuit, and a clamp switch MOS-FET 2
7 and a buffer circuit 28. The source of the drive MOS-FET 21 is a source resistor 25, and the gate of the drive MOS-FET 21 is a gate voltage holding capacitor 24 and an amplifier set MOS-FET 23.
One electrode is connected to the drain of the drive MOS-FET 21, the source of the load MOS-FET 22 and the other electrode of the amplifier set MOS-FET 23 are connected to the drive M.
The drain terminal 29 of the OS-FET 21 passes through a capacitor 26 that forms a clamp circuit, and then a clamp switch MO.
A buffer circuit 28 is connected to the S-FET 27 and the output terminal of the clamp circuit.

The image sensor section 1 and the amplifier section 20 are formed on the same chip by a CMOS process. A constant current source may be used instead of the source resistor 25. In this embodiment, the MOS-FET has a high input impedance.
Taking advantage of the above feature, the capacitor is used as a bias power source capable of sequentially setting a desired voltage value. The capacitance value of the gate voltage holding capacitor 24 is 0.5 to 10 pF.
It is formed by MOS junction. The source resistor 25 is formed of a diffusion resistor or a polycrystalline Si film, and has a thickness of several hundreds to several kohm. 14 is a positive power supply terminal, 15 is a reset pulse input terminal, 30 is an output terminal, and 31 is an amplifier set pulse (A
S) input terminal. The common signal line 8 of the image sensor unit 1 is connected to the drive MOS-FET 2 of the amplifier unit 20.
The image signal is input by connecting to the 1 source. Basically, the drive MOS-FET 21 constitutes a constant current circuit together with the gate voltage holding capacitor 24 and the source resistance 25, and when a signal current is input to the source, M
The drain current of the OS-FET 21 decreases, and as a result, the voltage drop of the load MOS-FET 22 decreases and the output voltage increases.

FIG. 2 shows the operation timing of the image sensor with an amplifier of this embodiment. CK and ST are a clock pulse and a start pulse of the scanning shift register 10 which constitutes a scanning circuit, respectively. SH1, SH2-SHn
Is a scan pulse output from the scan shift register 10. RS is a reset pulse input to the terminal 15. The anode voltage Vp1 indicates the voltage of the anode terminal of the photodiode 2 of the leading pixel. Is is a signal current appearing on the common signal line 8, AS is an amplifier reset pulse applied to the terminal 31, Vo1 is a signal voltage output to the drain terminal 29 of the driving MOS-FET 21, Vo2 is output via a clamp circuit and a buffer circuit. It is an output signal voltage output from the terminal 30. In each pixel, scan pulse S
NAND of H1, SH2-SHn and reset pulse AS
The output turns on the reset MOS-FET 5 at an intermediate point in the access timing, and the anode of the photodiode 2 is reset to the voltage of the reset power supply 9. Since the electric charge accumulated at the time of resetting is discharged by the photocurrent, Vp1 rises in proportion to the amount of light. Therefore, in each pixel, the amplification MOS-FET 3 and the access MOS
A signal current Is corresponding to the voltage of the anode terminal of the photodiode 2 is sequentially output to the common signal line 8 via the −FET 4 in accordance with the scanning pulse from the scanning shift register 10 which is a scanning circuit. In addition, in the signal current Is from each pixel, the bright signal current Ip is
Immediately after the reset, the dark signal current Id is output to the common signal line 8.

The amplifier section 20 operates by receiving the signal current Is from the common signal line 8 at the source of the drive MOS-FET 21. Timing pulses such as the reset pulse RS and the amplifier set pulse AS in FIG. 2 can be generated inside the chip by utilizing the delay function of the gate circuit. Signal current Is appearing on the common signal line 8
Is an alternating signal of a bright signal current Ip and a dark signal current Id.
In the image sensor of FIG. 1, since the anode potential of the photodiode 2 rises in proportion to the exposure amount, Ip> Id. By turning on the amplifier set MOS-FET 23 at the timing of the bright signal current Ip using the amplifier set pulse AS, the gate of the drive MOS-FET 21 is self-biased to the drain voltage at the time of the bright signal current, and thereafter, the gate voltage It is held by the holding capacitor 24. The amplifier set pulse AS is "
It is assumed that the amplifier-set MOS-FET 23 is turned on at L ". Based on the gate potential held in the capacitor 24, the amplifier-set pulse AS is used to turn off the amplifier-set MOS-FET 23 at the input timing of the dark signal current Id. The output voltage, that is, the amplified voltage signal Vo1 proportional to Id-Ip for each pixel can be obtained at the terminal 29. The signal Vo1 output from the terminal 29 is the timing of the bright signal current Ip using the amplifier set pulse AS. By turning on the clamp MOS-FET 27 at
An output signal Vo2 having a fixed DC voltage level is obtained and output via the buffer circuit 28.

FIG. 3 shows a MOS-FET 23 for amplifier set.
Is turned on, that is, the output voltage Vo1 and the gate bias voltage Vg of the amplifier when the bias voltage is set
It is plotted as a function of the signal voltage Vs input to the gate of OS-FET3. The output voltage Vo1 and the bias voltage Vg appearing at the drain terminal 29 of the driving MOS-FET 21 over a wide voltage range of Vs.
Is between the upper limit value and the lower limit value of the amplitude shown in FIG.
It is in the active operating area where linearity is guaranteed. When the amplifier-set MOS-FET 23 is ON, the change in Vo1 with respect to Vs becomes small because the drive MOS-
This is because negative feedback is applied from the drain to the gate of the FET 21, which is convenient for setting the bias. A reference output signal Vo1 equal to the bias voltage Vg is output from the terminal 29 at the timing of the bright signal current Ip, and an amplified output voltage Vo1 proportional to Id-Ip is output at the timing of the dark signal current Id. Dark signal current Id
At this timing, the amplifier-set MOS-FET 23 is off, so that no negative feedback is applied from the drain to the gate of the drive MOS-FET 21, resulting in a high gain. Since Ip> Id, the output signal Vo2 is output in the negative direction. In order for this amplifier to show linear characteristics, the drive MOS-FET 21 must be in a saturated operation state. Under this condition, the dynamic range of the output signal Vo2 is approximately Vg to Vg-Vt. Therefore, Vt is the threshold voltage of the drive MOS-FET 21.

FIG. 4 is an equivalent circuit of an image sensor with an amplifier according to the second embodiment of the present invention. In FIG. 4, the image sensor unit 1 is the same as that of the first embodiment (FIG. 1). The amplifier section 20 includes a drive MOS-FET 21 and
Load MOS-FET22 and amplifier set MOS-
The FET 23 includes a gate voltage holding capacitor 24, a source resistance 25, and a source follower circuit 32. The amplifier set MOS-FET 23 is a gate of the drive MOS-FET 21 and a source follower circuit 32.
Of the amplifier set pulse AS input from the terminal 31. The source follower circuit 32 is composed of a follower MOS-FET 33 and a current load MOS-FET 34.
The gate of the S-FET 33 is the input terminal of the source follower circuit 32, is connected to the drain terminal 29 of the drive MOS-FET 21, and is connected to the follower MOS-FET 33.
Is the output terminal of the source follower circuit 32,
It is connected to one electrode of the amplifier-set MOS-FET 23. Further, a capacitor 2 forming a clamp circuit at the drain terminal 29 of the drive MOS-FET 21.
A clamp switch MOS-FET 27 is connected via 6 and a buffer circuit is connected to the output terminal of the clamp circuit.

The amplifier set MOS-FET 23 is used at the timing of the bright signal current Ip using the amplifier set pulse AS.
By turning on, drive MOS-FET2
The gate of No. 1 is self-biased from the drain voltage at the time of the bright signal to a voltage shifted by the source follower circuit 32, that is, a voltage lower by Vgs, and thereafter, the gate voltage is held by the gate voltage holding capacitor 24. Therefore,
Vgs is the gate-source voltage of the follower MOS-FET 33. MOS-FE for amplifier set at the input timing of the dark signal current Id using the amplifier set pulse AS
By turning off T23, an output voltage based on the gate voltage held in the capacitor 24 can be obtained at the terminal 29.

FIG. 5 shows an amplifier set MOS-FET 23.
Is a plot of the amplifier output voltage Vo1 and the bias voltage Vg as a function of the signal voltage Vs when the switch is ON, and the output voltage Vo1 has a saturation value on the high voltage side and a saturation value on the low voltage side over a wide voltage range of Vs. It is in the area of guaranteed linearity. As described above, when the MOS-FET 23 for amplifier set is ON, the change of Vo1 with respect to Vs becomes small because the negative feedback is applied from the drain of the drive MOS-FET 21 to the gate through the source follower circuit 32. , It is convenient for setting the bias. A reference output signal that is higher than the bias voltage Vg by Vgs is output from the output terminal 29 at the timing of the bright signal current Ip, and an amplified output signal proportional to Id-Ip is output at the timing of the dark signal current Id. At the timing of the dark signal current Id, the amplifier-set MOS-FET 23 is OFF, so that the drive MOS-FET 21 does not receive negative feedback, and thus the gain is high. Since Id <Ip, the output signal Vo2 is output in the negative direction with reference to Vg + Vgs. In this embodiment, the drain voltage Vo1 of the drive MOS-FET 21 is
Is a follower MOS-FET than its gate voltage Vg
Since it is set higher by Vgs of 33, the dynamic range is approximately Vg + Vgs to Vg−Vt, which is wider than that of the circuit of FIG.

[0022]

As described above, according to the present invention, by incorporating a self-biased gate ground amplifier unit in an image sensor that alternately outputs a bright signal and a dark signal for each pixel,
The optimum bias voltage can be set for each pixel, an image sensor with a high gain and a wide dynamic range can be realized, and the industrial effect is extremely large as a high-performance, low-cost image reading device. .

[Brief description of drawings]

FIG. 1 is an equivalent circuit of an image sensor with an amplifier according to a first exemplary embodiment of the present invention.

FIG. 2 is an operation timing chart of the image sensor with an amplifier according to the first embodiment of the present invention.

FIG. 3 is a characteristic diagram showing an output voltage Vo1 and a gate bias voltage Vg of an amplifier with respect to an input signal voltage when a bias voltage is set in the first embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of an image sensor with an amplifier according to a second embodiment of the present invention.

FIG. 5 is a characteristic diagram showing the output voltage Vo1 and the gate bias voltage Vg of the amplifier with respect to the input signal voltage when the bias voltage is set in the second embodiment of the present invention.

FIG. 6 is an M when a gate grounded amplifier of a conventional example is connected.
It is an equivalent circuit of the OS image sensor.

FIG. 7 is a characteristic diagram showing an output voltage with respect to an input signal voltage with a bias voltage as a parameter in a conventional example.

[Explanation of symbols]

 1 Image Sensor Section 2 Photodiode 3 Amplification MOS-FET 4 Access MOS-FET 5 Reset MOS-FET 6 Pixel 7 NAND Gate 8 Common Signal Line 9 Reset Power Supply 10 Scan Shift Register 20 Amplifier Section 21 Drive MOS- FET 22 Load MOS-FET 23 Amplifier set MOS-FET 24 Gate voltage holding capacitor 25 Source resistance 26 Capacitor forming a clamp circuit 27 Clamp switch MOS-FET 28 Buffer circuit 30 Output terminal 31 Ampset pulse input terminal 32 source follower circuit 33 follower MOS-FET 34 current load MOS-FET

Claims (4)

[Claims] 1. A pixel is a photodiode and an amplification MOS.
Field effect transistor (MOS-FET), access MOS-FET, reset MOS-FET
The individual electrodes of the photodiode are switched to the reset power supply via the reset MOS-FET at a constant accumulation time interval, and the image signals proportional to the bright signal and the dark signal are sequentially shared according to the scanning pulse via the access MOS-FET. In an image sensor that outputs from a signal line, a drive MOS-FET, a load MOS-FET, a gate voltage holding capacitor connected to the gate of the drive MOS-FET, and a gate-drain of the drive MOS-FET. Amplifier set MOS-FET, drive MOS-FET source resistance and drive M
An image sensor with an amplifier, which has a built-in self-biased gate grounded amplifier unit consisting of a clamp circuit connected to the drain of an OS-FET. 2. The gate voltage of the drive MOS-FET is self-biased to the drain voltage by turning on the amplifier-set MOS-FET at the timing of the bright signal output in the first half of the scan pulse, and the latter half of the scan pulse. MOS for amplifier set at the timing of dark signal output to
2. An amplifier unit for sequentially outputting an amplified signal, which is proportional to a difference signal between a bright signal and a dark signal, from an output terminal by turning off the -FET.
Image sensor with amplifier. 3. A pixel is a photodiode and an amplification MOS.
-FET, access MOS-FET, reset MO
It is composed of S-FET, and the individual electrode of the photodiode is switched to the reset power source at a constant accumulation time interval via the reset MOS-FET to access the MOS-FET.
In an image sensor that sequentially outputs an image signal proportional to a bright signal and a dark signal from a common signal line in accordance with a scanning pulse via a drive MOS-FET and a load MO.
S-FET, drive MOS-FET gate voltage holding capacitor connected to the gate, drive MOS-
Source follower circuit connected to the drain of FET, output terminal of source follower circuit and drive MOS-FET
MOS-FET for amplifier set connected between the gates of
An image sensor with an amplifier, which has a built-in self-biased gate grounded amplifier unit consisting of a clamp circuit connected to the source resistance of the driving MOS-FET and the drain of the driving MOS-FET. 4. The gate voltage of the drive MOS-FET is self-biased to the output voltage of the source follower by turning on the amplifier-set MOS-FET at the timing of the bright signal output in the first half of the scan pulse, thereby performing scanning. Built-in amplifier unit that sequentially outputs amplified signals proportional to the difference signal between the bright signal and dark signal from the output terminal by turning off the amplifier-set MOS-FET at the timing of the dark signal output in the latter half of the pulse The image sensor with an amplifier according to claim 3, wherein