JP3038985B2 - Image sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor capable of reading document information at high speed and with high resolution.

[0002]

2. Description of the Related Art In recent years, with the development of image processing and image communication equipment, the need for high-performance and inexpensive image sensors has been increasing.

An image sensor uses a shift register or a charge transfer element as a scanning circuit and outputs a spatial light amount distribution as a time-series electric signal. For example, there are a CCD image sensor, a MOS image sensor, a bipolar image sensor, and the like. The MOS image sensor uses a photodiode as a light detecting element and a MOS shift register as a scanning circuit, and sequentially recharges a discharge charge caused by a photocurrent in the photodiode in accordance with a scanning signal from the shift register to form an image signal. It has gained. In this method, since the discharge charge in the photodiode is very small, the obtained image signal is small and S /
N is low.

In recent years, instead of directly taking out the discharge charge of the photodiode, a change in the terminal voltage of the photodiode due to incident light is added to the FE added to each photodiode.
2. Description of the Related Art An image sensor that obtains an image signal after amplification by a T (field effect transistor), that is, an amplification type MOS image sensor has been developed.

FIG. 3 shows the basic components of one pixel of the above-mentioned amplification type MOS image sensor. 1 is a photodiode, 2 is an amplifying MOS transistor that receives a potential change of the photodiode 1 as a gate potential and amplifies an optical signal, and 3 is a readout that sequentially reads out an amplified optical signal to an output line for each pixel. Switches 4 and 4 are reset switches for resetting the gate potential of the amplification MOS transistor 2 to a predetermined reference value after reading an optical signal for each pixel. As a form to be read out to the output signal line, it is read out as a source current or as a source follower output voltage of the amplifying MOS transistor 2. Although only one pixel has been described above, the image sensor is composed of a plurality of pixels, and each pixel may share a power supply line, a reset reference potential line, and an output signal line.

However, the amplification type MOS image sensor has fixed pattern noise because the output in the darkness always varies due to the manufacturing variation that is always present. Therefore, in order to remove the fixed pattern noise, an offset output value (corresponding to a dark output) unique to each pixel must be subtracted from the signal output value. FIG. 4 is a timing chart showing the state at this time. In FIG. 4, A (N) indicates an access pulse for driving the readout switch 3 of the Nth pixel, and R (N) indicates a reset pulse for driving the reset switch 4 of the Nth pixel. Hereinafter, A (N-1) and A (N + 1) are also access pulses, and R (N-1) and R (N + 1) are also reset pulses. As shown by the image signal Is in FIG. 4, a signal output and an offset output (dark equivalent output) appear in order. Between the signal output read timing of each pixel and the offset output timing, the reset switch 4 of FIG. 3 is turned on by the reset pulse shown in FIG. 4 to set the gate potential of the amplifying MOS transistor to a predetermined reference value. Resetting. R (N) is off
After that, the output value corresponding to the offset output is output as a value to be subtracted from the signal output. That is, the output after the subtraction is corrected so that the actual output at the time of darkness becomes zero.

In the output before the subtraction, when the reset switch 4 is in the ON state, an output having a size in which a feedthrough component due to a reset pulse is superimposed on the offset output value appears.

FIG. 5 shows a circuit for generating the reset pulse R (N). FIG. 5A is a timing chart of the image sensor. FIG. 5B shows pulses RP and A
FIG. 9 is a circuit diagram for generating a reset pulse R (N) from (N). FIG. 5C is a circuit diagram showing the circuit of FIG. 5B by logic elements.

As shown in FIG. 5, a reset pulse R
In order to generate (N), it is necessary to generate an external pulse RP and to configure many transistors for each pixel.

[0010]

SUMMARY OF THE INVENTION Reset MOSFE
A parasitic capacitance C exists between the gate terminal of T and the anode terminal of the photodiode. Therefore, when the reset signal changes from the high level to the low level, the anode potential of the photodiode becomes a potential slightly lower than the reset potential due to the variation in the potential of the capacitive coupling. Then, since this lowered potential becomes the anode potential at the time of darkness, the output signal at the time of reset becomes larger than the image signal at the time of darkness by an offset. Further, since the amplification factor gm and the threshold voltage VT of the amplification MOS transistor vary from element to element, the pixel signal in the darkness varies and fixed pattern noise occurs. To remove this, reset MOS
The signal is read twice before and after the FET performs the reset operation, and the difference between the two is obtained. However, many transistors as shown in FIG. 5 are required to generate a drive pulse required for such reading.

In view of the above, it is an object of the present invention to provide an image sensor capable of removing variations (fixed pattern noise) in a dark state with a simple driving pulse.

[0012]

In order to solve the above problems, an image sensor according to the present invention comprises a photodiode, an amplifying element for amplifying a signal from the photodiode,
A switch for reading an image signal for reading out a signal amplified by the amplifying element, a switch for resetting the output level of the photodiode to a predetermined level, and one of the drain and source terminals being open and the other being amplifying. A dummy reset switch connected to the gate terminal of the element, an odd image signal line that outputs an image signal of an odd pixel, an even image signal line that outputs an image signal of an even pixel, and a read switch; A half-bit shift register for generating a pulse for driving the reset switch and the dummy reset switch, wherein the dummy reset switch is driven by an inverted pulse of a pulse for driving the read switch;
The configuration is such that reading of an image signal from the Nth pixel and reading of a reset signal (offset signal) of the Nth pixel are performed simultaneously.

[0013]

According to the present invention, by providing the dummy reset circuit provided for each pixel with the above-described configuration, it is possible to cancel the feedthrough potential fluctuation of the gate terminal potential of the amplifying MOS transistor and the spike noise generated at the time of reset. In addition, it is possible to remove the influence of spike noise superimposed on the output signal and fluctuation of the feedthrough potential. As a result, the output of the reset switch in the ON state can be used as the offset signal, so that the parallel output signal of the half-bit shift register can be used as the reset pulse, and the image sensor can be driven with a simple pulse, and the integration degree can be increased. This realizes an image sensor with improved image quality.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a circuit diagram of an image sensor according to an embodiment of the present invention.
2a) to 2c) are amplification elements M which are amplification elements that amplify an optical signal by receiving a potential change of the photodiode 1 as a gate potential.
The OS transistor, 3 (3a to 3c), a read switch for sequentially reading out the amplified optical signal to the output line for each pixel, and 4 (4a to 4c), after reading the optical signal for each pixel, A reset switch for resetting the gate potential of the MOS transistor 2 to a predetermined reference value;
(5a-5c) are switches for dummy reset, and the above-mentioned 1-5 constitute a pixel for detecting an optical signal. The dummy reset switch 5 is formed such that the gate-drain capacitance is equal to the gate-drain capacitance of the reset switch 4 and is driven by an inversion pulse of the reset pulse, and is driven by the reset pulse. This offsets fluctuations in the feedthrough potential of the gate terminal potential of the amplifying MOS transistor and spike noise caused by the influence of the above. Since the inversion pulse is obtained from the terminals (B2 to B5) of the half-bit shift register 19, a circuit for generating the inversion pulse as shown in FIG. 5 is not required. The sources of the reset switches (4a to 4c) are commonly connected to a reset voltage supply terminal 15. Reference numeral 19 denotes a half-bit shift register composed of MOSFETs. Reference numerals 10, 11, and 12 denote a power supply terminal, a start signal input terminal, and a ground terminal, respectively. 1
Reference numerals 3 and 14 denote scanning shift clock input terminals.
Pulses having phases opposite to each other are input to 3 and 14, respectively. The carry pulse input terminal 16 is used when operating multiple chips in series, and the start signal input terminal 11 of the subsequent chip is used.
Connect to The source of the read-out FET of the odd-numbered pixel is commonly connected to the first odd-numbered image signal line 17, and the source of the read-out FET of the even-numbered pixel is commonly shared with the even image signal line 1.
8 is connected. 6a and 6b are buffers.

FIG. 7A is a plan view of a device structure of one pixel component, and FIG. 7B is a cross-sectional view taken along line XX ′ of FIG. 7A. As shown in FIGS. 7A and 7B, it is not necessary to form a source region on the side of the dummy reset switch 5 that is not connected to the photodiode.

Hereinafter, the operation of the image sensor according to the present embodiment will be described with reference to FIGS. At the time of resetting, the image sensor of this embodiment stores a constant charge by charging the photodiode to a constant voltage (Vdd-Vrs), and then detects a change in the terminal voltage of the photodiode due to the discharge of the charge due to the photocurrent. The amplified image output signal is obtained by receiving the signal at the gate of the amplification MOS transistor. Clock signals CK1, CK2, start signal S
1 together with the node A of the shift register 19 in FIG.
1, the pulses appearing on A2, A3 and B2, B3, and the image output signals Iso, Ise appearing on the odd image signal lines 17, 18. The pulses appearing in A1, A2, and A3 have an overlap by half a cycle in sequence and B
The pulses appearing at 2 and B3 are inverted pulses of the pulses appearing at A2 and A3, respectively. By driving the dummy reset switch with the above-described inversion pulse in conjunction with the reset switch, the feedthrough potential fluctuation component can be removed, so that the value when the reset switch is on can be used as the offset signal output.

In FIG. 1, the parallel output pulses at the nodes A1 to A5 of the half-bit shift register 19 are used as the reset pulse of the preceding stage pixel and the access pulse of the main stage pixel except for the head and tail. Therefore, as shown by Iso and Ise, the odd image signal line 17 and the even image signal line 1
In FIG. 8, an image output signal including an offset and an offset signal alternately appear every clock, and the odd image signal line 1
7 and the even image signal line 1
8 and the timing of the image signal appearing on the even image signal line 18 and the timing of the offset signal appearing on the odd image signal line 17 respectively match. In this embodiment, the output data rate of the image signal is comprehensive because the odd-numbered image signal line 17 that outputs the signal of the odd-numbered photodiode and the even-numbered image signal line 18 that outputs the signal of the even-numbered photodiode are provided. The number of stages of the half-bit shift register which is equal to the clock frequency and which is required is only one per pixel. Further, an inverted pulse of the reset pulse supplied to the gate of the dummy reset switch 5 provided to cancel the feedthrough potential fluctuation of the gate terminal potential of the amplifying MOS transistor and spike noise is easily taken out from the shift register. be able to.

FIG. 6 is an output circuit diagram applied to the image sensor according to the present embodiment. FIG. 6A shows a circuit for processing an image signal of an odd-numbered pixel, and FIG. 6B shows a circuit for processing an image signal of an even-numbered pixel. FIG. 6 (a)
Each circuit in (b) is the same, but the pulses applied to the control terminals of the analog switches 25a and 25b are respectively CK
1, CK2 is out of phase. 20a and 20b are odd-numbered image signal input terminals and even-numbered image signal input terminals, respectively, and 21a and 21b and 22a and 22b are feedback resistors and differential amplifiers, respectively. 23a,
23b and 26a, 26b are buffers, 24a,
24b is a sample and hold capacitor.

When an image signal is input to the image signal input terminal 20, it is converted into a voltage by the differential amplifier 24 and then charged as an output voltage on the input side of the sample-and-hold capacitor. Next, when an offset signal is input, the analog switch 25 is turned off, and the offset signal output voltage is output to the input side of the sample and hold capacitor, and a voltage obtained by subtracting the offset signal output voltage from the image signal output voltage is output to the output side. . The terminals 27a, 2
7b, it is possible to obtain an image signal from which the odd-numbered and even-numbered offset signals have been removed.

In order to operate the shift register as a static shift register, a plurality of circuits as shown in FIG. 8A may be connected and used as a scanning circuit. The timing chart of FIG. 8C is the same as the timing chart of the half-bit shift register of FIG. 2, and is driven by the scanning circuit of FIG. An image sensor that can eliminate the noise can be realized.

[0021]

According to the present invention, by applying a dummy reset switch, a feed-through potential fluctuation and spike noise of the gate terminal potential of the amplifying MOS transistor caused by the influence of the reset switch can be reduced by a simple driving pulse. Can be offset. Therefore, it is possible to obtain an offset signal output with the reset switch kept on, so that the fixed pattern noise of the amplification type MOS image sensor can be reduced by an extremely simple pulse.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an image sensor according to an embodiment of the present invention.

FIG. 2 is a timing chart of the image sensor circuit of the present invention.

FIG. 3 is a circuit diagram of a basic one pixel of a conventional image sensor.

FIG. 4 is a timing chart of a conventional image sensor circuit.
G

5A is a timing chart of a conventional image sensor circuit. FIG. 5B is a circuit diagram for generating a reset pulse in the conventional image sensor. FIG. 5C is a circuit diagram showing the circuit of FIG.

FIG. 6A is a circuit diagram of a circuit that outputs an image signal of each odd-numbered pixel in the present embodiment. FIG. 6B is a circuit diagram of a circuit that outputs an image signal of each even-numbered pixel in the present embodiment.

7A is a plan view of a device structure of a component of one pixel of the present embodiment. FIG. 7B is a cross-sectional view taken along line XX ′ of FIG. 7A.

8A is a circuit diagram of a half-bit shift register using a clocked inverter as feedback. FIG. 8B is a circuit diagram of the circuit of FIG. 8A represented by a logic element. FIG. 8C is a timing diagram of FIG. chart

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Photodiode 2a-2c MOS transistor 3a-3c Output readout switch 4a-4c Reset switch 5a-5c Dummy reset switch 17 Odd image signal line 18 Even image signal line 19 Half bit shift register

Continuation of front page (56) References JP-A-3-167955 (JP, A) JP-A-3-212057 (JP, A) JP-A-2-237264 (JP, A) JP-A-61-281668 (JP) , A) JP-A-59-6664 (JP, A) JP-A-57-50178 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1/028

Claims (3)

(57) [Claims] 1. A photodiode, an amplifying element for amplifying a signal from the photodiode, a switch for reading an image signal for reading out a signal amplified by the amplifying element, and an output level of the photodiode for a predetermined level And a dummy reset switch having one of the drain and source terminals open and the other connected to the gate terminal of the amplifying element. An image sensor driven by an inverted pulse of a pulse for driving a switch. 2. A half bit shift register for generating a pulse for driving a read switch, a reset switch, and a dummy reset switch.
An image sensor as described. 3. A half-bit shift register that commonly uses a pulse for driving a reset switch of an N-th pixel and a pulse for driving a read-out switch of an (N + 1) -th pixel, and an image signal of an odd-numbered pixel. An odd-numbered image signal line to be output, and an even-numbered image signal line to output an even-numbered pixel image signal are provided. The image signal is read from the (N + 1) -th pixel and the reset signal of the N-th pixel (offset signal). 3. The image sensor according to claim 2, wherein reading is performed simultaneously.