JPH03212057A - Image sensor - Google Patents

Abstract

PURPOSE:To eliminate fixed pattern noise and to read an original with high quality by outputting a picture signal including an offset for each picture element and an offset signal to a picture signal output line sequentially. CONSTITUTION:Half bit shift circuits 7-12 are connected sequentially and act like a shift register through the application of a clock pulse and parallel output signals Y1-Y6 of the shift register are shifted sequentially by a half bit each. Thus, a picture signal including an offset signal of each picture element and an offset fixed pattern noise signal appear sequentially on an output line. A difference signal is taken between the picture signal and the offset signal to obtain the picture signal whose fixed pattern noise is eliminated for each picture element. Thus, the fixed pattern noise is eliminated and the original read quality is improved.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to an image sensor that is capable of reading document information with high sensitivity, high speed, and high S/N. Image sensors formed on crystals include LCD image sensors, MOS image sensors, bipolar IC image sensors, etc. A CCD image sensor uses a photodiode as a light detection element and a CCD (charge-coupled device) as a scanning circuit. Then, the optical signal charge generated by the photodiode is accumulated for a certain period of time and transferred to the CCD, and the signal charge is transferred to the S! An image signal is obtained by amplifying it and converting it into a voltage using an amplifier built into the chip.4 A MOS image sensor has a configuration using a photodiode as a light detection element and a MOS shift register as a scanning circuit, and the photocurrent in the photodiode is Even if an image signal is obtained by sequentially recharging the discharged charge in accordance with the shift signal from the shift register, the discharged charge in the photodiode is minute in this method, and the obtained image signal is small and the S/N is low ( -Recently, instead of directly extracting the discharge charge of the photodiode, a method has been developed to obtain an image signal by amplifying the change in the terminal voltage of the photodiode due to incident light using an FET (field effect transistor) attached to each photodiode. Image sensor, i.e. amplified MO
A bipolar IC image sensor is a bipolar IC image sensor that uses a phototransistor as a light detection element and a bipolar IC shift register or decoder as a scanning circuit. This amplification type MOS image sensor obtains an image signal through the amplification function of a phototransistor by sequentially recharging the discharged charge due to a photocurrent according to the access from a scanning circuit. An amplification FET is attached to one end of each photodiode, and the offset signal (dark signal) varies due to non-uniformity of the threshold voltage vt and mutual conductance gm of the FET.

This is called fixed pattern noise (FPN).An increase in fixed pattern noise degrades the reading quality of the original.The purpose of the present invention is to solve this problem.a.Means for solving the problemEach pixel The photodiode K consists of an amplification FET, an access FET, and a reset FET. One end of the photodiode is connected to the gate of the amplification FET and the drain of the reset FET, and the gate of the access FET is connected to the scanning circuit. The scanning signal output terminal is connected, and the source electrodes of the access FETs are commonly connected between pixels to serve as the image signal output terminal.In this image sensor, the access signal and reset signal are overlapped, so that the photodiode is The timing for accessing the signal current from the amplification FET immediately before resetting the photodiode and the timing for accessing the signal current from the amplification FET when resetting the photodiode are set. In addition, a first image signal output line for outputting the signals of the odd-numbered photodiodes and a second image signal output line for outputting the signals of the even-numbered photodiodes were provided. It is also possible to have a configuration in which the image signal including the offset signal of each pixel and the offset fixed pattern noise signal appear in sequence on the output line. too
By taking the difference signal between this image signal and the offset signal, it is possible to obtain an image signal from which fixed pattern noise has been removed for each pixel. FET
The fixed pattern noise that is output through the access FET can be accurately removed, but since the image signal and offset signal are output alternately, if there is only one output line, the data rate is halved. If high-speed reading is required, a drop in data rate can be prevented by providing two lines, one for outputting signals from odd-numbered pixels and one for outputting signals from even-numbered pixels. EXAMPLE Hereinafter, one embodiment of the present invention will be described with reference to the drawings, and FIG. 1 shows an equivalent circuit of an image sensor according to the present invention.

Each pixel is composed of a photodiode, an amplification FET, an access FET, and a reset FET.

Ia, 2a, 3a are photodiodes, lb, 2b, 3b are amplification FETs, 1c
, 2c, 3c are access FETs, and 1d.

2d and 3d are reset FETs. Access FE
The sources of T are commonly connected to form an image signal output line 5, and the sources of the reset FETs are commonly connected to form a reset voltage supply line 6. 7.8.9, 10.
+1 and 12 are half pit shift circuits, which are connected in sequence and function as a shift register by applying a clock pulse. YLY2, Y3, Y4, Y5 and Y6 are parallel output signals of the shift register, which are sequentially shifted by half pits. 13 and 14 are shift clock lines for scanning, ! 5 is a start signal input terminal, and 16 is an output terminal for an expansion signal. Can be expanded to a practical number of pixels.

Next, the operation of the image sensor of the present invention will be explained. Second
The figure is an operation timing chart of the image sensor in the first embodiment, and shows clock signals CKL, CK2,
Along with the start signal ST, the parallel output signals Y1, Y2, Y3, Y4, Y5 and Y6 of the shift register and the image output signal appearing at terminal 5 are shown. Y2, Y
3. Even though Y4, Y5, and Y6 sequentially overlap each other by half a cycle, the image sensor of the present invention stores a constant charge by charging the photodiode to a constant voltage (Vdd-Vrs) at the time of reset, and then The amplified image output signal is obtained by receiving the change in the terminal voltage of the photodiode due to the discharge of the charged charge due to the photocurrent to the gate of the amplification FET.In particular, the signal current becomes non-uniform due to the non-uniformity of the characteristics of the FET. , causing fixed pattern noise.

In the dark, the photodiode terminal voltage is held at the reset voltage until the next reading timing because there is no discharge due to the photocurrent.In other words, the fixed pattern noise signal in the dark is the output signal obtained at the timing when the reset FET conducts. (offset signal) is equal to 1. y Y
L Y2, Y3, Y4, Y5, and Y6 sequentially overlap each other by half a cycle, so go to 1. Through the circuit connection as shown in Figure 1, the image signal including the offset signal and the subsequent offset signal of that pixel are output. be able to.

FIG. 3 is an equivalent circuit of an image sensor according to a second embodiment of the present invention.

The configuration of each pixel and shift register is the same as that of the first embodiment (in the parallel output of the shift register, the parallel output pulses except for the top and bottom are the reset pulse of the previous pixel and the access pulse of the main pixel). Shared7
). la, 2a, 3a.

4a, lb, 2b, 3b, 4b,
lc, 2c, 3c, 4c, 1d, 2d,
3d and 4d are photodiodes and amplification FE, respectively.
T, the access FET and the reset FET are a.The source electrodes of the odd-numbered access FETs are commonly connected to form the first image signal output line 5a, and the source electrodes of the even-numbered access FETs are commonly connected to form the first image signal output line 5a. FIG. 4 is an operation timing chart of the image sensor in the second embodiment, in which parallel output signals Yl, Y2, Y3, Y4 of the shift register are used together with clock signals CKI, CK2, and a start signal. The timing of the image signal appearing at the 5a terminal, the timing of the offset signal appearing at the 5b terminal, the timing of the image signal appearing at the 5b terminal, and the offset signal appearing at the 5a terminal. Even if the timing matches
In the first embodiment, the output data rate of the image signal is half the clock frequency, and in order to scan one pixel,
In the second embodiment, the first image signal output line outputs the signals of the odd-numbered photodiodes, and the second image signal output line outputs the signals of the even-numbered photodiodes. In order to provide an image signal output line, the overall output data rate of the image signal is equal to the clock frequency, and in order to scan one pixel, there is a one-stage half-pit shift circuit.Therefore, this embodiment has a high speed of 41. 4 Figure 5 shows an output circuit that delays the image output signal by one clock period and amplifies it differentially with the offset signal.As a result, the offset component is subtracted for each pixel and fixed pattern noise is eliminated. Although the output circuit can be significantly reduced, the output circuit is a current-voltage converter 1.
7. Analog switches 20, 21. Sample and hold capacitor 18, buffer 19 and differential amplifier 2
It consists of 2. CKI and CK2 are pulses applied to the control terminal of the analog switch.
4 is a terminal for manually inputting a signal from the image sensor, and an output terminal for an image signal from which fixed pattern noise has been removed. FIG. 6 is an output circuit applied to the image sensor according to the second embodiment, and Even though it consists of two circuits that process the image signal and the odd-numbered image signal, each circuit has the same power as the one in Figure 5 (the connections of CKI and CK2 applied to the control terminal of the analog switch are opposite to each other). Even if the image signals are obtained from the terminals 24a and 24b, from which odd-numbered and even-numbered fixed pattern noises have been removed, respectively, the effects of the present invention can reduce the fixed pattern noise of an amplified MOS image sensor. Therefore, the image sensor of the present invention is extremely useful as an input device for information processing equipment, and its industrial effects are significant.

[Brief explanation of drawings]

FIG. 1 shows an equivalent circuit of an image sensor according to a first embodiment of the present invention. FIG. 2 shows an operation timing chart of an image sensor according to a first embodiment of the present invention. The equivalent circuit of the image sensor according to the second embodiment is as follows. FIG. 4 is an operation timing chart of the image sensor according to the second embodiment of the present invention. Output circuit for removing offset portion Figure 6 is a diagram of an output circuit for removing offset portion of each pixel connected to the image sensor according to the second embodiment. , lb, 2b, 3b, 4b...FET for amplification. lcl 2C13C14C...FET for access
. ld, 2d, 3d, 4d...FET for reset. 5, 5a, 5b... Image signal output terminal, 6... Reset voltage supply line, 7, 8, 9, 10.11.1
2...Half pit shift 1il 13.14
...Shift clock line, 15...Start signal input terminal, 16...Extension signal output terminal, 17
, 17a, 17b - current voltage converter 18, 1
8a, 18b...Sample hold capacitor, 19, 19a, 19b buffer 20, 20a,
20b 21, 21a, 21b... Analog switch, a, 22b... Differential amplifier 23.3b... Image signal input terminal, 24° 4b... Image signal output terminal.

Claims (3)

[Claims] (1) In an amplifying MOS image sensor in which each pixel consists of a photodiode, an amplifying field-effect transistor (FET), an access FET, and a shift register for generating a scanning signal, a period in which only the access FET is made conductive by a scanning signal, and a subsequent period An image sensor characterized in that an access FET and a reset FET are made conductive at the same time, and an image signal including an offset and an offset signal are sequentially output to an image signal output line for each pixel. (2) A first image signal output line that outputs signals of odd-numbered pixels and a second image signal output line that outputs signals of even-numbered pixels are provided, and the timing of the offset signal of the first output line is Claim (1) characterized in that the timing of the image signal including the offset of the second output line and the timing of the image signal including the offset of the first output line and the offset of the second output line are made to match. The image sensor described. (3) Each pixel is equipped with a delay circuit that delays the image signal including the offset to match the timing of the offset signal, and a differential amplifier that differentially amplifies the image signal including the delayed offset and the offset signal. An output circuit characterized by removing pixel offset.