JPS6337995B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge detection circuit that is suitable for a high-speed operating line sensor and can be integrated with the sensor on the same semiconductor substrate.

In recent years, there has been a tendency for semiconductor functional devices to have the peripheral circuits necessary to operate them integrated on the same semiconductor substrate (on-chip), but this trend is also becoming more prevalent in character recognition devices and facsimile machines (hereinafter referred to as OCR).
The same applies to line sensors used for fax (abbreviated as fax).

On-chip implementation of shift register drive circuits (CCD transfer pulse generation circuits) and signal charge detection circuits in the readout section of line sensors has already been carried out, and recently simple signal processing circuits, such as sample and hold circuits, have been implemented on-chip. There is a tendency to integrate such things. On the other hand, along with recent improvements in information processing technology, line sensors are now required to have high speed and high sensitivity characteristics in terms of their performance.

FIG. 1 shows an example of a conventional line sensor equipped with two readout sections B ₁ and B ₂ and a detection circuit for the signal output appearing at the output diode D. The photosensitive section shown in A plays the role of reading each horizontal row of the illuminated image pickup object, such as lines drawn on a form, by photoelectric conversion, and the photosensitive section shown in A is responsible for reading the illuminated image pickup object, for example, lines drawn on a form, one by one, by photoelectric conversion. The group of signal charges is transferred to each readout section by the operation of a transfer gate (not shown).
The data is transferred all at once to each bit in, for example, a two-phase drive type CCD shift register constituting B ₁ and B ₂ . These two signal charge groups are shown by the dotted line.
Transfer electrodes 11,
12, 13, 14, 15... and 21, 22,
Figure 2 a, b applied to 23, 24, 25...
are transferred in the directions of arrows A and B, respectively, by the transfer voltages φ ₁ and φ ₂ as shown in the figure, and the output gate
It alternately passes directly under OG and is supplied to output diode D.

The output voltage, which is also provided in a time series by the signal charges sent in a time series alternately from the two readout sections B ₁ and B ₂ , is sequentially detected by the first source follower amplifier 1. However, if one signal charge that has flowed into the output diode D remains even after being detected, it will be mixed with the charge that is to be detected next. To avoid this, it is necessary to remove the residual charge each time one charge detection is completed.For this purpose, the output diode D is equipped with _a reset MOS transistor ( Hereinafter abbreviated as MOST) QR
A reverse bias voltage is applied via.

If the above operation is shown using the transfer voltages φ ₁ and φ ₂ shown in FIGS. 2a and 2b, for example, the first reading section
The inflow charge from _B1 is detected during the period _τ1 of the first half of the waveform of the first phase transfer voltage _φ1 , and the charge is removed (reset) during the period _τ2 of the second half of the same waveform. Also,
Detection of the inflow charge from the second reading section _B2 is performed during the first half period _τ3 of the second phase transfer voltage _φ2 , and reset is performed during the second half period _τ4 . The same applies to subsequent signal charges that subsequently flow in alternately from the first and second reading sections, and detection is performed at τ ₅ , τ ₇ , etc., respectively, and reset is performed at τ ₆ , τ ₈ Do it with... In other words, since the reset voltage is applied at τ ₂ , τ ₄ , τ ₆ , τ ₈ . join.

By the way, amplifier 1 works as an active element.
The output voltage that appears at the output terminal P, which consists of MOST・Q ₁ and MOST・Q ₁ L, which acts as a load.
The waveform of Vo does not rise sharply due to the influence of the resistance when MOST/Q ₁ is turned on, the parasitic capacitance due to the presence of the connected MOST/QSH for the switch, the wiring capacitance, and the insulated gate capacitance of MOST/Q ₂ . Also, when disconnecting MOST/Q ₁ , the load
Due to the influence of the MOST・Q ₁ L resistance and the various capacitances mentioned above, the fall of the output voltage Vo does not become steep, and the second
The waveform will be as shown in Figure d. however,
MOST·Q ₂ is an active element of the second source follower amplifier 2, MOST·Q ₂ L is a MOST for loading the active element, and V _DD is a power supply voltage of the first and second source follower amplifiers. For this reason, the repetition frequency of the reset voltage φ _R must be twice the repetition frequency of the transfer voltages φ ₁ and φ ₂ , for example, 10 MHz, as is clear from _FIG . The duration is about 50ns. Furthermore, as mentioned above, the output voltage Vo appears as a pulse train, so in order to convert it into an analog signal, it is necessary to sample and hold the voltage. This sample-and-hold circuit (hereinafter abbreviated as S/H circuit) is configured by the insulated gate capacitance of MOST-QSH and MOST- _{Q 2 and} the conductance of MOST-Q ₁ L because MOST-Q 1 is in the cut-off state. However, it has a time constant of approximately 30 ns. After the signal passes through the S/H circuit, that is, the second
After passing through the source follower circuit 2 of Only the signal voltage Vo whose amplitude appears in the negative polarity direction is shown as a reference level.

By the way, in order to sample and hold the voltage Vo in Figure 2 d, it is necessary that the flat part F following the leading edge of the voltage waveform is appropriately wide, but in reality, for the reasons mentioned above, the flat part F is narrow. , or only a waveform with almost no flat portions can be obtained, and for this reason, the pulse generating circuit 3 shown in FIG. 1, which generates extremely narrow sampling pulses, is required. The configuration of the pulse generation circuit 3 requires a complex combination of frequency dividers and logic circuits, and integrating this on the same semiconductor substrate as the line sensor requires a complicated circuit and is difficult. arise. Besides, the voltage
If the flat portion of Vo is narrow like this, it becomes extremely difficult to set the sampling pulse timing.

The present invention was made in view of the above-mentioned difficulties, and in order to solve this problem, each transfer charge in the readout sections B ₁ and B ₂ of the sensor is not collected in one output diode, but is separately prepared. The present invention provides a new signal charge detection circuit in which each signal of the first and second systems is combined after being detected by a first-stage amplifier connected to each of these diodes and sampled and held. The details will be described below using the drawings.

FIG. 3 shows a preferred embodiment of the signal detection circuit for the line sensor according to the present invention, and FIG.
The figure is a timing chart of various voltages in the circuit, and portions equivalent to those in FIGS. 1 and 2 are designated by the same symbols.

First, the charges in the odd-numbered and even-numbered cell groups in the photosensitive section A are transferred all at once to each bit in the CCD shift registers constituting each readout section B ₁ and B ₂ by the action of a transfer gate (not shown). It will be done. These 2
The signal charges of the system pass directly under the output gate OG transferred in the directions of arrows A and B, respectively, and flow into the output diodes D ₁ and D ₂ of the respective readout sections B ₁ and B ₂ . First, the signal charge of the first system is reset by the reset voltage φ _R1 applied to the reset MOST QR ₁ during the period from time t ₁ to _{t 2} , t ₅ to t ₆ , . . . During the period from t ₂ to _{t 5} , from t ₆ to _{t 9} when _R1 returned to a low level, the first
is detected by the amplifier 1A and appears as Vo ₁ at the output terminal P ₁ of the amplifier. Moreover, the signal charge of the second system is the reset voltage φ _R2 applied to the reset MOST/QR ₂ during the period from time t ₃ to _{t 4} , from t ₇ to t ₈ .
During the period t ₄ -t ₇ , t _{8 -t 11} . ₂ appears as Vo ₂ .

Since each output voltage Vo ₁ and Vo ₂ is taken out independently by separate amplifiers 1A and 1B in this way, the repetition frequency is equal to the output voltage Vo shown in FIG.
, that is, the repetition frequency of the transfer voltages φ ₁ and φ ₂ is the same. For this reason, as seen in Fig. 4e and f, the flat part F ₁₁ of the voltage Vo ₁ ,
F ₁₂ ... as well as the duration of the plateau of voltage Vo ₂
F ₂₁ and F ₂₂ are sufficiently wide, making it easy to perform sample hold even if the width of the sampling pulse is relatively wide. Therefore, there is no need to make the pulse generator circuit complicated in order to make the sampling pulse width sufficiently narrow.
There is no risk that the scale of the circuit will increase. Figure 4g shows the output voltage of the first and second systems mentioned above.
After sampling Vo ₁ and Vo ₂ ,
Combine at the point S shown in FIG.
the second stage source follower amplifier 2 connected to
This figure shows the waveform of the final output voltage VSH that appears across the load MOST Q ₂ L of the amplifier after detecting the sampled and held composite voltage.

A major advantage of this circuit, as can be easily determined from the timing diagram in FIG. 4, is that the reset voltage can be directly used as the sampling pulse. That is _, the second reset voltage φ _R2 that lasts from time t _{3 to t 4} , t _{7 to t 8} . Since it is within each flat portion F ₁₁ , F ₁₂ , . . . which continues for a period of t _{9 .} . . , the first output voltage Vo ₁ can be sufficiently sampled with the reset voltage φ _R2 . The first reset voltage φ _R1 , which lasts from time _t5 to _t6 , from _t9 to _t10 , continues at the leading edge of the second output voltage _Vo2 from _t5 to _t7 , from _t9 to _t11 , . . , _the second output voltage Vo ₂ can be sufficiently sampled with _{the voltage φ R1 .} Incidentally, this detection circuit can be applied to a line sensor having a readout section of three or more CCDs driven by transfer voltages of three or more phases, and also to functional elements other than line sensors. However, in that case, three or more sample-and-hold MOSTs may be combined depending on the number of readout sections, and signals from each readout section may be combined. As described above, the signal charge detection circuit for a line sensor according to the present invention allows easy sampling, and since the reset voltage can be directly used as a sampling pulse, a high-performance sampling pulse generator can be omitted. This reduces the number of processes,
Since the chip size can be reduced and it can be made suitable for high-speed operation, extremely large practical effects can be expected.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the main parts of a conventional line sensor and its signal charge detection circuit, Fig. 2 is a timing diagram showing the voltage applied to each part in the circuit, and Fig. 3 is a main part of the line sensor according to the present invention. FIG. 4 is a timing diagram showing voltages applied to various parts of the circuit. 1, 1A, 1B: 1st stage source follower amplifier, 2: 2nd stage source follower amplifier,
3: Sample pulse generation circuit, 11, 12, 1
3, 14, 15..., 21, 22, 23, 24,
25...: CCD transfer electrode, A: Photosensitive part, B ₁ ,
B ₂ : Readout section, D, D ₁ , D ₂ : Output diode,
O: Final output terminal, P, P ₁ , P ₂ : Output terminal of first stage source follower amplifier, Q ₁ , Q ₂ , Q ₁ L,
Q ₂ L, Q ₁₁ , Q ₂₁ , Q ₁₂ , Q ₂₂ , QSH ₁ , QSHz, QR,
QR ₁ , QR ₂ :MOS transistor, φ _R , φ _R1 ,
_φR2 : Reset voltage, _φSH , _φSH1 , _φSH2 : Sampling voltage.

Claims (1)

[Claims] 1. A photosensitive section consisting of a plurality of light receiving cells that generate signal charges through photoelectric conversion, and a time-series transfer of the signal charges of the odd-numbered light-receiving cells and the signal charges of the even-numbered light-receiving cells of the photosensitive section separately. Output as 2
In a line sensor consisting of a system readout section, a detection circuit consisting of an output diode, its reset means, and first stage amplification means is connected to each readout section, and a sample is connected to the output side of each detection circuit. The hold circuits are connected, and sampling pulses are alternately supplied to the sample and hold circuits connected to the other detection circuit in a relationship that matches the reset pulse to the reset means of one of the detection circuits, and the output signals of both sample and hold circuits are combined. A signal charge detection circuit for a line sensor, which is characterized in that the signal is extracted as a single output.