JP2001346104A - Solid-state image pickup device and image pickup device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pickup device that monitors an incident luminous quantity at image pickup in real time with high accuracy so as to attain optimum exposure control at all times. SOLUTION: A 1st solid-state image pickup element 10 having a photo diode 11 and a reset drain 15 as a photo diode PD2 and a 2nd solid-state image pickup element 20 having a photo diode 21 and a reset drain 25 whose incident face side is shaded are arranged to a light receiving section 120 of the solid-state image pickup element 100 in a matrix form. A difference signal output section 150 outputs an electric signal Ip in response to a difference between an electric signal charge Iout from the photo diode PD2 of the 1st solid-state image pickup element 10 and an electric signal charge Idark from the reset drain 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device capable of monitoring the amount of incident light and an imaging device using the same.

[0002]

2. Description of the Related Art In a solid-state image pickup device which uses a photodiode as a photoelectric conversion unit and amplifies a current corresponding to a charge generated by the photodiode with an amplifying transistor and outputs the amplified signal, the charge of the same pixel is reset. A monitoring photoelectric conversion unit is formed in a part of the main electrode (reset drain) of the transistor of FIG. 1, and the incident light amount at the time of photographing is monitored by the monitoring photoelectric conversion unit, and based on the obtained electric signal. A solid-state imaging device for performing exposure control and the like has been proposed by the present applicant (Japanese Patent Application Laid-Open No. 11-1999).
204767).

In this solid-state imaging device, the amount of light actually incident on each pixel can be monitored in real time during photographing. Therefore, optimal exposure control (shutter speed control, aperture control, etc.) according to the photographing situation is always performed. be able to.

[0004]

In recent years, in solid-state imaging devices such as image sensors, there has been a demand for higher performance exposure control.

For example, in a solid-state imaging device, the actual incident light amount is monitored in real time with high accuracy, so that T
Reflected in control of the speedlight light amount by TL dimming, automatic control of the combination of shutter speed and aperture, etc.
There is always a need to be able to shoot with optimal exposure. The present invention has been made in view of such circumstances,
An object of the present invention is to provide a solid-state imaging device capable of always performing optimal exposure control by monitoring the amount of incident light at the time of photographing with high accuracy in real time.

[0006]

In order to solve the above-mentioned problems, the invention according to claim 1 has a first photoelectric conversion unit and a second photoelectric conversion unit which respectively generate signal charges corresponding to incident light. One pixel, a second pixel having a third photoelectric conversion unit that generates signal charges corresponding to incident light, and a second pixel having a fourth photoelectric conversion unit whose incident surface side is shielded from light are arranged in a matrix on the light receiving unit. The arranged solid-state imaging device includes a differential signal output unit that outputs an electric signal according to a difference between the signal charge from the second photoelectric conversion unit and the signal charge from the fourth photoelectric conversion unit. It is. Accordingly, when the electric signal corresponding to the incident light obtained by the second photoelectric conversion unit is used as a monitor signal at the time of exposure control, the electric signal from which noise components such as dark current have been removed is output as a differential signal output. Obtained from the department.

According to a second aspect of the present invention, the first pixel is composed of an amplifying transistor, and the electric signal corresponding to the signal charge supplied from the first photoelectric converter to the control electrode of the amplifying transistor. An output unit for outputting the signal charge generated by the first photoelectric conversion unit, a first transfer unit for supplying the signal charge generated by the first photoelectric conversion unit to the control electrode, and a signal charge generated by the first photoelectric conversion unit. A reset drain for discharging, the second photoelectric conversion unit is formed in a semiconductor region constituting the reset drain, and the second pixel is formed of an amplifying transistor, and the third photoelectric conversion unit And an output unit for outputting an electric signal corresponding to the signal charge supplied to the control electrode of the amplifying transistor, and a second unit for supplying the signal charge generated by the third photoelectric conversion unit to the control electrode. A transfer unit, and a reset drain for discharging a signal charge generated by the third photoelectric conversion unit; and the fourth photoelectric conversion unit is formed in a semiconductor region forming the reset drain. The upper surface of the semiconductor region is covered with a light shielding plate. Thus, in the amplification type solid-state imaging device, when an electric signal corresponding to the incident light obtained by the second photoelectric conversion unit is used as a signal for monitoring at the time of exposure control, noise components such as dark current are reduced. The removed electric signal is obtained from the difference signal output unit.

According to a third aspect of the present invention, the first and second pixels provided in the light receiving section include a first pixel group including the first pixel and only the second pixel. A second pixel group, and the difference signal output unit outputs an electric signal corresponding to a difference between the signal charge from the first pixel group and the signal charge from the second pixel group. Is what you do.
Accordingly, by comparing the electric signal from the first pixel group having the plurality of first pixels with the electric signal from the second pixel group having the plurality of second pixels, the electric signal representing the difference is obtained. Signal detection accuracy can be improved.

According to a fourth aspect of the present invention, the first pixel group and the second pixel group form different rows in the light receiving section. The first in the light receiving section,
In the solid-state imaging device in which the second pixels are arranged in a matrix, an electric signal representing the difference can be easily obtained.

According to a fifth aspect of the present invention, a color filter is formed in a predetermined arrangement pattern on an incident surface of the first and second pixels, and the first pixel group and the second pixel group are Are divided so that the ratio of the color filters in the first pixel group and the ratio of the color filters in the second pixel group match each other. Thus, an electric signal representing the difference can be obtained without being affected by the color filter.

According to a sixth aspect of the present invention, the light receiving section is divided into a plurality of areas, and the difference signal output section outputs an electric signal corresponding to the difference for each area. Thereby, in the solid-state imaging device in which the divided photometry is performed, the electric signal representing the difference can be obtained for each divided region. According to a seventh aspect of the present invention, there is provided the solid-state imaging device according to any one of the first to sixth aspects, a shutter unit, and a control unit for controlling opening / closing timing of the shutter unit. Controls the opening / closing timing of the shutter unit based on the electric signal output from the difference signal output unit. Thereby, in the photographing device, shutter control according to the monitored incident light amount can be performed.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a solid-state imaging device 100 according to the first embodiment.
The first pixel 10 (“a” in FIG. 5) arranged in FIG.
(Shown in FIG. 1).
FIG. 1A is a plan view of the first pixel 10, and FIG.
1A is a cross-sectional view taken along line XX, and FIG.
It is sectional drawing along the YY line of (a). FIG. 2 is a circuit diagram of the first pixel 10.

FIG. 3 shows a device structure of a second pixel 20 (indicated by "b" in FIG. 5) arranged in the solid-state imaging device 100, of which FIG. 2B is a plan view of the pixel 20, FIG. 3B is a cross-sectional view taken along line XX of FIG. 3A, and FIG. 3C is a cross-sectional view taken along line YY of FIG. FIG. FIG. 4 is a circuit diagram of the second pixel 20.

As shown in FIG. 1A, the first pixel 10 has a photodiode 11 (first photoelectric conversion unit; PD1) that generates and accumulates charges according to incident light, and a gate region thereof. 12A, an electric signal V corresponding to the signal charge received
out type junction field effect transistor (JFE
T) 12 and a transfer transistor (Tr1) 1 for supplying (transferring) signal charges generated and accumulated by the photodiode 11 to the gate region 12A of the JFET 12.
3 and supply (transfer) to the gate region 12A of the JFET 12
A reset transistor (Tr2) 14 for discharging the generated signal charges through the reset drain 15, and a photodiode PD2 parasitic on the reset drain 15.
(A second photoelectric conversion unit) and a switch MOS transistor (Tr3) 18 formed in a region that partitions pixels.

The photodiode 11, JFET1
2, the P-type transfer transistor 13 and the P-type reset transistor 14 are formed in the N-type semiconductor layer 2 on the P-type semiconductor substrate 1 as shown in FIGS. 1B and 1C. . In addition, photodiode 11 for one pixel, JFET
12, the transfer transistor 13, and the reset transistor 14 are surrounded by a high-concentration N-type (N +) impurity diffusion layer 3.

Here, the photodiode 11 corresponds to FIG.
As shown in (c), a P-type impurity diffusion layer (charge storage region) 4 formed in the N-type semiconductor layer 2 and a high concentration N-type impurity diffusion layer formed above the P-type impurity diffusion layer 4. Layer 5
The signal charge generated according to the incident light is stored in the P-type impurity diffusion layer (charge storage region) 4. In the JFET 12, as shown in FIG. 1B, the P-type impurity diffusion layer 6 formed in the N-type semiconductor layer 2 forms a gate (gate region 12A), and is formed in the P-type impurity diffusion layer 6. N-type impurity diffusion layer 7 constitutes a source, and N-type impurity diffusion layer 8 also formed in P-type impurity diffusion layer 6.
Constitute a channel. The signal charge generated and stored in the photodiode 11 is transferred to the gate region 12A of the JFET 12 through the transfer transistor 13.
An electric signal Vout corresponding to the supplied (transferred) signal charge is supplied from the source 7 to the vertical signal line 16.
Is output via.

The transfer transistor (Tr1) 13 functions as a first transfer unit. As shown in FIG. 1A, the source of the transfer transistor (Tr1) is a charge storage region (P-type impurity diffusion layer) 4 of the photodiode 11. And the drain is JF
It is composed of a P-type impurity diffusion layer 6 constituting the gate region 12A of the ET 12. A gate electrode 13C is formed between the source and the drain. The transfer transistor 13 has a function of supplying (transferring) signal charges stored in the P-type charge storage region (P-type impurity diffusion layer) 4 of the photodiode 11 to the gate region 12A of the JFET 12.

Reset transistor (Tr2) 14
As shown in FIGS. 1A and 1B, the source is JFE
The P-type impurity diffusion layer 6 constituting the gate region 12A of T12 is configured, and the drain (reset drain 15) is configured by the P-type impurity diffusion layer 9. A gate electrode 14C is formed between the source and the drain (reset drain 15). The reset transistor 14 thus configured has a function of resetting the potential of the gate region 12A of the JFET 12.

Meanwhile, in the first pixel 10, a reset drain wiring 17 (shown by oblique lines rising to the right in FIG. 1A) that shields portions other than the photodiode 11 is provided with a portion other than the photodiode 11 (reset drain 15). (Above) is provided with an opening 17A. Light is allowed to enter the P-type impurity diffusion layer 9 forming the reset drain 15 from the opening 17A, and the photodiode PD2 is formed in this portion (parasitic photodiode).

As will be described in detail later, the signal charge generated by the photodiode PD2 is controlled by the reset transistor 14 and the switch MOS transistor (Tr3) 18 so that the pixels (pixels) included in the same row of the solid-state imaging device 100 can be used. As an electric signal Iout from the first pixel group),
At a certain timing, the signal is sent to the difference signal output unit 150 side (output of the first pixel group).

FIG. 2 shows the structure of the pixel 10 of FIG.
As shown in FIG. 5, various drive pulses are input from the vertical scanning circuit 70 (FIG. 5), and a predetermined voltage is supplied. Specifically, a constant voltage source VDD is connected to the photodiode (photoelectric conversion unit) 11, and a reverse bias is applied. or,
The drive pulse φTG is supplied to the gate electrode (transfer gate 13C) of the transfer transistor (Tr1) 13 and the drive pulse φRSG is supplied to the gate electrode (reset gate 14C) of the reset transistor (Tr2) 14 at its drain ( Drive pulse φRSD
Are each supplied. The source (node N1 side) of the JFET 12 is connected to a constant voltage source VSS via a constant current source (both are not shown). With the function of the constant current source, a constant current Ibias flows to the source of the JFET 12. , Source follower is done.

In the first pixel 10, the JFET 12
The source follower operation causes the source potential (potential of the node N1) Vout to become an electric signal obtained by amplifying the signal indicated by the electric charge stored in the gate region 12A of the JFET 12 (current amplification). By controlling the waveforms of the supplied drive pulses φTG, φRSG, and φRSD, the electric signal Vout appearing at the source (on the node N1 side) of the JFET 12 is output at a constant timing. Also, the first
In the pixel 10, the signal charge generated and accumulated in the photodiode PD2 (reset drain 15) at a certain timing different from the above is supplied via the reset drain wiring 17 to the differential signal output unit 150 in the form of an electric signal Iout. Supplied to the side.

As shown in FIGS. 3 and 4, the second pixel 20 has the same basic structure as that of the first embodiment, and has a photodiode (third photoelectric conversion unit) 21.
, JFET 22, transfer transistor (second transfer unit) 23, and reset transistor 24. In the second pixel 20, portions other than the photodiode 21 are covered by the reset drain wiring 17. Therefore, in the second pixel 20, the first pixel
The parasitic photodiode PD2 like the pixel 10 is not formed (FIG. 4). Therefore, P of the reset drain 25
Unlike the P-type impurity diffusion layer 9 of the reset drain 15, the P-type impurity diffusion layer 29 generates signal charges corresponding only to noise components such as dark current (functions as a light-shielded fourth photoelectric conversion unit). Do). The other components of the second pixel 20 are denoted by the same reference numerals as those of the corresponding components of the first pixel 10 shown in FIG. 1, and description thereof will be omitted.

The second pixel 20 also has the first pixel 10
Similarly to the above, various driving pulses are input from the vertical scanning circuit 70 (FIG. 5), and a predetermined voltage is supplied (FIG. 4). In the second pixel 20, charges (signal charges including noise components such as dark current) remaining in the reset drain 25 at a predetermined timing are collected by the pixels (second pixel group) forming one row. Then, it is output to the difference signal output unit 150 as an electric signal Idark at a predetermined timing (output of the second pixel group).

In the difference signal output section 150 (FIG. 5), the electric signal Iout is compared with the electric signal Idark.
The electric signal (photocurrent) Ip indicating the difference is output as a value (photometric current proper) obtained by removing noise components such as dark current from the electric signal Iout indicating the monitored light amount. FIG.
1 is a circuit diagram of a solid-state imaging device 100 in which a first pixel 10 and a second pixel 20 are arranged.

In the solid-state imaging device 100 according to the first embodiment, the first pixel 10 (FIG. 1) having the above-described monitoring function and the second pixel 20 having no monitoring function (FIG. ) Are arranged in a matrix (in the illustrated example, 4 ×
6) They are arranged. In the figure, the first having the monitor function
Pixel 10 (indicated by “a” in the figure) is in the first row, the third row,
A second pixel 20 having no monitor function (indicated by “b” in the figure) is arranged in the second and fourth rows.

In each row of the matrix arrangement, all reset transistors (Tr2) in the pixels of the row are used.
The gate electrode 14C of 14 and the gate electrode 18C of the switch MOS transistor (Tr3) 18 are commonly connected for each row, and these reset transistors (Tr2) 1
4. The switch MOS transistor (Tr3) 18 can be turned on and off at the same time (see FIG. 1).

As is clear from FIGS. 1 and 5, for each row, all the reset transistors (Tr2) in the row are used.
14. When the switch MOS transistor (Tr3) 18 is on (in a conductive state), the gate regions 12A and 22 of the JFETs 12 and 22 of all the pixels in the row are used.
A and the reset drains 15 and 25 are electrically connected to the reset drain wiring 17 of the row, and the switch MOS transistor (Tr3) 1 between pixels
8 electrically connects the gate regions 12A and 22A and the reset drains 15 and 25 of all the JFETs 12 and 22 in the row.

In each row, all reset transistors (Tr2) 14 and switch MOS transistors (Tr3) 18 in the row are turned off (in a cutoff state).
In this case, the gate regions 12A and 22A of the JFETs 12 and 22 of all the pixels in the row are electrically disconnected from the reset drain lines 17 in the row. Therefore, for each row, the reset drain wiring 17 of the row is
Charges in the gate regions 12A and 22A of the JFETs 12 and 22 can be discharged through the reset drains 15 and 25, and a drive signal φRSD for controlling the potentials of the gate regions 12A and 22A can be given.

Attention is paid to each row including the first pixel 10 having the monitor function. When all the reset transistors (Tr2) 14 and the switch MOS transistors (Tr3) 18 in the row are turned on. The gate regions 12A and the reset drains 15 of all the JFETs 12 in the row are electrically connected by a switch MOS transistor (Tr3) 18 between pixels. At this time, the reset drain 15 of the first pixel 10 in the row is used.
Is a reset transistor (Tr2) of an adjacent pixel
14, the switch MOS transistor (Tr3) 18 and the reset drain 15 are electrically connected to the reset drain wiring 17 (L1, L3) of the row.

As a result, the electric signal Iout due to the signal charge (indicating the monitored incident light amount) generated in the first pixel 10 according to the light incident from the opening 17A is
The data can be output from the reset drain wiring 17 (L1, L3) of the row. Focusing on each row including the second pixel 20 having no monitor function, if all reset transistors (Tr2) 24 and switch MOS transistors (Tr3) 18 in the row are on, the pixel Switch MOS transistor (Tr3) between
18 electrically connects the gate regions 22A and the reset drains 25 of all the JFETs 22 in the row. At this time, the reset drain 25 of the second pixel 20 of the row is connected to the reset transistor (Tr2) 24 and the switch MOS transistor (Tr) of the adjacent pixel.
3) Via the 18 and the reset drain 25, it is electrically connected to the reset drain wiring 17 (L2, L4) of the row.

As a result, in the second pixel 20, the electric signal Idark due to the signal charge generated in the P-type impurity diffusion layer 29 of the reset drain 25 is output from the reset drain wiring 17 (L2, L4) of the row. Can be done. Note that peripheral circuits of the solid-state imaging device 100, for example,
The configuration of peripheral circuits such as the vertical scanning circuit 70 and the horizontal scanning circuit 80 is the same as that of a conventional solid-state imaging device, and a detailed description thereof will be omitted.

In the solid-state imaging device 100, each row including the first pixel 10 having a monitor function (the first row and the third row in FIG. 5).
Row), the reset drain wiring 17 (L) of each row (second row, fourth row) including the second pixel 20 having no monitor function.
1 to L4) are selection switches S composed of MOSFETs and the like.
Each of the driving pulses φRSD of the corresponding row of the vertical scanning circuit 70 is connected to the output section of each driving pulse φRSD via b1-4.

The reset drain wiring 17 of each row
(L1 to L4) are connected to the difference signal output unit 150 via the selection switch Sa1-4. A drive pulse φMON is applied to the gate electrode of each selection switch Sb1-4, and a pulse obtained by inverting the drive pulse φMON by the inverter 91 is applied to the gate electrode of each selection switch Sa1-4.

By the selection switches Sa1-4 and Sb1-4, the JFET1 of each pixel in the row is set.
The state in which the charges in the gate regions 12A and 22A are discharged through the reset drains 15 and 25 and the potentials of the gate regions 15 and 25 are controlled (driving signal φ
It is possible to switch between a state where the RSD is supplied and a state where the signal appearing on the reset drain wiring 17 (L1 to L4) of the row is output to the outside (to the difference signal output unit 150 side). That is, the selection switches Sa1-4, Sb1-4
, And selectively outputs the electric signals (Iout, Idark) generated at the reset drain 15 of the first pixel 10 and the reset drain 25 of the second pixel 20 to the difference signal output unit 150. Can be done.

The difference signal output unit 150 compares the electric signals Iout and Idark and outputs a signal Ip indicating the difference.
Is composed of current amplifiers 152, 153 and an amplifier 154, as shown in FIG. 5, and outputs from an output terminal 151 an electric signal I corresponding to a difference between the electric signals Iout and Idark.
p is output. Specifically, the first having a monitor function
And the reset drain line 17 (L1, L3) to which the pixel 10 ("a" in FIG. 5) is connected, and the reset drain line to which the second pixel 20 ("b" in FIG. 5) having no monitor function is connected. The output lines L11 and L12 in which the wirings 17 (L2 and L4) are combined are connected to one terminals of the current amplifiers 152 and 153 of the difference signal output unit 150, respectively, to change the current and the voltage. At this time, a reset voltage is applied to the other terminals of the current amplifiers 152 and 153. here,
The voltage supplied to the reset electrode of the first pixel 10 having a monitor function and the voltage of the second pixel 20 having no monitor function
The voltages supplied to the reset electrodes are set to the same value so that the operation is not hindered. Therefore, in the current amplifiers 152 and 153, the electric signals Iout and Idark are
Current-voltage conversion is performed based on the reset voltage.

The electric signals subjected to the current-voltage conversion are input to the terminals of the current amplifier 154, respectively. Here, as the current amplifier 154, one having very low input impedance is used. The electric signal that has been subjected to current-voltage conversion by the current amplifiers 152 and 153 and subjected to the subtraction processing by the amplifier 154 is used when a charge component overflows from the photocurrent (electric signal Iout) to a noise component such as a dark current and the photodiodes 11 and 21. The photometric current bhopper (electric signal Ip = Iout-Idark) is obtained by subtracting a possible current.

The electric signal Ip obtained by the difference signal output section 150 is used for determining the exposure time of the solid-state imaging device 100. That is, it is generated by the photodiode 11.
The value (intensity of light) of the accumulated signal charge is monitored based on the signal charge from the photodiode PD2 parasitic on the reset drain, and the result of this monitoring (electric signal Ip)
Exposure control using is performed.

Next, an example of a photographing apparatus 500 using the solid-state imaging device 100 will be described with reference to FIG.
In the imaging device 500, the solid-state imaging device 100 is disposed in a dark box 502 with a light-blocking shutter 501, and the controller 501 controls the shutter 501 and the speedlight 510.

The differential signal output unit 1 in the solid-state imaging device 100
The output terminal 151 of 50 is connected to a photocurrent processing circuit 504 having a photocurrent integration circuit 505 and a comparator 506.

The photocurrent integration circuit 505 further includes an operational amplifier 507, a capacitor CL, and a reset switch 50.
8. Here, the reset switch 5
08 is the reset signal φRST received at the gate electrode.
Discharges the charge of the capacitor CL in response to
The photocurrent integration circuit 505 is reset.

From the output terminal 151, the photocurrent integrating circuit 505
Is integrated and converted into a voltage Vip. The converted voltage Vip is compared with the reference voltage Vc by the comparator 506, and the voltage Vi is
When p becomes smaller than the reference voltage Vc, the shutter 5
01 is output to the controller 503 side.

As described above, in the solid-state imaging device 100 using the first and second pixels 10 and 20, the photodiode 1
Exposure time during shooting using shutters 1 and 21 (shutter 5
01 opening / closing time) can be controlled based on the electric signal Ip (Iout-Idark) monitored in real time by the photodiode PD2 parasitic on the reset drain 15, so that it is always appropriate in accordance with a change in the photographing situation. Exposure time can be obtained.

Here, the operation timing of the solid-state imaging device 100 when capturing a still image using the imaging device 500 will be described with reference to the timing chart of FIG.
In FIG. 7, the selection switch Sb1 is turned on between T1 and T8, and the selection switches Sb2, Sb3. At this time, the selection switch Sa1-4 is in a state opposite to that of the selection switch Sb1-4.

The vertical scanning and the horizontal scanning when the selection switch Sb1 is turned on (between T1 and T8) will be described below. First, vertical scanning is performed at T1 to T4. Specifically, at time T1, the signal Sb1 is switched from a low level to a high level (the signal Sa1 is switched from a high level to a low level). At this time, the signal RSG1, the signal RSD1
Are both low level.

In this state, the selection switch Sb1 is turned on, the selection switch Sa1 is turned off, the reset drain 15 of each pixel is connected to the vertical scanning circuit 70, and the vertical scanning circuit 70 supplies a high level signal to each first pixel 10. Is supplied. On the other hand, the selection switch S
As a1 turns off, each first pixel 10 is disconnected from the current output line L1. Note that the gate of the JFET 12 is fixed to the reset potential VGL before reaching the time point T1.

Between the time T1 and the time T2, the signal RSD
When the signal RSG1 becomes high level at the time point T2, the reset transistor (Tr2) 14 is turned on and the amplifying section (JFET1
2) A high level signal RSD is applied to the reset drain 15
1 is supplied and the gate is at the read voltage level VGH. At this point, the transfer transistor (Tr1) 13
Is off, the output signal Vout has a signal level Vdark corresponding to a noise component such as a dark current.

Here, paying attention to the second line shown in FIG. 5, since the selection pulse Sb2 supplied to the selection switch Sb2 is at a low level between T1 and T8 in FIG. 7, the reset transistor (Tr2) 24 The gate is fixed at a high level potential (Vref), and only the photometric current (FIG. 7)
In the second line, the second pixel 2 having no monitor function
0 “b” are output through the reset drain wiring 17 (L2). This electric signal Idark
Indicates a noise component such as dark current.

At time T3, the output capacitor Ctj
Are clamped to a signal level indicating a noise component such as a dark current. At time T4, the transfer transistor (Tr1) 13 turns from off to on, and the transfer transistor (Tr1) 1
By turning on 3, the signal charge of the photodiode 11 is transferred to the gate region 12A of the JFET 12.

(FIG. 5), the output capacitors Ctj... Connected to the vertical signal lines 81, 82.
The side of the output signal line which is clamped to a signal level indicating a noise component such as a dark current is level-corrected, and the corrected signal voltage Vout is output. After T6, horizontal scanning (in the example shown in FIG. 5, 1 to 6 rows) is performed.

First, at time T6, RSTH is supplied to the horizontal signal line 81 of the pixel in the first column, and the charge remaining on the horizontal output line is eliminated (reset). At time T7, the transistor Hj (FIG. 5) disposed between the horizontal output line of the first column and the horizontal scanning circuit 80 switches from off to on, and the output capacitor Ctj of the pixel in the first column is charged. The output signal is output to the horizontal output line.

Thereafter, the read operation of the next horizontal output line (second column) is started, and horizontal scanning is performed sequentially. As described above, the solid-state imaging device 100 according to the first embodiment
In the light receiving unit 120, a first pixel 10 having a monitoring function and a second pixel 20 not having a monitoring function are arranged in a matrix, and the first pixel 10 having a monitoring function is arranged in accordance with incident light obtained by the first pixel 10. The electric signal Ip representing the difference between the obtained electric signal Iout and the electric signal Idark obtained by the second pixel 20 is obtained, and this electric signal Ip is used as a signal for monitoring during exposure control. Exposure can be controlled without being affected by noise components.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
The embodiment will be described with reference to FIG. In the solid-state imaging device 200 according to the second embodiment, the light receiving section 220 includes the first pixel 10 according to the first embodiment described above.
(Pixels surrounded by a circle in the figure) and second pixels 20 (pixels surrounded by a triangle) are arranged in a matrix, and the incident surfaces of the first and second pixels 10 and 20 are colored in a predetermined pattern. Filters (for example, “R”, “G”, “B”) are arranged (in the illustrated example, Bayer arrangement).

In the solid-state imaging device 200 having the light receiving section 220 as described above, the difference between the electric signal Iout obtained from the first pixel 10 and the electric signal Idark obtained from the second pixel 20 is also obtained. , And a difference signal output unit 250. By the way, electric signals Iout, Idark
Varies depending on the type of the color filter arranged on the incident surface.

For this reason, K1 and K1 including the first pixel 10
Rows 2, K3 and K4 (first pixel group) and second pixel 20
And the light receiving unit 220 so that the ratio of the color filters included in the rows M1 and M2 (the second pixel group) including
Are divided on a line-by-line basis (in the horizontal direction). That is, in the differential signal output unit 250, rows K 1, K 2, K 3, and K 4 are connected to one terminal of the current amplifier 252, and M 1 and M 2 are connected to one terminal of the current amplifier 253.

Here, rows K1, M1 and K4 have the same arrangement with respect to the color filters, and rows K2, K3 and M2
The rows are in the same array. Therefore, the line L2 connected to one terminal of the current amplifier 252 of the differential signal output unit 250
1 and the pixel on the line L22 connected to one terminal of the current amplifier 253 have the same ratio of the included color filters, and the values of the obtained electric signals Iout and Idark are different from those of the color filters. Has no effect.

In the above embodiment, the light receiving section 220 is described as an example of a light receiving section arranged in a Bayer array. However, the arrangement of the color filters is not limited to this. Good. Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIG.

The solid-state imaging device 30 of the third embodiment
0 indicates that the light receiving unit 320 has three regions 320A, 320B,
320C, and three difference signal output units 350A, 350B, and 350C are divided into three regions 32C.
0A, 320B, 320C, the electric signals Iout, Idar
Electric signals Ip1, Ip2, and Ip3 indicating the difference of k are output.

Specifically, in the solid-state imaging device 300, the light receiving section 320 has the first
Pixel 10 (the pixel circled in the figure) and the second pixel 20
(Pixels surrounded by △) are arranged in a matrix, and color filters (for example, “R”, “G”, and “B”) are arranged in a predetermined pattern on the incident surfaces of the first and second pixels 10 and 20. Are arranged (Bayer arrangement).

Incidentally, in the third embodiment, 3
Electric signals Ip1 and Ip indicating the difference between the electric signals Iout and Idark from the three difference signal output units 350A, 350B and 350C for each of the three regions 320A, 320B and 320C.
2, Ip3, so that the first
Row D1, row D2 including pixel 10 and row E1, row E2 including first pixel 10 only in region 320B, and row F1, row F2, and region 320 including first pixel 10 only in region 320C.
Rows S1 and S2 that do not include the first pixel 10 are formed in any of A, 320B, and 320C.

In the difference signal output section 350A, one terminal of the current amplifier 352A is connected to the line L31 of the D1 and D2 rows, and one terminal of the current amplifier 353A is connected to the line L34 of S1 and S2. . In the differential signal output unit 350B, the line L32 of the E1 and E2 rows is connected to one terminal of the current amplifier 352B, and the line L34 of S1 and S2 is connected to one terminal of the current amplifier 353B.
Is connected.

In the differential signal output section 350C, one terminal of the current amplifier 352C is connected to the line L3 of the F1 and F2 rows.
3 is connected to one terminal of the current amplifier 353C.
1, the line L34 of S2 is connected.

As a result, the areas 320A, 320B, 32
In each area of 0C, without being affected by the color filter, and
The electric signal Ip according to the difference between the electric signals Iout and Idark
1, Ip2 and Ip3 are individually output. In the third embodiment, the light receiving section 320 is described as a light receiving section arranged in a Bayer array as an example. However, the arrangement of the color filters is not limited to this. Good.

[0064]

As described above, according to the first and second aspects of the present invention, the difference between the electric signal corresponding to the incident light obtained at the first pixel and the electric signal obtained at the second pixel. Is obtained, and an electric signal which is not affected by noise components such as dark current can be used as a monitor signal.
As a result, in the solid-state imaging device, the amount of incident light can be monitored in real time with high accuracy, and the optimal exposure reflected in control of the speedlight light amount by TTL dimming, automatic control of the combination of shutter speed and aperture, and the like. Control becomes possible.

According to the third aspect of the present invention, the first and the second
Are divided into a first pixel group including the first pixel and a second pixel group including only the second pixel, so that signal charges from the first and second pixel groups are compared with each other. As a result, an electric signal corresponding to the difference can be output, and the detection accuracy of the electric signal representing the difference can be improved. According to the fourth aspect of the present invention, in a solid-state imaging device in which first and second pixels are arranged in a matrix in a light receiving section, an electric signal representing the difference can be easily and accurately obtained.

According to the fifth aspect of the present invention, the first and the second
Even when a color filter is formed in a predetermined arrangement pattern on the incident surface of the pixel, an electric signal representing the difference can be obtained with high accuracy without being affected by the color filter.
According to the invention of claim 6, since the electric signal representing the difference is obtained for each of the divided regions, the electric signal representing the difference is divided by the solid-state imaging device in which the divided photometry is performed. The accuracy of the exposure control can be obtained for each region to improve the accuracy of the exposure control.

According to the present invention, since the opening / closing timing of the shutter is controlled based on the electric signal output from the difference signal output unit, the accuracy of the photographing apparatus according to the monitored incident light amount is improved. High shutter control is possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a device structure of a first pixel 10 according to a first embodiment.

FIG. 2 is a circuit diagram of the first pixel 10;

FIG. 3 is a diagram showing a device structure of a second pixel 20.

FIG. 4 is a circuit diagram of a second pixel 20.

FIG. 5 is a circuit diagram schematically showing a solid-state imaging device 100 using first and second pixels 10 and 20.

FIG. 6 is a photographing apparatus 50 using the solid-state imaging device 100;
FIG.

FIG. 7 is a timing chart showing waveforms of driving pulses supplied to first and second pixels 10 and 20.

FIG. 8 is a circuit diagram schematically showing a solid-state imaging device 200 using first and second pixels 10 and 20.

FIG. 9 is a circuit diagram schematically illustrating a solid-state imaging device 300 using first and second pixels 10 and 20.

[Explanation of symbols]

 10, 20 pixels 11, 21 Photodiode (photoelectric conversion unit) 12, 22, Amplifying transistor (JFET) 12A, 22A Gate region (control electrode) 13, 23 Transfer transistor (Tr1) 14, 24 Reset transistor (Tr2G) 15, 25 reset drain 17 reset drain wiring 17A opening 100, 200, 300 solid-state imaging device 500 imaging device

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/146 H04N 9/07 D 27/14 A H04N 9/07 H01L 27/14 A D F term (reference) ) 2H054 AA01 4M118 AA09 AA10 AB01 BA14 CA04 CA22 DD09 DD10 DD12 FA06 FA33 GB06 GC08 GC14 5C024 CX32 CX56 CY17 EX12 EX31 EX52 GX14 GY31 GZ10 GZ36 HX17 HX29 HX40 5C065 BB08 BB18 CC05 DD15 DD17 DD18 DD17 DD

Claims (7)

[Claims] 1. A first pixel having a first photoelectric conversion unit and a second photoelectric conversion unit that respectively generate signal charges according to incident light, and a third pixel that generates signal charges according to incident light. In a solid-state imaging device in which a photoelectric conversion unit and a second pixel having a fourth photoelectric conversion unit whose incident surface side is shielded from light are arranged in a matrix in a light receiving unit, a signal from the second photoelectric conversion unit is provided. A solid-state imaging device comprising: a difference signal output unit that outputs an electric signal according to a difference between the charge and the signal charge from the fourth photoelectric conversion unit. An output unit configured to output an electric signal corresponding to a signal charge supplied from the first photoelectric conversion unit to a control electrode of the amplification transistor; A first transfer unit for supplying the signal charge generated by the first photoelectric conversion unit to the control electrode; a reset drain for discharging the signal charge generated by the first photoelectric conversion unit; And the second photoelectric conversion unit is formed in a semiconductor region forming the reset drain, and the second pixel is formed of an amplification transistor, and the third photoelectric conversion unit controls the amplification transistor from the third photoelectric conversion unit. An output unit that outputs an electric signal corresponding to the signal charge supplied to the electrode; a second transfer unit that supplies the signal charge generated by the third photoelectric conversion unit to the control electrode; 3 A reset drain for discharging signal charges generated by the photoelectric conversion unit, and the fourth photoelectric conversion unit is formed in a semiconductor region constituting the reset drain, and an upper surface of the semiconductor region is a light-shielding plate. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is covered. 3. The first and second light-receiving parts provided in the light-receiving part.
Are divided into a first pixel group including the first pixel and a second pixel group including only the second pixel, and the difference signal output unit includes a first pixel group from the first pixel group. 3. The solid-state imaging device according to claim 1, wherein an electrical signal corresponding to a difference between the signal charge of the second pixel group and the signal charge from the second pixel group is output. 4. 4. The solid-state imaging device according to claim 3, wherein the first pixel group and the second pixel group form different rows in the light receiving unit. 5. A color filter is formed in a predetermined arrangement pattern on an incident surface of each of the first and second pixels, and the first pixel group and the second pixel group are arranged in the first pixel group and the second pixel group. The solid-state imaging device according to claim 3, wherein the ratio of the color filter in the pixel group and the ratio of the color filter in the second pixel group are separated from each other. . 6. The light receiving unit according to claim 1, wherein the light receiving unit is divided into a plurality of regions, and the difference signal output unit outputs an electric signal corresponding to the difference for each region. The solid-state imaging device according to any one of the above. 7. The solid-state imaging device according to claim 1, comprising: a shutter unit; and a control unit that controls opening / closing timing of the shutter unit. An image capturing apparatus, wherein the opening and closing timing of the shutter unit is controlled based on an electric signal output from a signal output unit.