JPH08139715A - Frame synchronizing communication system - Google Patents

Abstract

PURPOSE: To detect a correct frame synchronizing position at the receiver side by disposing the latter half of a frame synchronizing code between the digital data at nearly even intervals for generation of the frame information. CONSTITUTION: An FSC(frame synchronizing code) includes both codes 0000 and 1111 of 4 bits respectively, i.e., a code 00001111 of 8 bits. Then the first half code 00001 of the FSC consists of the head bits of both codes 0000 and 1111 and is disposed at the head of the frame information. The remainder codes 111 are defined as the latter half code of the FSC and scattered with every bit between the digital data at nearly even intervals. A frame synchronization detecting circuit collates the received signal with the FSC which is previously set in a data register 1 via a shift register 2, an EXOR 3, an inverter 5 and AND gate 5 to detect the timing where the FSC is acquired as a correct code. Thus a correct frame synchronizing position can be detected at the receiver side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization communication method for transmitting and receiving frame information consisting of digital data and a frame synchronization code in series at a predetermined speed using one line.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing an example of a frame format of a conventional frame synchronous communication method, showing an example of a general frame format for transmitting digital data serially using one conventional line. ing. In FIG. 4, part A is a period in which a code for frame synchronization is inserted, and part B is a period in which digital data is inserted. A specific pattern code is used as the code for frame synchronization in FIG. The receiving side has a function of detecting this specific pattern code, and when this code is detected, it is determined to be the beginning of one frame, and the next data is sequentially read. However, in this method, when the content of the data matches the specific pattern code for frame synchronization, it is mistaken as a frame synchronization signal, and therefore the following method is usually adopted.

As a first method, the content of the data is restricted in advance so that the content of the data does not match the code for frame synchronization, or the content is changed to another content. As a second method, since the code for frame synchronization has a periodicity, it is judged whether or not the specific pattern code for frame synchronization has arrived at the same time of each frame, and if the time is shifted, the frame It has a function to judge that it is not a code for synchronization. In this way, it is possible to receive a signal synchronized with the signal on the transmitting side.

[0004]

However, in the first method of the above-mentioned methods, it is not versatile to limit the data so that the input data does not match the code for frame synchronization. There was a problem that an extra circuit was needed to change the contents of. Also the second
In the above method, if the input data is data that changes randomly for each frame, but if the input data is fixed and is the same as the specific pattern code for frame synchronization, it is used for frame synchronization at the same time for each frame. Since the same data as the above code comes, the circuit that determines the frame synchronization code from the periodicity of the frame synchronization code malfunctions.

[0005]

A frame synchronization communication method according to the present invention is a frame synchronization communication method for transmitting and receiving frame information consisting of digital data and a frame synchronization code in series at a predetermined speed. Is composed of a first half code and a second half code, the first half code of the frame synchronization code is arranged at the beginning of the frame information, and then digital data is arranged respectively, and the latter half code of the frame synchronization code is arranged. By arranging one bit or a plurality of bits at a substantially even interval between the arranged digital data and arranging the frame information, it is possible to detect the correct frame synchronization position on the receiving side. is there.

[0006]

According to the present invention, in a frame synchronization communication method for transmitting and receiving frame information consisting of digital data and a frame synchronization code in series at a predetermined speed, the frame synchronization code is composed of a first half code and a second half code. Then, the first half code of the frame synchronization code and then the digital data are respectively arranged at the head of the frame information, and the latter half code of the frame synchronization code is arranged by 1 bit or a plurality of bits. Since the frame information is configured by arranging the data at substantially equal intervals between the data, the frame synchronization code configured and arranged as described above is determined from the received information at all positions. The timing obtained as the correct code is detected as the correct frame synchronization position, and normal reception is possible.

[0007]

【Example】

Example 1. FIG. 1 shows a first frame synchronization communication method according to the present invention.
FIG. 4 is a diagram showing an example of the frame format of FIG. 1, one horizontal line in the upper part of the drawing shows a configuration example of frame information, and a matrix in the lower part of the drawing shows an example of synchronization deviation of frame information on the receiving side. First, the configuration and arrangement of the frame synchronization code in the first embodiment will be described. The code for frame synchronization in this example has a total of 8 bits including a first code 0000 of 4 bits of consecutive 0s and a second code 1111 of 4 bits of consecutive 1s with opposite signs to the first code. Of 00001111. Further, the data is 25 bits, and the frame information is 33 bits in total.

Next, the first code 0000 and the leading 1-bit 1 of the second code form a first half code 00001 of the frame synchronization code, which is placed at the beginning of the frame information, and thereafter. The digital data was placed in. Next, a code 1 obtained by removing the leading 1 bit from the second code
11 designates the latter half of the frame synchronization code, and the latter half of the code is dispersed bit by bit at substantially equal intervals (in this example, every 7 bits of digital data) between the arranged digital data. I placed it. An example of the frame information configured in this way is shown in a horizontal row in the upper part of FIG. 1, in which the code for frame synchronization is arranged at the position indicated by 0 or 1, and the data is indicated by *. It is located in a position.

In the matrix at the bottom of FIG. 1,
Vertical position No. In the horizontal frame information of 1, all the bit information matches the one frame information shown separately in the upper part, which indicates the correct state in which the received signals are synchronized. And the vertical position No. 2 to No. Three
As for each horizontal frame information up to 3, the information of one frame is shifted to the right one bit by one bit in sequence (that is, the synchronization is deviated) and shows an incorrect state.

Here, No. No. 1 frame information in synchronization with No. 1 frame information. 2 to No. When comparing up to 33 pieces of out-of-sync frame information one bit at a time, it shows that in-frames out of sync with information (0 or 1) at any position of the in-sync frame synchronization code Even if there is a part where the information (0 or 1) matches,
As indicated by the thick frame in the figure, No. Any one bit of the frame synchronization code with which the synchronization of 1 is matched always becomes inconsistent with the other information in the frame where the synchronization is deviated.
Due to this 1-bit mismatch, No. 2 to No.
It can be seen that the 33 pieces of frame information are all out of synchronization. Therefore, if the frame synchronization code is constructed and arranged as shown in FIG. 1, no matter what information the transmitted * mark data has, the information at each position of the frame synchronization code is received on the receiving side. If all the timings that are obtained as correct information are detected, normal reception can be performed without erroneous frame synchronization positions.

FIG. 2 is a diagram showing an example of the frame synchronization signal detection circuit of the present invention. In FIG. 2, 1 is a data register, and in this example, 8 in one frame of FIG.
The bit frame synchronization code 00001111 is set in the random register. Reference numeral 2 denotes a 33-bit shift register, which receives a received signal from the input end, holds information for one frame, and then outputs the information from the output end.
Reference numeral 3 is an exclusive OR gate (hereinafter referred to as EXOR), which outputs 0 when two input signals are equal and outputs 1 when the input signals are not equal. Reference numeral 4 is an inverter, which inverts 1 and 0 of the input signal and outputs the inverted signal. 5 is AN
It is a D gate, and its output becomes 1 when all eight input signals are 1.

In the circuit of FIG. 2, frame format information including the frame sync code and data of FIG. 1 is transmitted, and the reception side shifts this received signal.
Input from the input end of. And 1 by the synchronous cook signal
The input information is shifted to the right bit by bit and output from the output end. In the above information shift process, in the case of the correct synchronization position, the information at the position where the frame synchronization code should exist in the shift register 2 (the position shown by hatching in FIG. 2) and the data register 1 are set. The timing at which all the generated synchronization codes match is detected.

That is, when all the two input signals input to the eight EXOR3 are equal, the outputs of the EXOR3 are all 0, and the outputs of the eight inverters 4 are all 1.
And the output of the AND gate 5 also becomes 1. The output of the AND gate 5 is used as the sync detection signal. Therefore, by using the circuit of FIG. 2, a correct frame synchronization position can be detected and normal reception can be performed.

Example 2. In the first frame format example of FIG. 1, by chance noise or the like is mixed in the line, the content of the frame synchronization code is changed by 1 bit out of 8 bits, and data is accidentally changed by another bit. If it is the same as the frame synchronization code, it may be mistaken for a frame synchronization signal. FIG. 3 is a diagram showing a second frame format example of the frame synchronous communication method of the present invention. In order to further reduce the possibility of being mistaken as a synchronization code due to noise mixing in the frame format example of FIG. The example of the frame format which increased the bit number of the code for frame synchronization is shown.

First, the structure and arrangement of the frame synchronization code in the second embodiment will be described. The code for frame synchronization in this example is the first consecutive 6-bit 0s.
And the second code 111111 in which 6 is the first code and the opposite code is 1 in sequence, and a total of 12 bits is 00000011111. Further, the data is 25 bits, and a total of 37 bits of frame information is used. Next, the first code 000000 and the first 1 bit 1 of the second code form a first half code 0000001 of the frame synchronization code, which is placed at the head of the frame information, and then digitally. Arranged the data.

Next, a code 11111 obtained by removing the leading 1 bit from the second code is used as a latter half code of the frame synchronization code, and the latter half code is almost 1 bit at a time between the arranged digital data. The data are arranged at even intervals (in this example, every 5 bits of digital data). An example of frame information configured in this way is shown in FIG.
Are shown in a horizontal row at the top of the frame, where the code for frame synchronization is placed at the position indicated by 0 or 1, and the data is *
It is arranged at the position indicated by the mark.

In the matrix at the bottom of FIG. In the horizontal frame information of 1, all the bit information matches the one frame information shown separately in the upper part, which indicates the correct state in which the received signals are synchronized. And the vertical position No. 2 to No. 37
In the horizontal frame information up to, the information of one frame is shifted to the right by 1 bit (that is, the synchronization is shifted),
Indicates an incorrect state.

Here, No. No. 1 frame information in synchronization with No. 1 frame information. 2 to No. Comparing the frame information up to 37 with the out-of-sync frame by bit, the information (0 or 1) at any position of the in-frame sync code is out of sync with the frame information. Even if there is a part where the information (0 or 1) matches,
As indicated by the thick frame in the figure, No. One of the two bits of the frame synchronization code that is in synchronization with 1 is always inconsistent with the other information in the frame that is out of synchronization.
Then, due to the mismatch of any one of these bits, No. Two
-No. It can be seen that all the 37 frame information is out of synchronization. That is, on the receiving side, at the time of receiving the frame information, the probability that the 2-bit information at the specific position of the frame synchronization code is simultaneously received in one frame is extremely low. Therefore, even if one bit of the frame synchronization code is erroneously received, if the remaining one bit is correctly received, the synchronization shift is detected due to the mismatch of the one bit.

Therefore, no matter what kind of information the * -marked data transmitted when the frame synchronization code is constructed and arranged as shown in FIG. 3, at the receiving side at each position of the frame synchronization code. If the timing at which all information is obtained as correct information is detected, normal reception can be performed without erroneous frame synchronization positions, and a highly reliable frame synchronization communication method can be realized. Further, in a communication line having a poor line quality such that normally two bits are erroneous in one frame, the data itself is erroneous, so that the present invention is hardly applied.

Even if a code 11110000 in which 1 and 0 are inverted is used instead of the frame synchronization code 00001111 in the first embodiment, an inversion code 111111000000 is similarly used instead of the frame synchronization code 000000111111 in the second embodiment. When used, it works exactly the same. The number of bits of the frame synchronization code in the first and second embodiments is 8 bits and 12 bits, both of which are even numbers, but the present invention is not limited to this, and any number of bits, even or odd numbers, can be used. Good.

In the first and second embodiments, the latter half of the frame synchronization codes 111 and 11111 are distributed by one bit so that the digital data is distributed every 7 bits and at equal intervals of 5 bits. Although shown, the invention is not so limited. For example, if the number of bits of the latter half of the code is sufficient, a plurality of bits may be dispersed and arranged. However, increasing the number of bits of the frame synchronization code improves the reliability of the synchronization position detection, but also has the disadvantage of decreasing the number of bits of the data in the frame, so the number of bits of the data in the frame The number of bits of the efficient frame synchronization code may be set according to the above.

Depending on the number of bits of digital data in one frame, the latter half of the frame synchronization code may be
In some cases, it may not be possible to disperse the digital data such that the predetermined bits of digital data are evenly spaced. For example, digital data 7
When the bits are distributed and arranged at intervals of each bit, the end may be 6 bits or 5 bits. Therefore, the intervals are not necessarily equal, and it is sufficient that the intervals are substantially equal.

[0023]

As described above, according to the present invention, in the frame synchronization communication method for transmitting and receiving the frame information composed of the digital data and the frame synchronization code serially at a predetermined speed, the frame synchronization code is the first half code. And the latter half code, the first half code of the frame synchronization code is arranged at the beginning of the frame information, and the digital data is arranged next to the first half code, and the latter half code of the frame synchronization code is 1 bit or more. Since the frame information is configured by arranging the bits at a substantially even interval between the digital data arranged, the frame synchronization code configured and arranged as described above from the received information. However, by detecting the timing that is obtained as the correct code at all the arrangement positions, the correct frame synchronization position on the receiving side is detected. Detection is possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a first frame format example of a frame synchronous communication method of the present invention.

FIG. 2 is a diagram showing an example of a frame synchronization signal detection circuit of the present invention.

FIG. 3 is a diagram showing a second frame format example of the frame synchronous communication method of the present invention.

FIG. 4 is a diagram showing an example of a frame format of a conventional frame synchronous communication method.

[Explanation of symbols]

 1 Data Register 2 Shift Register 3 EXOR 4 Inverter 5 AND Gate

Claims (4)

[Claims] 1. A frame synchronization communication method for serially transmitting and receiving frame information composed of digital data and a frame synchronization code at a predetermined speed, wherein the frame synchronization code is composed of a first half code and a second half code, The first half code of the frame synchronization code is arranged at the beginning of the frame information, and the digital data is arranged next to the first half code, and the latter half code of the frame synchronization code is arranged by 1 bit or a plurality of bits between the arranged digital data. A frame synchronization communication method, wherein the frame information is arranged at substantially equal intervals and the frame information is configured so that a correct frame synchronization position can be detected on the receiving side. 2. The frame synchronization code comprises a first code of 0 or 1 having an arbitrary number of bits and a second code of 1 or 0 having a code opposite to the first code by an arbitrary number of bits. The first half bit of the frame synchronization code is formed by the first code and the first 1 bit of the second code, and the first 1 bit is removed from the second code. 2. The frame synchronization communication method according to claim 1, wherein the code configures the latter half of the frame synchronization code. 3. The frame synchronization communication method according to claim 1, wherein the first half code of the frame synchronization code is 00001 or 11110 and the second half code is 111 or 000. 4. The first half code of the frame synchronization code is 0
000001 or 1111110, and the latter half code is 1
The frame synchronous communication method according to claim 1, wherein the frame synchronous communication method is 1111 or 00000.