JPH0879229A - Synchronous data transmission system - Google Patents

Abstract

PURPOSE: To provide a synchronous data transmission system for eliminating the need of a synchronizing character by an intrinsic code such as an ASCII code or the like and improving transmission efficiency. CONSTITUTION: A transmission side is provided with an ASK modulation part 1 for setting carrier signals 512 for carrying data signals S11, switching a modulation output level corresponding to the presence/absence of the bit pulse of the data signals S11 by ASK modulation and turning off the carrier signals S12 except for a data signal period. In the meantime, a reception side is provided with an ASK demodulation part 2 for receiving transmission signals S14 on a transmission line, discriminating the OFF period of the signals from a received pulse level, taking out DET signals S15 and discriminating, taking out and outputting the data signals S16 and the carrier signals S17, a data end detection part 3 for detecting the OFF period of the signals by the DET signals S15 and outputting reset pulses S18 and a data processing part 4 for preparing data output SN by the reset pulses S18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous data transmission system which includes a transmission side and a reception side, and the reception side demodulates the transmission signal by word-synchronizing the transmission signal from the transmission side. , A synchronous data transmission method capable of improving the data transmission efficiency by reducing the ratio of synchronization bits to data bits.

[0002]

2. Description of the Related Art Conventionally, in this type of synchronous data transmission system, as shown in FIG.
It is composed of a sync part composed of a number of sync characters and a data part composed of b data characters.
A character consists of one word of 8 bits.

On the receiving side receiving such a message, a sync signal is generated by detecting a sync character, and word synchronization is established. By establishing the word synchronization, it is possible to match the timings of the following data parts and correctly receive the data character. As the character, a sync character and a data character defined by the ASCII code are generally used.

Next, a conventional synchronization method will be described with reference to FIG.

FIG. 4 (A) shows the receiving side of the transmission line, and the receiving side is, as shown in FIG. 4 (A),
It is composed of a demodulation circuit 101, a word synchronization circuit 104, and a data output circuit 106, detects data from an input signal received from a transmission line, and outputs it as a data output 107.

The input signal (that is, the data input) transmitted on the transmission path includes the modulation signal modulated by the data signal together with the clock signal on the transmission side. In the demodulation circuit 101, a clock (hereinafter referred to as CLK) signal 10 is generated from the modulated signal received from the transmission line as a data input.
2 and the data signal 103 are demodulated and separated, and output to the word synchronization circuit 104 and the data output circuit 106. The word synchronization circuit 104 uses the CLK signal 102 and the data signal 1
03, the sync character in the data signal 103 is detected.

Further, in the word synchronization circuit 104, a synchronization signal 105 is formed from the detected synchronization character and is output to the data output circuit 106 to establish word synchronization.

The data output circuit 106 has a CLK signal 1
When 02, the data signal 103, and the synchronization signal 105 are input and synchronization is accurately established by detecting the correct synchronization character, an accurate data output can be output from the accurate data character. CLK signal 102, data signal 1
03 and an example of the synchronization signal 105 are shown in FIG.

When the word synchronization circuit 104 detects a synchronization character, the detection operation does not always start from the beginning of the message. Therefore, a signal having the same pattern as the synchronization character is erroneously placed at a position different from the synchronization character. May be detected. When the sync character is erroneously detected at different positions in this way, the beginning of the word is erroneously detected from the sync signal 105 at the erroneous position. For this reason, while causing bit shift,
A data character is received and, as a result, an incorrect data character is received.

In order to prevent this malfunction, when at least two consecutive sync characters are not detected, this sync is invalidated and the sync characters are detected again. That is, as shown in FIG. 4, the synchronization establishing operation is performed only when at least two consecutive synchronization signals 105 are detected.

Therefore, on the transmitting side, a synchronization characters are arranged at the beginning of the message so that the receiving side can accurately detect the data character. In the well-known method using the ASCII code, it is recommended to provide five or more sync characters at the beginning of the message in order to detect sync with less error.

Further, when a large number of data characters are consecutive, the probability of data error is inevitable.
As a result, since it is necessary to retransmit a large number of data characters, there is a problem that not only a data transfer delay occurs but also the load on the transmission line is doubled. Therefore, the number of characters in the data section is limited.

Under this condition, when the transmission efficiency is calculated when one message is (5 + 64 =) 69 words composed of 5 words (40 bits) for the synchronization section and 64 words (512 bits) for the data section, ASCII is calculated. In the code,
Since 7 bits in 1 word are used as 1 data character, the transmission efficiency is (7 × 64 × 100/8 ×
69 =) 81.2% is calculated.

[0014]

In the conventional synchronous data transmission system described above, a plurality of synchronization characters are provided at the beginning of the message and before the data character so that the synchronization character on the receiving side can be reliably detected. By doing so, word synchronization can be accurately established. As described above, in order to accurately establish synchronization, it is necessary to arrange a plurality of synchronization characters, and the ASCII code requires at least five 8-bit synchronization characters, that is, 40 bits or more for synchronization. .

In this configuration, there is a problem in that 40 or more sync characters with respect to the number of bits of the data character deteriorate the data transmission efficiency. Furthermore,
There is a problem that codes other than ASCII code cannot be set.

An object of the present invention is to provide a synchronization bit period irrelevant to the ASCII code and reduce the number of synchronization bits to shorten the length of one message transmitted on the transmission path. An object of the present invention is to provide a synchronous data transmission method capable of improving the transmission efficiency of data on the road.

[0017]

A synchronous data transmission system according to the present invention comprises a transmission side and a reception side, and the reception side obtains word synchronization of a transmission signal from the transmission side.
In the synchronous data transmission method for demodulating a transmission signal, the transmitting side has guard bits (n and m are positive integers) which are n data bits and m synchronization bits.
And a second means for transmitting a signal containing the data bit in the one word and suppressing the guard bit in the one word as the transmission signal. The second means modulates the data bit in the one word by turning on the carrier signal during the data bit period and turns off the carrier signal during the guard bit period. , A modulation means for suppressing the guard bit and obtaining the transmission signal. Further, the modulating means includes carrier signal generating means for generating a carrier signal having a repetition frequency of k times data bits (k is a positive integer), and ASK modulating means for ASK modulating the carrier signal with the data bits. Have

On the other hand, the receiving side detects ON / OFF of the carrier signal from the received transmission signal by a predetermined first threshold value, separates the ON / OFF state of the carrier signal, identifies and outputs a period of 1 word, and outputs the word. A demodulation means for distinguishing and separating the data bit and the carrier signal from the received transmission signal by a predetermined second threshold value during the ON period of the carrier signal, and separating and outputting the carrier signal;
In addition, a data signal is reproduced and output by a reset pulse for detecting the start of turning off of the carrier signal and outputting it, a data bit output from the demodulating means, and a carrier signal having a repetition frequency of K times the data bit. It has data processing means.

[0019]

Next, the present invention will be described with reference to the drawings.

First, the pulse train on the transmission path used in the present invention will be described with reference to FIG. As shown in the figure, a synchronization character is not provided for each message, n data bits and m guard bits are provided in one word, and the guard bit period is used for synchronization. It is different from 3. For example, the data signal S1
A carrier signal S12 having a repetition frequency of k times 1 (k is an integer of 2 or more) is used, and a 1-bit synchronization signal is added as a guard bit to an 8-bit data signal to form 1 word. I shall. In this case, since the carrier signal has a repetition frequency of k times, 8k data bits are assigned to the data signal and k guard bits are assigned to the synchronizing signal.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. A synchronous data transmission system according to the present invention will be described with reference to FIGS.

In the synchronous data transmission system shown in FIG. 1, the ASK modulator 1 is provided on the transmitting side and the ASK is provided on the receiving side.
K demodulator 2, data end detector 3, and data processor 4
Is provided. The ASK demodulation unit 2 includes a DET (carrier on / off) signal detection circuit 11, a data signal detection circuit 12,
And a carrier signal detection circuit 13. The data end detection unit 3 includes a data end detection circuit 14 and an oscillator 15. The data processing unit 4 includes an SC (shift clock) generation counter 16, an n-bit shift register 17, and an LP.
A (latch pulse) generation counter 18 and an F / F (flip-flop) circuit 19 are provided.

The ASK modulator 1 on the transmission side uses the data signal S11 having one word consisting of the n-bit data bit and the m-bit guard bit to ASK the carrier signal S12.
(Amplitude deviation) Modulate. Is the data signal S11 "0"?
It is a digital binary signal of "1". Carrier signal S12
Is k times the transmission speed of the data signal S11 (k is a positive integer)
It has a repetition frequency of and is synchronized with the data signal. When the DET signal S13 is on, AS
The transmission signal S14 that has been ASK-modulated is transmitted from the K modulator 1, and when it is off, the transmission of the transmission signal is stopped. The waveform of each signal in this case is shown in FIG.

The DET detection circuit 11 receives and detects the transmission signal S14, integrates it, and then detects the level at a threshold value set for detecting the DET signal. DET indicating whether it is 1 ”or“ 0 ”
The signal S15 is sent to the data end detector 3. The data signal detection circuit 12 receives and detects the transmission signal S14, integrates it, and then performs level detection at a threshold value set for data signal detection, and then receives the received data signal S16.
Send to. The carrier signal detection circuit 13 uses the transmission signal S14.
The received signal is received and detected, the carrier signal is reproduced in the level existence period as the data bit existence period, and sent to the data processing unit 4.

In the data end detection circuit 14, the DET signal S15 received from the DET detection circuit 11 is reset by the clock signal S19 received from the oscillator 15 to the reset pulse S.
18 is generated and sent to the data processing unit 4. CL
The frequency of the K signal S19 is assumed to be sufficiently higher than the frequency of the data signal S11. By setting such a frequency relationship, the reset pulse S18 is a guard that fills the gap between the end of the data bits and the appearance of the first bit of the data bits of the next word, that is, the gap between the data bits. It is sent during the bit period.

SC (shift clock) generation counter 16
Then, the carrier signal S17 from the carrier signal detection circuit 13 is input to the CLK terminal, the carrier signal S17 is divided by the speed ratio k with the data signal S16, and the bit-synchronized shift clock (SC) signal S20 is generated. It RS
The reset pulse S18 from the data end detection circuit 14 is input to the (reset) terminal at the start of the guard bit period, and the count value of the SC generation counter 16 is initialized.
In the n-bit shift register 17, the data signal S16 from the data signal detection circuit 12 is input to the DATA terminal, and the data signal S16 is shifted bit by bit by the shift clock signal S20 input from the SC generation counter 16 to the CLK terminal. And is output as a shift data signal Sn.

In the LP (latch pulse) generation counter 18, the carrier signal S17 from the carrier signal detection circuit 13 is input to the CLK terminal, the CLK pulse by the carrier signal S17 is counted up to a predetermined value, and the data latch pulse S
21 is generated. That is, the data latch pulse S21 is generated at the time when the last data in one word is input, as shown in FIG. The reset pulse S18 from the data end detection circuit 14 input to the RS terminal initializes the count value of the CLK pulse by the carrier signal S17. F / F (flip-flop) circuit 19
Then, n shift data signals Sn are input from the n-bit shift register 17, and the n shift data signals Sn are latched by the data latch pulse S21 from the LP generation counter 18 and output as output data SN. .

Here, when the data bit n = 8 and the guard bit m = 1 are set, the transmission efficiency is n / n.
+ M, which is 88.9%. On the other hand, according to the conventional method, as described above, the transmission efficiency is 81.2%, and a great improvement can be expected.

In the above description, a guard bit period is provided for each word and is used as a synchronizing signal, but a guard bit may be provided for each word.

That is, although the functional blocks and the signal waveforms have been shown and described in the above embodiments, the functions can be freely divided and merged, and the above functions limit the present invention. Not a thing.

[0031]

As described above, according to the present invention, a carrier signal is ASK-modulated by a data signal, and a guard bit period of carrier signal off is provided as a synchronizing signal on a transmission line in a synchronization detecting portion. Has been transferred.

With this configuration, a synchronization character by a unique code such as an ASCII code is not necessary, the guard bit period can be detected in a short time, and the data bit period is longer than the guard bit period. , It is possible to obtain a synchronous data transmission method whose transmission efficiency is further improved.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of signals in FIG.

FIG. 3 is a bit configuration diagram showing an example of a conventional message.

FIG. 4 is a block diagram (A) and a waveform diagram (B) showing a conventional example.

[Explanation of symbols]

 1 ASK (amplitude shift) modulator 2 ASK demodulator 3 data end detector 4 data processor 11 DET signal detector 12 data signal detector 13 carrier signal detector 14 data tail detector 15 oscillator 16 SC (shift clock) Generation counter 17 n-bit shift register 18 LP (latch pulse) generation counter 19 F / F (flip-flop) circuit S11, S16 data signal S12, S17 carrier signal S13, S15 DET (carrier on / off) signal S14 transmission signal S18 reset pulse S19 clock signal S20 shift clock signal S21 data latch pulse Sn shift data signal SN output data

Claims (6)

[Claims] 1. A transmission side and a reception side are provided, and the reception side obtains word synchronization of a transmission signal from the transmission side,
In the synchronous data transmission system for demodulating a transmission signal, the transmission side forms first words by n data bits and m guard bits (where n and m are positive integers), and a first means. And a second means for transmitting, as the transmission signal, a signal including the data bit in the one word and suppressing the guard bit in the one word. 2. The method according to claim 1, wherein the second means modulates the data bits in the one word by turning on a carrier signal during the data bits.
A synchronous data transmission system comprising a modulation means for suppressing the guard bit and turning off the carrier signal during the guard bit period to obtain the transmission signal. 3. The carrier signal generating means according to claim 2, wherein the modulating means generates a carrier signal having a repetition frequency of k times the data bit (k is a positive integer), and the carrier signal is ASK by the data bit. A synchronous data transmission system, comprising: an ASK modulation means for modulating. 4. A transmission side and a reception side are provided, and the reception side obtains word synchronization of a transmission signal from the transmission side,
In the synchronous data transmission method for demodulating a transmission signal, the receiving side detects on / off of a carrier signal from a received transmission signal according to a predetermined first threshold value, separates it from the received transmission signal, and
Demodulating means for identifying and outputting the word period, and for identifying and separating the data bit and the carrier signal from the received transmission signal by a predetermined second threshold value during the ON period of the carrier signal, separating and extracting the data bit and the carrier signal. A synchronous data transmission method characterized by having. 5. The demodulating means according to claim 4, wherein the data bit and the carrier signal are discriminated and separated from each other by a predetermined threshold from the pulse level included in the received transmission signal during the ON period of the carrier signal. A synchronous data transmission system, characterized in that it is an ASK demodulation means for taking out and outputting. 6. A reset pulse for detecting and outputting an off period of the carrier signal, a data bit output from the demodulating means, and K of this data bit according to claim 4.
A synchronous data transmission system comprising a data processing means for reproducing and outputting a data signal with a carrier signal having a double repetition frequency.