JPH0812989B2 - Time constant circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a time constant circuit composed of a resistor and a capacitor, and more particularly to a time constant circuit that is reset at high speed when the power is turned off.

[Conventional technology]

Conventionally, most of the time constant circuits of this type are constituted by a resistor and a capacitor and do not have the high-speed reset function. Although a device having a high-speed reset function has been proposed, it has a configuration that operates only when a circuit is connected, that is, when the power is turned on.

[Problems to be Solved by the Invention]

Even if the conventional time constant circuit described above has a high-speed reset function, it operates only when the power is turned on. Therefore, if there is a power interruption, for example, reset only after the interruption. The function will be activated. For this reason, it is difficult to sufficiently discharge the capacitor charge of the time constant circuit not only during this momentary interruption but also by the reset function at the time of momentary interruption, and therefore the delay time error due to the time constant circuit after the momentary interruption becomes large. There is a problem.

An object of the present invention is to provide a time constant circuit that can make the delay time due to the time constant accurate even when the power supply is momentarily cut off.

[Means for solving the problem]

In the time constant circuit of the present invention, the forced reset input terminal is connected to the base, and the first and second voltage dividers divide the voltage of the power supply.
Voltage dividing resistors are respectively connected between the base and the power source and ground, a time constant output terminal is connected to the emitter through a diode, and a resistor and a capacitor for setting a time constant are respectively output from the time constant output. A time constant circuit comprising a transistor connected between a terminal and a power supply or ground, wherein the transistor is turned on when a forced reset signal is input or when the power is turned off to short-circuit the capacitor; A third and a fourth voltage dividing resistor for dividing the voltage of the power source are connected to the emitter of each of the emitter and the power source and the ground, respectively, and a resistor is connected between the collector of the transistor and the ground. The resistance connected to the collector is set to be lower than the resistance for setting the time constant and the fourth voltage dividing resistance. And wherein the Rukoto.

[Action]

In the above-described configuration, the transistors are turned on when the forced reset signal is input or the power is turned off to short-circuit the capacitor, and the capacitor is discharged at high speed to reset the time constant circuit.

Also, by connecting a resistor between the power supply and ground to the emitter of the transistor, reverse bias between the base and emitter of the transistor is prevented when the capacitor is not charged and the voltage of the time constant output terminal is low. To prevent damage. Further, by connecting a low resistance resistor to the collector of the transistor, the discharge current of the capacitor is suppressed below the standard value of the transistor to prevent the characteristic deterioration and damage of the transistor.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of the first embodiment of the present invention. In the figure, 1 is a forced reset input terminal, to which a forced reset signal is input. Further, the transistor Q ₁ , the diode CR ₁ , the resistors R ₁ , R ₂ , R ₃ , R ₄ , R ₅ , and R ₆ constitute a power-off detection and high-speed discharge circuit, while the resistor R ₇ and the capacitor C ₁ are A constant circuit is configured and an output corresponding to the time constant τ = C ₁ R ₇ is output from the time constant output terminal 2.

That is, the transistor Q ₁ is configured to be turned on and off by a reset input input to the base by applying a bias voltage to the base and the emitter by the bias resistors R ₂ , R ₃ , R ₅ , and R ₆ , respectively. Further, a resistor R ₄ having an extremely low resistance value is connected to the collector of the transistor Q ₁ . The connection point between the resistor R ₇ and the capacitor C ₁ forming the time constant circuit is connected to the emitter via the diode CR ₁ .

Here, the values of the resistors R ₂ and R ₃ are selected so that the transistor Q ₁ is turned off when the power supply V _DD is on. Also the resistance R
The values of ₅ and R ₆ are set so that the base-emitter bias voltage of the transistor Q ₁ does not exceed a certain value. This prevents the reverse bias of the power source V _{DD from} being applied between the base and emitter of the transistor Q ₁ at worst when the potential across the capacitor C ₁ is low.

Next, the operation of this circuit will be described. After the power is turned on, when the forced reset signal is at high level, the transistor Q ₁ is turned off, so the voltage V _{1 at} the intersection of the resistors R ₅ and R ₆ is the power supply voltage.
A value obtained by dividing V _DD by resistors R ₅ and R ₆ (approximately transistor Q ₁
Value that is equal to the base voltage of V _DD, that is, a value approximately equal to the power supply voltage V _DD ). Therefore, the output voltage of the time constant output terminal 2 rises at the time constant τ = C ₁ R ₇ at the same time when the power is turned on, and becomes constant at a value obtained by subtracting the junction voltage of the diode CR ₁ from the voltage V ₁ . Diode CR ₁ has a time constant C ₁ R ₇
It is inserted so that the influence of the resistor R ₅ does not come out.

On the other hand, when the forced reset signal goes low, the transistor Q ₁ turns on. Set the value of resistor R ₄ to R ₄ << R ₆ and
If it is set so that R ₄ << R ₇ , then capacitor C ₁
The electric charge charged at is discharged at high speed via CR ₁ → Q ₁ → R ₄ and with the time constant C ₁ R ₄ , and the time constant circuit is reset.

Now, after the power-on, the forced reset signal is powered off when the high level, the resistor R _2, the current flowing in R ₅ may become zero, the base of the transistor Q _1, the emitter voltage is equal. Therefore, the transistor Q ₁ is turned on, and as a result, the charge accumulated in the capacitor C ₁ is transferred via CR ₁ → Q ₁ → R ₄ as in the case where the forced reset signal is low level.
And it is discharged at high speed with time constant C ₁ R ₄ . As a result, the reset of the time constant circuit is completed.

FIG. 2 shows a second embodiment of the present invention, and the same parts as those in FIG. 1 are designated by the same reference numerals.

In this embodiment, the resistance-divided voltage created by the resistors R ₅ and R ₆ is used to prevent the base-emitter reverse bias of the transistor Q ₁ , and a constant voltage V ₁ is created by the resistor R ₅ and the Zener diode CR ₂ . This is applied to the emitter of the transistor Q ₁ . The Zener voltage V ₁ of the Zener diode CR ₂ is set to such a value that the base-emitter bias of the transistor Q ₁ is within an allowable range and does not significantly affect the time constant circuit (that is, a value close to the power supply voltage V _DD ).

Also in this circuit, the same operation and effect as those of the circuit in FIG. 1 can be obtained.

〔The invention's effect〕

As described above, the present invention connects a transistor that is turned on at the time of inputting a forced reset signal or turning off the power supply to a time constant circuit, short-circuits the capacitor by the turning-on operation, and discharges the charge of the capacitor at high speed. Since the constant circuit is reset, there is an effect that the time constant circuit operates normally even when the power supply is interrupted.

Further, in the present invention, by connecting a resistor to the emitter of the transistor between the power supply and the ground, the reverse bias between the base and the emitter of the transistor when the capacitor is less charged and the voltage of the time constant output terminal is low is provided. It is possible to prevent the transistor from being damaged.

Further, in the present invention, by connecting a resistor having a lower resistance than the resistor connected between the emitter and the power supply between the collector of the transistor and the ground, the discharge current of the capacitor is suppressed to the standard value of the transistor or less. However, it is possible to prevent characteristic deterioration and damage of the transistor.

[Brief description of drawings]

FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIG. 2 is a circuit diagram of the second embodiment of the present invention. 1 …… Forced reset input terminal, 2 …… Time constant output terminal,
Q ₁ ...... Transistor, CR ₁ ...... Diode, CR ₂ ...... Zener diode, R ₁ ...... Input resistance, R ₂ , R ₃ , R ₅ ,, R ₆ ...... Bias resistance, R ₄ ...... Discharge resistance , R ₇ …… Time constant resistance, C ₁ …… Time constant resistance.

Claims (1)

[Claims] 1. A base is connected to a forced reset input terminal, and first and second voltage dividing resistors for dividing a voltage of a power supply are connected between the base and a power supply and ground, respectively, and a diode is connected to an emitter. A time constant output terminal is connected via a resistor, and a resistor and a capacitor for setting the time constant each include a transistor connected between the time constant output terminal and a power source or ground. In a time constant circuit configured to be turned on at the time of input or power off to short-circuit the capacitor, third and fourth voltage dividing resistors for dividing the voltage of the power source are respectively provided at the emitters of the transistors. A resistor is connected between the emitter and the power supply and ground, and the collector of the transistor is connected to the ground. The time constant circuit is connected resistors, characterized in that it is set to lower resistance than the resistor, and voltage dividing resistors of the fourth for the time constant set to.