JPH08125458A - Power amplifier circuit - Google Patents

Abstract

PURPOSE: To reduce a current of a power supply at no load by controlling emitter follower circuits connected in two-stages with a current obtained by a current mirror means. CONSTITUTION: As a share of transistors(TRs) being components of a differential amplifier means is selected that 9 TR pairs (11, 12) correspond to 1 TR pair (9, 11), then a collector current I3 of one unit of the TR pair (9, 11) corresponds to a collector current I2 of 9 units of the TR pair (10, 12). On the other hand, as a share of TRs being components of a current mirror means is selected that 10 TR pairs (15, 17) correspond to 1 TR pair (16, 18), then a collector current I3 of one unit of the TR pair (16, 18) corresponds to a collector current I4 of 10 units of the TR pair (15, 17). The emitter follower circuit is driven by the collector current I4 .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier circuit used in audio equipment and the like.

[0002]

2. Description of the Related Art A conventional power amplifier circuit will be described with reference to FIG.

In FIG. 2, 21 is a signal source for generating an AC voltage signal, 22 is an input terminal to which the signal source 21 is connected, 23 is a base connected to the input terminal 22 and a collector is connected to the negative power supply terminal. The pnp-type transistor 24 has a base connected to the input terminal 22 and a collector connected to the positive power supply terminal.
An npn-type transistor having a polarity opposite to that of the reference numeral 25 is an npn-type transistor whose base is connected to the emitter of the transistor 23 and whose collector is connected to the positive power supply terminal, and 26 is connected to the emitter of the transistor 24. A pnp-type transistor having a collector connected to the negative power supply terminal and having a polarity opposite to that of the transistor 25,
Reference numerals 27 and 28 denote constant current sources that obtain a predetermined operating current by supplying power from the positive power supply terminal + B and the negative power supply terminal -B. The output of the constant current source 27 is output to the emitter of the transistor 23 and the base of the transistor 25, The output of the constant current source 28 is output to the emitter of the transistor 24 and the base of the transistor 26. 28 is connected to the emitters of the transistors 25 and 26,
An output terminal having both emitter outputs as output signals, and 29 is a load driven by the output signal from the output terminal 28.

In the current amplifying circuit configured as described above, when the voltage signal from the signal source 21 input to the input terminal 22 is a positive voltage, the emitter follower output of the transistor 23 is based on that signal. The emitter follower of the transistor 25 is driven, and the amplified current flows into the load from the emitter of the driven transistor 25, while the signal source 21 input to the input terminal 22 is supplied.
When the voltage signal from is a negative voltage, the emitter follower output of the transistor 24 drives the emitter follower of the transistor 26 based on the signal, and the amplified current flows from the emitter of the driven transistor 26 to the load. It was like this.

[0005]

However, in the above-mentioned conventional circuit, the base current of the transistor 25 or the transistor 26 is one-hundredth of the current amplification factor hfe with respect to the maximum current I _0max flowing through the load. The current setting values of 28 and 28 must be equal to or more than this value (I _0max / hfe), and therefore the power supply current of the entire circuit without load is 3
× I _0max / hfe is the minimum required, for example, current amplification factor
When a transistor having a minimum value of hfe of 60 is used, the no-load power supply current is 0.05 × I _0max, and there is a problem that there are many losses.

An object of the present invention is to provide a current amplifier circuit capable of reducing the power supply current when there is no load.

[0007]

In order to achieve the above object, the invention according to claim 1 current-amplifies an input voltage signal by an emitter-follower circuit connected in two stages,
In a power amplification circuit that drives a load by the current-amplified signal, a differential amplification unit that changes a current ratio of two current outputs based on a voltage difference between input and output, and an output current of one of the differential amplification units. On the other hand, a current mirror means for obtaining a current having a constant ratio is provided, and the emitter-follower circuits connected in two stages are controlled by the current obtained by the current mirror means.

According to a second aspect of the present invention, the differential amplifying means and the current mirror means are constituted by transistors to form a first amplifying circuit, while the transistors of the differential amplifying means and the current mirror means are opposite to each other. A differential amplifying means and a current mirror means are newly formed by transistors having polarities to form a second amplifying circuit, and the first amplifying circuit and the second amplifying circuit are combined to form a complementary type.

[0009]

Therefore, according to the first aspect of the invention, when a voltage difference occurs between the input voltage and the output voltage due to an increase in the input signal or an increase in the load current, the differential amplifying means outputs the input / output signal. Two currents whose current ratios are changed by the voltage difference are output, and the current generated by the current mirror means increases on the basis of one of the output currents, while the input voltage and the input voltage decrease as the input signal decreases or the load current decreases. When a voltage difference occurs between the output voltage and the output voltage, the differential amplifier outputs two currents whose current ratio is changed by the voltage difference between the input and output, and the current generated by the current mirror means based on one of the output currents. Is reduced. By driving the emitter-follower circuit with the current generated by the current mirror means, a large load current can be made to flow when a load is connected, and a small load current can be obtained when there is no load and no signal. Can be drained.

According to the second aspect of the present invention, power amplification is performed by the first amplifier circuit when the polarity of the input signal is positive and by the second amplifier circuit when the polarity of the input signal is negative. Thus, the connected load can be driven regardless of the polarity of the input signal.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is an electric circuit diagram showing the configuration of a power amplifier circuit according to an embodiment of the present invention. In FIG. 1, 1 is a signal source for generating an AC voltage signal, 2 is an input terminal to which the signal source 1 is connected, 3 is a base connected to an input terminal 2 and a collector is connected to a negative power supply terminal -B. The pnp type transistors 4 and 4 have the bases connected to the input terminal 2 and the collector connected to the positive power supply terminal + B, and the npn type transistors 5 and 5 have the opposite polarity to the transistor 3. Npn in which the base is connected and the collector is connected to the positive power supply terminal + B
Type transistor, 6 is connected to the emitter of the transistor 4 and the collector is connected to the negative power supply terminal -B,
Further, it is a pnp type transistor having a polarity opposite to that of the transistor 5, and the transistor 3 and the transistor 5 and the transistor 4 and the transistor 6 form a two-stage connected emitter follower circuit.

Reference numeral 7 is connected to the emitters of the transistors 5 and 6, and outputs the outputs of both emitters as an output signal I.
An output terminal set to ₀ and a load 8 driven by an output signal from the output terminal 7.

Reference numeral 9 denotes an np whose base is connected to the input terminal 2.
An n-type transistor, 10 is a pnp-type transistor whose base is connected to the input terminal 2, 11 is a base to the output terminal 7, a collector is connected to the positive power supply terminal + B, and an emitter is connected to the emitter of the transistor 9 Transistor, 12 is base on output terminal 7, negative power supply terminal -B
Is a pnp-type transistor in which the collector is connected to the collector and the emitter of the transistor 10 is connected to the emitter.
And the transistor 12 constitute differential amplifying means.

Reference numerals 13 and 14 denote constant current sources for obtaining a predetermined operating current by supplying power from the positive power supply terminal + B and the negative power supply terminal -B. The output of the constant current source 13 is the transistor 1
0 and the emitter of the transistor 12, and the output of the constant current source 14 is the transistor 9 and the transistor 11.
Are output to the emitters of the above, and the respective operating currents I ₁ are determined.

Reference numeral 15 is a pnp type transistor in which the collector is connected to the emitter of the transistor 3 and the emitter is connected to the positive power supply terminal + B, and 16 is the transistor 4
The collector is connected to the emitter of and the negative power supply terminal −
Npn type transistor whose emitter is connected to B, 1
7 is a pnp type transistor in which the base is connected to the base of the transistor 15, the collector is connected to the collector of the transistor 9, and the emitter is connected to the positive power supply terminal + B. 18 is the base to the base of the transistor 16, the collector to the collector of the transistor 10, and the negative power supply. An npn-type transistor having an emitter connected to the terminal -B, connecting the bases of the transistors 15 and 17 to the collector of the transistor 17, and connecting the bases of the transistors 16 and 18 to the collector of the transistor 18. Respectively constitute current mirror means.

And, there are two two-stage emitters each.
A complementary power amplifying circuit is constructed by reversing the polarities of the transistors forming the follower circuit, the differential amplifying means and the current mirror means.

In addition, the transistors 9 and 11 are distributed as 1 as the distribution of the transistors constituting the differential amplifying means.
When the number of transistors is 11 and the number of transistors 12 is 9, the voltage difference between the input and output when there is no signal and when there is no load is “0”.
And the collector current I ₃ of the transistor 11 is "1", the differential amplifier means is configured so that the collector current I ₂ of the transistors 11 and 12 is "9", while the distribution of the transistors forming the current mirror means The transistor 15 and the transistor 17 as
When the number of transistors is 16 and the number of transistors is 18, the collector current I ₄ of the transistors 15 and 17 is “10” when the collector current I ₃ of the transistors 16 and 18 is “1”. It is configured to be.

In the power amplifier circuit configured as described above, the base currents of the transistors 5 and 6 are 1 / the current amplification factor hfe with respect to the maximum current I _0max flowing through the load, and therefore the value of I ₄ is obtained. Is this value (I _0max / hf
It must be at e) above, since the collector current I ₃ through the allocation of the transistors constituting the current mirror means is one-tenth of the collector current I _4, as the value of I ₃ is

[0020]

[Equation 1]

The above must be satisfied.

Since the voltage difference between the input and the output is large at the time of maximum current output, the collector currents of the transistors 9 and 10 and the transistors 11 and 12 constituting the differential amplifying means are I ₂ = 0 and I ₃ = I ₁ and therefore

[0023]

[Equation 2]

It becomes

On the other hand, the current of each part under no load is I ₂ = 0.
Since 9 × I ₁ , I ₃ = 0.1 × I ₁ , I ₄ = 10 × I ₃ = I ₁ , and the collector currents of the transistors 5 and 6 are almost equal to I ₄ , the entire circuit is unloaded. Power supply current is 0.5
× I _0max / hfe.

The current flowing through the load is the maximum current I
_{When 0max} or less, the collector currents of the transistors 9 and 11 and the transistors 10 and 12 which form the differential amplifying means are such that I ₂ is a value between 0 and 0.9 × I ₁ and I ₃ is I _1.
Since it represents the value of −I ₂ , I ₄ represents a value between I _{1 and} 10 × I ₁ , with the result that I ₄ varies continuously with the magnitude of the load current.

Therefore, the emitters connected in two stages by I ₄ which changes continuously with the magnitude of the load current.
By driving the follower circuit, when looking at the power supply current of the entire circuit, it is possible to flow a large load current while reducing the power supply current when there is no load or no signal.

[0028]

As described above, according to the first aspect of the invention, when a voltage difference occurs between the input voltage and the output voltage due to the increase of the input signal or the load current, the two-stage emitter The current for driving the follower circuit is increased, and the current for driving the two-stage emitter-follower circuit is decreased when a voltage difference occurs between the input voltage and the output voltage due to the decrease of the input signal or the decrease of the load current. As a result, a large load current can flow when a load is connected, and a small load current can flow when there is no load and no signal. It is possible to flow a large load current while reducing the power supply current, and it is possible to reduce the loss of the power supply current when there is no load.

According to the second aspect of the invention, power amplification is performed by the first amplifier circuit when the polarity of the input signal is positive, and by the second amplifier circuit when the polarity of the input signal is negative. As a result, the connected load can be driven regardless of the polarity of the input signal, and thus alternating current can be used as the signal source.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing a power amplifier circuit according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram showing a conventional power amplifier circuit.

[Explanation of symbols]

 1 signal source 2 input terminal 3, 4, 5, 6 transistor 7 output terminal 8 load 9, 10, 11, 12 transistor 13, 14 constant current source 15, 16, 17, 18 transistor

Claims (2)

[Claims] 1. A power amplifier circuit in which an input / output voltage signal is current-amplified by an emitter-follower circuit connected in two stages, and a load is driven by the current-amplified signal. The differential amplification means for varying the current ratio of the current output and the current mirror means for obtaining a current having a constant ratio to one output current of the differential amplification means are provided, and the current mirror means is provided. A power amplifier circuit, characterized in that the emitter-follower circuit connected in two stages is controlled by an electric current. 2. The differential amplifying means and the current mirror means are constituted by transistors to form a first amplifying circuit, while a transistor having a polarity opposite to that of the transistors of the differential amplifying means and the current mirror means is added. 2. The power amplifier circuit according to claim 1, wherein the differential amplifier means and the current mirror means are configured as a second amplifier circuit, and the first amplifier circuit and the second amplifier circuit are combined to form a complementary type. .