JPH0533563B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an amplifier, and more particularly to an amplifier that can accurately set an idling current and is suitable for integration into an integrated circuit (IC). (b) Conventional technology An amplifier capable of increasing the maximum output current and having a small idling current was disclosed in Japanese Patent Application Laid-open No. 1983-
It is disclosed in Publication No. 99808. The amplifier is
As shown in FIG. 2, first to fourth transistors 1 to 4 whose emitters are commonly connected,
and a first current mirror circuit 5 connected between the collectors of the third transistors 1 and 3; a second current mirror circuit 6 connected between the collectors of the second and fourth transistors 2 and 4; Second
a first output transistor 7 connected to the collector of the transistor 2; a second output transistor 8 whose base is connected to the collector of the third transistor 3; and a third current for inverting the collector current of the second output transistor 8. It consists of a mirror circuit 9 ,
The input signal applied to the input terminal 10 is differentially amplified by the first to fourth transistors 1 to 4, and is amplified by the first and second output transistors 7 and 8, and the amplified output signal is output to the first output. The current is supplied to the load 11 from the transistor 7 and the third current mirror circuit 9 in a push-pull relationship. Therefore, in FIG. 2, if the current flowing through the constant current transistor 12 connected to the common emitter of the first to fourth transistors 1 to 4 is _I0 , then the idling current flowing to the first output transistor 7 is approximately Since the idling current is I ₀ /2 and a stable and appropriate value can be obtained, crossover distortion can be reduced. (c) Problems to be solved by the invention However, in the case of the amplifier shown in Figure 2, the output transistor is composed of a PNP type transistor and the amplification factor is low, so the maximum output current must be sufficiently large. The disadvantage is that it cannot be done. For example, the maximum output current I _MAX of the first output transistor 7 can be expressed as I _MAX = I ₀ /2・h _FEP (1) (where h _FEP is the current amplification factor of the first output transistor 7) , the current amplification factor h of the PNP transistor h _FEP is the current amplification factor h of the NPN transistor h _FEP
Since it is small compared to , it is not possible to obtain a sufficiently large output current. In equation (1), if the current I ₀ flowing through the constant current transistor 12 is increased, the maximum output current can be increased, but this is not preferable because the idling current also increases. Furthermore, when the final stage output transistor is configured with a PNP type transistor, there is a drawback that the IC area becomes larger than when configured with an NPN type transistor. Since the allowable current per unit area of a PNP transistor is a fraction of that of an NPN transistor, if you want to obtain the same output current,
The area of a PNP transistor is several times that of an NPN transistor. (d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and uses a transistor between the first and second stages to take out output currents of opposite polarity obtained from the differential amplifier stages. , the first and second adjustment circuits are amplified by a push-pull connected output transistor and supplied to the load, and supply a current corresponding to the current taken out by one interstage transistor to the output point of the other interstage transistor. It is characterized by the placed points. (e) Effects According to the present invention, the circuit configuration is such that one of the output currents of opposite polarity obtained from the differential amplifier stage is adjusted by the other, so that the idling current can be suppressed to a small level, and Since the circuit configuration is such that an NPN transistor can be used as the final stage output transistor, the maximum output current can be increased. (F) Embodiment FIG. 1 shows an embodiment of the present invention. 1
3, first and second transistors 15 and 16 whose bases are commonly connected to the input terminal 14, and third and fourth transistors whose bases are commonly connected to the negative feedback point 17.
Transistors 18 and 19 and the first to fourth transistors
A differential amplifier circuit consisting of a constant current transistor 20 connected to a common emitter of transistors 15 to 19; 21 has an input terminal connected to the first transistor 1;
A first current mirror circuit 22 has an input terminal connected to the collector of the fourth transistor 19 and an output terminal connected to the collector of the second transistor 16. 23 is a first interstage transistor whose base is connected to the collector of the second transistor 16, and 24 is a first interstage transistor whose base is connected to the third transistor 18.
a second interstage transistor connected to the collector of
25 is a first output transistor whose base is connected to the collector of the first interstage transistor 23 and whose emitter is connected to the output midpoint 26; and 27 is a first output transistor whose base is connected to the collector of the first interstage transistor 23;
A second output transistor whose collector is connected to the output midpoint 26 is connected to the collector of the interstage transistor 24; and 28 is a transistor 2 whose base and emitter are commonly connected to the first interstage transistor 23.
9 and the input terminal are connected to the collector of the transistor 29,
a first adjustment circuit consisting of a third current mirror circuit 30 whose output end is connected to the collector of the second inter-stage transistor 24, and a transistor 31 whose base and emitter are commonly connected to the second inter-stage transistor 24; 32 and the input terminal are the transistor 3
2, and a fourth current mirror circuit 33 whose output ends are respectively connected to the collector of the first interstage transistor 23. First, the first and second output transistors 25 and 2
Let's consider the idling current flowing through 7. Now, the constant current transistor 20 of the differential amplifier circuit 13
If the current flowing through the transistors is I ₀ , the collector currents of the first to fourth transistors 15 to 19 are equal to I ₀ /4 in a no-signal state. In addition, transistors 21a and 21b of the first current mirror circuit 21
The collector current I _C1 of is I _C1 = I ₀ /4・1/1+2/h _FEP (2), and the base current of the second stage inter-stage transistor 24 and the base current of the transistor 32 of the second adjustment circuit 31 are If I _B1 is equal, then I _B1 = I ₀ /4·1/h _FEP +2 ...(3). Then, since the base current I _B1 is amplified by the second interstage transistor 24, the base current I B1 is amplified by the second interstage transistor 24.
The collector current I _C2 of the interstage transistor 24 is I _C2 =I ₀ /4·h _FEP /h _FEP +2 (4). Note that since the amplifier is configured symmetrically, the first interstage transistor 23 and the first adjustment circuit 2
The collector currents of the transistor 29 of No. 8 and the transistor 32 of the second adjustment circuit 31 are equal to the collector current of the second inter-stage transistor 24.
The value is given by the formula. The base current of the second output transistor 27 is a difference current between the collector current of the second interstage transistor 24 and the output current of the third current mirror circuit 30 ,
The output current of the third current mirror circuit 30 (collector current of the transistor 30a) I _C3 is as follows: I _C3 = I _C2 ·h _FEN /h _FEN +2 (5) Therefore, Equation (4) and Equation ( From equation 5), the base current I _B2 of the second output transistor 27 is: I _B2 = I _C2 − I _C3 = I ₀ /4·h _FEP /h _FEP +2·2/h _FEN +2 (6) . Therefore, the second output transistor 27
The collector current I _C4 is I _C4 = I ₀ /4・h _FEN・h _FEP /h _FEP +2・2/h _FEN +2...
…(7) becomes. Here, if h _FEP ≫ 2, h _FEN ≫ 2, then
Equation (7) becomes I _C4 ≒I ₀ /2 (8), and the idling current flowing through the second output transistor 27 is constant regardless of the current amplification factor (h _FEP , h _FEN ) of the transistor. current transistor 20
It is understood that it is determined only by the current I ₀ flowing in . Incidentally, the idling current flowing through the first output transistor 25 is also calculated as shown in equation (8) using the same calculation. Next, consider the maximum output current. Input terminal 1
When a large input signal is applied to the differential amplifier circuit 13, a collector current of maximum I ₀ /2 flows through the first and second transistors 15 and 16 of the differential amplifier circuit 13. Also, at that time, the collector currents of the third and fourth transistors 18 and 19 become zero, and the second current mirror circuit 22
The output current of will also become zero. Therefore, the collector current of the second transistor 16 is entirely supplied by the base current of the first inter-stage transistor 23 and the transistor 29 of the first adjustment circuit 28 , and the base current of the first inter-stage transistor 23 The current will be I ₀ /4. Since the base current I ₀ /4 is amplified by the first interstage transistor 23 and the first output transistor 25, the output transistor 2
The maximum output current I _MAX flowing through the circuit 5 is I _MAX =I ₀ /4·h _FEP ·h _FEN (9). Here, for example, h _FEP = 50, h _FEN = 300, I ₀
= 100μA, the maximum output current I _MAX is
The current is 375mA, which is sufficient to drive a load such as a headphone used in low-voltage equipment. Further, when the input signal applied to the input terminal 14 becomes negative, the first and second transistors 15 and 1
6 is turned off and the third and fourth transistors 18
and 19 collector currents become I ₀ /2, respectively. Therefore, the base current of the second interstage transistor 24 becomes I ₀ /4, and is amplified by the second interstage transistor 24 and the second output transistor 27, so that the maximum output current of the second output transistor 27 also increases. I ₀ /4·h _FEP ·h _FEN , and a sufficiently large maximum output current can be obtained. (g) Effects of the Invention As described above, the present invention provides an amplifier having an idling current set to an accurate and appropriate value depending only on the current flowing through the constant current source of the differential amplifier circuit. I can do it. Furthermore, it is possible to provide an amplifier with a large maximum output current. Further, according to the present invention, since an NPN transistor can be used as an output transistor, it is possible to reduce the chip area when integrated into an IC, and it is also possible to provide an amplifier that can operate at a low power supply voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional amplifier. Explanation of main drawing numbers, 15, 16, 18, 19...
First, second, third, fourth transistors, 20...
Constant current transistors, 23, 24...first, second
Interstage transistors, 25, 27...first and second output transistors, 28 , 31 ...first and second adjustment circuits.

Claims (1)

[Claims] 1 first and second transistors whose bases are commonly connected; third and fourth transistors whose bases are commonly connected;
a constant current source commonly connected to the emitters of the first to fourth transistors; a first current mirror circuit connected between the collectors of the first and third transistors; and the second and fourth transistors. a second current mirror circuit connected between the collectors of the transistor, a first interstage transistor that operates according to the collector current of the second transistor, and a second interstage transistor that operates according to the collector current of the third transistor. a first output transistor that amplifies the output signal of the first interstage transistor; a second output transistor that amplifies the output signal of the second interstage transistor; and a first output transistor that amplifies the output signal of the second interstage transistor; The collector current of the transistor between the two stages is attracted, and the difference current is the second
a first adjustment circuit that adjusts the base current of the output transistor; and a first adjustment circuit that sucks the collector current of the first interstage transistor according to the collector current of the third transistor, so that the difference current becomes the base current of the first output transistor. and a second adjustment circuit that adjusts the amplifier so that the first and second output transistors drive a load in a push-pull relationship.