JPS6178212A - Amplifier - Google Patents

Abstract

PURPOSE:To increase a maximum output current by using one of output currents of opposite polarity obtained from a differential amplifier stage so as to adjust the other thereby mimimizing an idling current. CONSTITUTION:A differential amplifier circuit 13 consists of a constant current transistor (TR) connected to a common emitter of TRs 15-19. The idling current flowing to output TRs 25, 27 depends not onTR current amplification factors (hFEP, hFEN) but only on a current IO flowing to the TR20. When a base current of a TR24 is IO/4 and amplified by the TRs 24, 27, then the maximum output current of the TR27 is hFEP.hFEN.IO/4 and a sufficiently large maximum output current is obtained. Thus, an NPN TR is used for an output TR and the chip area is reduced in circuit integration.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an amplifier, and more particularly to an amplifier that can accurately set the tr idle link current and is suitable for integration into an integrated circuit (IC).

(b) Prior Art An amplifier capable of increasing the maximum output current and having a small idling current is disclosed in Japanese Patent Laid-Open No. 59-99808. As shown in FIG. 2, the amplifier includes first to fourth transistors (11 to (4)) whose emitters are commonly connected, and a transistor between the collectors of the first and third transistors (1) and (3). a first current inverting circuit (Tun) connected to the second current inverting circuit (Tun), and a second current inverting circuit (Tun) connected between the collectors of the second and fourth transistors (2) and (4);
6), a first output transistor (7) whose base is connected to the collector of the second transistor (2), and a second output transistor (8) whose base is connected to the collector of the third transistor (3). and a third current inverting circuit (
91, the human input signal applied to the input terminal (lI) is differentially amplified by the first to fourth transistors (1) to (4), and the first and second output transistors (7
) and (8), and the amplified output signal is the first
Output transistor (7) and the third current inversion circuit (9)
It is supplied to the load circle in a pull/pull relationship.

In FIG. 2, the direct current flowing through the constant current transistor flZK connected to the common emitters of the first to fourth transistors fil to (4) is I. Then, the idle link current flowing to the first output transistor (power) is approximately -
b, and since it is possible to obtain a stable and appropriate idle link current, it is possible to reduce crossover attempts.

(c) Problems that the invention seeks to solveHowever,
In the case of the amplifier shown in Figure 2, the output transistor is l) N
Since it is composed of P-type transistors and has a low amplification factor, it has the disadvantage that the maximum output current cannot be made sufficiently large.

For example, the maximum output current of the first output transistor (7)
(where h□ is the current amplification factor of the first output transistor (7)).
Since the current amplification factor h2□ of the NPN transistor is smaller than the current amplification factor h2□ of the NPN transistor, a sufficiently large output current cannot be obtained. In equation (1), constant current transistor (I7
Current T flowing through J. By increasing , the maximum output current can be increased, but the idle link current also increases, which is not preferable.

Furthermore, when the final stage output transistor is configured with a PNP type transistor, there is a disadvantage that the IC area is smaller than when configured with an NPN type transistor. The allowable current per unit area of a PNP transistor is a fraction of that of an NPN transistor, so if you want to obtain the same output current, the area of a PNP transistor is N
The area of the PN transistor is 1 times the area.
! .

(Means for Solving the Problems) The present invention has been made in view of the points mentioned above, and the output current of opposite polarity obtained from the differential amplification stage is transferred to the first and second
It is taken out by an interstage transistor, amplified by a parallel-connected output transistor, and supplied to the load.
- The present invention is characterized in that first and second adjustment circuits are arranged to supply a current corresponding to the direct current outputted from the other crotch transistor to the output point of the other crotch transistor.

(E) Effects According to the present invention, the circuit configuration is such that one of the output direct currents of opposite polarity obtained from the differential amplifier stage is adjusted by the other, so that the idle link current can be kept small. And a circuit structure IJy that can use an NPN type transistor as the final stage output transistor and [K because it is negative,
The maximum output current can be increased.

(G) Embodiment FIG. 1 shows an embodiment of the present invention. A differential amplifier consisting of third and fourth transistors 08 and 01 whose bases are commonly connected to the negative feedback point plane, and a constant current transistor wire whose bases are connected to the common emitters of the first to fourth transistors 051 to 09. The input terminal of the circuit 0 is the first transistor 0!
9, the output end is connected to the third transistor (18
first current inversion circuits connected to the collectors of (
The 21st! 031 is a first inter-stage transistor whose base is connected to the collector of the second transistor QQ, and (24) is a second inter-stage transistor whose base is connected to the collector of the third transistor QQ.

(c) is the base force of the first interstage transistor (23) whose emitter is connected to the collector of the first interstage transistor (23) and the output midpoint (c).
The output transistor (2) is a second output transistor whose base is connected to the collector of the second interstage transistor 0 (A) and the collector is connected to the output midpoint (C). The first inter-stage transistor C23), the commonly connected Samuta transistor (2), and the input terminal of the transistor C! 9), the output end of which is connected to the second interstage transistor c! 4) a first adjustment circuit consisting of a $33 current commutation circuit □□□ connected to the collector of 6), and 6) a first adjustment circuit whose base and emitter are connected to the second interstage transistor CI'41;
and a fourth DC inverting circuit (G) whose input terminal is connected to the collector of the transistor 1 and whose output terminal is connected to the collector of the first interstage transistor C231, respectively. This is the second adjustment circuit consisting of the following.

First, consider the idle link undercurrent flowing to the first and second output transistors 05) and (5). Now, if the current flowing through the constant current transistor wire of the differential amplifier circuit
The collector currents ICI of 21a) and (21b) are as follows, and the base current of the second interstage transistor C (a) is equal to the base current of the transistor 02 of the second adjustment circuit 2). If it is 1, then it becomes. And the base current ■. is amplified by the second interstage transistor C4), so it becomes the collector ti IC2ti of the second interstage transistor C24).

Note that since the amplifier is configured symmetrically, the first interstage transistor (c), the 1.11! The collector current of the transistor 04 of the transistor 04 of the adjustment circuit @ and the second adjustment circuit 04 is equal to the collector current of the second interstage transistor, and has a value expressed by the f41 formula.

The base current of the second output transistor 127) is the first interstage transistor c! This is the difference current between the collector current of 4) and the output current of the third current inversion circuit, and the output current of the third current inversion circuit (collector current of the transistor (30a)) 9. Therefore, from equations (4) and (5), the base current 1112 of the second output Y transistor η is expressed as ist
= IC2' L3. Therefore, the collector current of the second output transistor amount. 4 becomes . Here, if hygp>2, "rww)2, then equation (7) becomes: The idle link current flowing through the second output transistor (2η) is
, hrs, l), constant current transistor (a)
It is understood that only the current I0 flowing through K is determined by K. Note that the idle link direct current flowing to the first output transistor C25) is also calculated from the same total IK as in equation (8).

Next, consider the maximum output current. When a large input signal is applied to the input terminal 041, the collector current of the first and second transistors (one and (16)) of the differential amplifier circuit 0 is zero. As a result, the output current of the second current inverting circuit @ also becomes zero. Therefore, the collector current of the second transistor (161) is entirely from the first inter-stage transistor C3 and the transistor (c) of the first adjustment circuit @. Since the base current is supplied by the base current and is amplified by the first output transistor (c) of the first interstage transistor, the maximum output current 'IMA' flowing through the output transistor (c) is.

becomes. Here, for example, 'FIF" 50, hFIN"
300, I0 = 100 μA, the maximum output current IMA! is 37577 LA, which is a value sufficient to drive a load such as a handphone used in low voltage equipment.

In addition, when the input signal applied to input terminal 04) K becomes small, the first and second transistors (one and Oe are turned off, and the third and fourth transistors (181 and 09, the second interstage transistor Since it is amplified by C141 and the second output transistor (5), it becomes the second output, and a sufficiently large maximum output current can be obtained.

(G) Effects of the Invention As described above, according to the present invention, an amplifier having an idle link current that is set to an accurate and appropriate value depending only on the current flowing to the constant current source of the differential amplifier circuit can be provided. I can provide it. Furthermore, it is possible to provide an amplifier with a large maximum output current.

Furthermore, according to the present invention, an NPN transistor is used as the output transistor.
Since a type transistor can be used, it is possible to reduce the chip area when integrated into an IC, and it is also possible to provide an amplifier that can operate with a low power supply voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional amplifier. Explanation of main drawing numbers 0!9, Oe, 0110, Qt...1st, 2nd, 3rd... 4th transistor, 翰...constant current transistor, (c), c24)...transistor between the first and second stage, (c), (9)...first and second output transistor, ni) , (b)... 1st, 2nd & 14th rectifying circuit.

Claims (1)

[Claims] (1) first and second transistors whose bases are commonly connected; third and fourth transistors whose bases are commonly connected; and a constant current source that is commonly connected to the emitters of the first to fourth transistors; a first current inversion circuit connected between the collectors of the first and third transistors; and a second current inversion circuit connected between the collectors of the second and fourth transistors.
a current inversion circuit; a first interstage transistor that operates according to the collector current of the second transistor; a second interstage transistor that operates according to the collector current of the third transistor; and a first interstage transistor that operates according to the collector current of the third transistor. a first output transistor that amplifies the output signal; a second output transistor that amplifies the output signal of the second interstage transistor;
the second transistor depending on the collector current of the second transistor;
a first adjustment circuit that adjusts the collector current of the interstage transistor; and a second adjustment circuit that adjusts the collector current of the first interstage transistor according to the collector current of the third transistor.
and an adjustment circuit, the amplifier being configured to drive a load in a push-pull relationship using the first and second output transistors.