JPH08123952A - Image data read control circuit - Google Patents

Abstract

PURPOSE: To provide the image data read control circuit which is capable of thinning and read at the time of setting arbitrary start and end addresses. CONSTITUTION: An address counter 13 and an address counter 14 are provided, and the start address of the area from which image data is read out is set to the counter 13, and this counter 13 counts up the start address, and the end address of this area is set to the counter 14, and this counter 14 corrects the end address. An adder 19 which detects the data width from the start address to the end address in the direction of thinning and read is provided; and if this data width is not adapted to the thinning width, the address counter 14 corrects the end address so that the data width is adapted to the thinning width.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read control circuit for reading image data from an image memory which stores image data, and more particularly to an image data read control circuit in an optical character reader.

[0002]

2. Description of the Related Art Conventionally, for example, an optical character reader (OC)
In R), the image on the form is read by the sensor,
The read image data is converted into digital data and stored in the image memory. When reading image data such as characters from the image memory, a method called area read is used in which the start address and the end address in the main scanning direction and the sub scanning direction of the area including the data are designated.

Area reading methods include a normal reading method for reading all data in an area and a thinning-out reading method for thinning out data in the main scanning direction or the sub-scanning direction. When reading is performed, the end of reading is determined by counting up to the designated end address by the address counter and detecting whether the counted up value matches the value of the end address. When performing thinning reading, the address count up in the thinned direction is
It is counted up by two.

[0004]

However, in the conventional read control circuit, when area reading is performed by thinning-out reading in the sub-scanning direction, if the start address and end address in the sub-scanning direction are set with even widths, Since the address counter in the sub-scanning direction counts up by two from the start address, the value of the address counter does not match the end address. Therefore, in the case of thinning-out reading, the start address and end address in the sub-scanning direction must be set with an odd width,
There was a problem that it could not be set with an arbitrary address value.

[0005]

To solve the above problems, the present invention specifies an address of an area in an image memory to read image data from the area, and
In an image data read control circuit capable of thinning and reading image data, a detecting means for detecting a data width between a read start address and a read end address designated in a main scanning direction or a sub scanning direction, and an address from the read start address. A counting means for counting the number and a correcting means for correcting the data width so that the data width matches the count value of the counting means when the image data is thinned out and read out are provided. Is.

[0006]

According to the present invention having the above-mentioned structure, when the image data is thinned out and read out, the detecting means detects the data width between the designated read start address and the read end address. The counting means counts the number of addresses from the read start address. If the read end address does not match the address count value, the correction unit corrects the detected data width so as to match the count value. As a result, the read end address and the address count value match, and the read can be ended.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. Note that elements common to the drawings are given the same reference numerals. 1 is a block diagram showing an image data read control circuit of an embodiment according to the present invention, FIG. 2 is an explanatory view showing an image memory, and FIG. 3 is an explanatory view showing thinning-out reading.
First, thinning-out reading will be described with reference to FIGS.

In FIGS. 2 and 3, the image memory 1 stores data for one read form. When reading these data, the characters are cut out character by character, but the character cutting is performed by cutting out the area 2 including the characters. The cut-out area 2 is transferred to the cut-out memory through a binarization circuit (not shown). This reading method is called area reading as described above, but the image data in the image memory 1 is coordinate-managed by the address in the main scanning direction (X direction) and the address in the sub scanning direction (Y direction).

When performing area read, the start address and end address in the X and Y directions are designated. In FIG. 3, "0" is set as the X-direction start address and "15" is set as the end address. Similarly, "0" is set as the start address in the Y direction and "15" is set as the end address.

In FIG. 1, the image data read control circuit of the embodiment is provided with a buffer 11 for storing a start address in the Y direction and a buffer 12 for storing an end address in the Y direction. Connected, the buffer 12 is connected to the address counter 14. The address counter 13 is loaded with the start address data in the Y direction by the start address set signal, and the address counter 14 is loaded with the start address data.
End address data in the Y direction is loaded by the end address set signal. Address counters 13 and 14
An address compare 15 is connected to. The address compare 15 compares the count value output from the address counter 13 with the value set in the address counter 14, and if both values match, outputs a match signal to one input of the OR gate 16. . The OR gate 16 is connected to the flip-flop 17, and the flip-flop 17 is further connected to the area read timing circuit 18.

The address counter 13 and the address counter 14 are connected to an adder 19. Adder 19
The least significant bit of the start address is input from the address counter 13, and the least significant bit of the end address is input from the address counter 14. The adder 19 is
Connected to the OR gate 21 via the knot gate 20,
The OR gate 21 is connected to the address counter 14.

Next, the operation of this embodiment will be described. Note that, here, a case where thinning-out reading is performed in the Y direction will be described. The thinning readout in the X direction is basically the same, and illustration of the readout control circuit in the X direction is omitted.

When a Y direction start address set signal is output from the control unit (not shown) to the buffer 11 and the address counter 13, the Y direction start address data "0" is sent to the address counter 13 via the Y direction start address bus and the buffer 11. "Is loaded. When a Y-direction end address set signal is output from the control unit (not shown) to the buffer 12 and the address counter 14, the Y-direction end address data “15” is sent to the address counter 14 via the Y-direction end address bus and the buffer 12. Loaded.

Although not shown, a start address counter and an end address counter are also provided in the X direction, and "0" is set in the start address counter as in the Y direction. Is
“15” is set in the end address counter. Then, after the X-direction address counter counts up from the start address to the end address, the Y-direction address counter 13 counts up by 2. Then, the address counter in the X direction counts up from the start address to the end address, and then the address counter 13 in the Y direction counts up by 2. By repeating this operation, the image data in the shaded area shown in FIG. 3 is sequentially read.

The least significant bit (LS) of the output data (start address) output from the Y-direction address counter 13
B) is input to the adder 19 and the address counter 1
4 output data (end address) least significant bit (L
SB) is input to the adder 19. The adder 19 performs an operation based on these least significant bits to obtain the data width of the start address data and the end address data.
If the data width is an odd width, the output result of the adder 19 is "0", and if the data width is an even width, the output result is "1". Here, the odd width is represented by an odd number of widths from the start address to the end address in the Y direction, and the even width is represented by an even number of widths from the start address to the end address in the Y direction. It is a thing. For example, the start address value is "0" and the end address value is "15".
If the start address value is “0” and the end address value is “14”, the data width is an even width.

The adder 19 outputs this output result to the knot gate 20 as an end address correction signal. The output of the NOT gate 20 is set by the OR gate 21 to the count enable terminal of the address counter 14 after taking OR with the Y direction thinning / without signal output from the control unit (not shown). As for the Y direction thinning-out presence / absence signal, "0" is output when thinning out in the Y direction, and "1" is output when thinning out is not performed. In this case, since the thinning-out is performed in the Y-direction, the Y-direction thinning-out presence / absence signal is "0". Therefore, when thinning out in the Y direction, if the data width is an even width, the OR gate 2
The output of 1 becomes "0", and if the width is odd, OR gate 2
The output of 1 becomes "1".

After that, when area reading is performed, an area read activation signal is output from the control unit (not shown) and input to the count enable terminal of the end address address counter 14. When the output value of the OR gate 21 set to the count enable terminal of the address counter 14 is “0”, the count value of the address counter 14 is 1
One is counted down. That is, the address value decreases by one with respect to the end address value initially set. When the output value of the OR gate 21 is "0", it means that the data width is an even width, and this means that the data width is changed from an even width to an odd width. If the data width is originally an odd width, the end address value remains unchanged.

The end address data of the address counter 14 is output to the address compare 15. On the other hand, the start address data of the address counter 13 is input to the address compare 15. Address counter 13
Counts up by 2 from the start address value, and the counted up value is the address compare 15
Sent to The address compare 15 compares the count-up start address value with the corrected end address value, and outputs an address match signal to the OR gate 16 when they match. Since the corrected end address value has an odd width, it always matches the counted up address value, and the address match signal is output.

When an X-direction address counter (not shown) counts up to the end address, an X-direction address coincidence signal is output, and the OR gate 16 performs a negative OR operation with the Y-direction address coincidence signal and the flip-flop is operated. 17 is reset. As a result, the area read valid signal output to the area read timing circuit 18 becomes "invalid", and the area read ends.

FIG. 4 is a time chart showing the end timing of the area read when the area read is performed by thinning-out reading in the Y direction. In the figure, since the end address address counter 14 counts down when the area read is activated, the end address value in the Y direction is changed from "15" to "14". The addresses in the Y direction are incremented by 2, and the addresses in the Y direction are changed from "Ay12" (Y address "12") to "Ay1".
When it becomes 4 "(Y address" 14 "), the Y direction address match signal becomes valid. When it becomes" Ay14 ",
The address in the X direction is “Ax15” (X address “1
5 "), the X-direction address match signal becomes valid, and the area read ends at this point.

As described above, even if the start address and the end address are set to arbitrary values, the thinned-out reading can be performed. Although the above embodiment has described the case of thinning out in the sub-scanning direction (Y direction), it goes without saying that the same can be done in the case of thinning out in the main scanning direction (X direction).

[0022]

As described above in detail, according to the present invention, when performing thinning-out reading, even if the start address and the end address to be set are arbitrary values, the end address is set so as to match the thinning-out width. Since the correction is performed, the thinned-out reading can be performed even if the start address and the end address are arbitrarily set.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image data read control circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an image memory.

FIG. 3 is an explanatory diagram showing thinning-out reading.

FIG. 4 is a time chart showing the timing of ending area reading.

[Explanation of symbols]

 1 Image Memory 13 Start Address Address Counter 14 End Address Address Counter 15 Address Compare 19 Adder

Claims (2)

[Claims] 1. An image data read control circuit capable of designating an address of an area in an image memory to read image data from the area, and thinning and reading the image data, and designating in a main scanning direction or a sub scanning direction. Detecting means for detecting the data width between the read start address and the read end address, counting means for counting the number of addresses from the read start address, and when the image data is thinned and read, the data width is the counting means. And a correction means for correcting the data width so as to match the count value of the image data reading control circuit. 2. The image data read control circuit according to claim 1, wherein the detection means is an adder that adds the least significant bit of the read start address and the most significant bit of the read end address.