JPS5812471A - Picture signal processing system - Google Patents

Abstract

PURPOSE:To correct a whisker-shaped projecting part which appears in a picture signal when ruled lines in a main scanning direction are read, and to improve picture quality and the band compressibility of the picture signal, by providing a picture signal processing circuit between a read part and a band compression part. CONSTITUTION:An original picture signal (e) obtained by a read part is outputted as one-line data from a demultiplexer 6 to line memories 7a-7d by a selection input from a line counter 5, and also applied to black-picture-element counters 8a-8d. Those counters 8a-8d count the numbers of succeeding black picture elements of the one-line signals written in the memories 7a-7d and outputs carries (g)-(j) when N bits succeed. The outputs of the counters 8a-8d are held temporarily in registers 10a-10d, and 11a-11d and then applied to a correction signal generating circuit 12 and also to a circuit 12 through FFs 9a-9d. Whisker-shaped projecting parts of the picture-element signals read out of the memories 7a-7d are corrected by the circuit 12 to improve picture quality.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing method for processing both white and black binary signals obtained by a task scanning type reader in a facsimile machine, etc. The present invention relates to an image signal processing method that can remove fluff-like protrusions from ruled lines.

For example, many documents sent by facsimile machines have ruled lines as shown in FIG. If the ruled line is misread by the reading section of the facsimile E/IJ device, the image signal output from the reading section is converted into a corresponding received image and expressed as, for example, as shown in Fig. 2. , a fluff-like protrusion like F often occurs in D and D (in FIG. 2, one shaded square indicates one black pixel).

However, in the conventional facsimile machine, as shown in FIG. 4, the image signal shown in FIG. The fuzz-like protrusions appear on the image, making them look bad, and the fuzz-like protrusions deteriorate the compression ratio of the image signal in the band compression section 2.

The present invention has been made to eliminate the above-mentioned drawbacks of the conventional art, and improves image quality by removing the fluff-like protrusions that occur in the image signal when reading ruled lines in the main scanning direction, as shown in FIG. 3, for example. It is an object of the present invention to provide an image signal processing method that can improve the band compression ratio of both signals.

Specifically, the image signal processing method according to the present invention is a dual signal processing method for processing binary white and black image signals obtained by a task scanning type reading device.
The lines are sequentially counted, and if there are at least 1 consecutive black pixels in the first line or the last line among the three lines, and the consecutive black pixels in the middle line among the three lines are If there is a black pixel in the same section as the pixel, and if the pixel in the same number as the black pixel in the middle line of the first line or the last line is a white pixel, then The black pixels of the line are changed to white pixels.

The present invention will be described below based on embodiments shown in the drawings.

In FIG. 6, the signal processing circuit 3 inputs the original image signal e output from the reading section 1, creates both signals f, and sends them to the band compression section 2.

FIG. 6 shows an example of the original image signal e when the reading unit 1 has read the ruled lines in the main scanning direction and the ruled lines in the sub-scanning direction.
It is expressed by converting it into an image corresponding to it, and one square with diagonal lines indicates one black pixel. In the figure, G is a 2-dot wide ruled line in the main scanning direction;
H, , I, and J are ruled lines in the sub-scanning direction, K and L are 1-dot fluff-like protrusions, and M and N are 2-dot fluff-like protrusions.

It is no secret that the ruled lines H, I, and J in the sub-scanning direction must not be removed. Also, statistically speaking, there is a low probability that a fuzzy protrusion with two or more dots like M or N will occur, so in the wooden sword style, K.

Remove the fluff-like protrusion with only one dot like L.

7 to 9 are a block diagram and a circuit configuration diagram showing the configuration of the image signal processing circuit 3 in this embodiment. In FIG. 7, there are four original image signal input terminals, into which the original image signal e output from the reading section 1 is input. 6 is 0 → 1 → 2 → 3 → 0 →...
6 is a demultiplexer whose data input is the original picture signal e inputted from the original picture signal input terminal 4, and whose selection input is the output of the line kakunta 6. '7a, 7b, 7c, 7dLI
i is a line memory, and each of the four outputs of the demultiplexer 6 is used as a data input. Sa.

8b, 80.8+5Iri is a black pixel kakunta for detecting ruled lines in the main scanning direction, and black pixels are continuous in the original image signal e for each line written to each line memory 7a to 7d through the demultiplexer 6. The number of dots that appear is counted, and if H bits of black pixels are consecutive, carry g+h, i, and j are output, respectively.

In the following explanation, let N be the number of dots on 84 screens, 2048.
In the explanation, it is assumed that N is set to 1o24, which is half of N, but this N can be selected appropriately. 9 turtle, 9b.

Reference numerals 9c and 96 are flip-flops, which are set by the carries g to j of the black pixel kakuntas 8a to 8d, respectively. 10m, 10b, 10c.

IQd is a register, and if there are 1024 or more consecutive black pixels in one line of original image signal e written to each line 7a to 7d, the address of the first black pixel (JJ, bottom, start, address ) are temporarily held. 11 &, 11 b.

11Q, 11 (5 is also a register, each line 7a-7
1024 in one line of original image signal e written to d
If there are consecutive black pixels, the address of the last black pixel (hereinafter referred to as end address) is temporarily held. 12 is a corrected image signal generation circuit, which includes line memories 7a to 7d, flip-flops 9 & to 9 (1
, and registers 1oa to 10d, 113 to 11 (i) to create and output a corrected image signal f.

A more specific configuration of the corrected image signal generation circuit 12 is described in the eighth section.
As shown in FIG.

Next, the operation of this embodiment will be explained first with reference to FIG.

By counting and accruing each line of the original image signal e by the line capacitor 6, the outputs of the demultiplexer 7 and the cleavage sensor 6 are sequentially selected line by line, so that the original image signal e is sequentially input to the line memo IJ 7 line by line.
Writes are written in a to 7d and are truncated. While the original image signal e of a certain line is being written into one of the line memories 71 to 7d, from the remaining three line memories,
The original image signal e of one to three lines before the line where the writing is being performed is read out.

On the other hand, if there are 1000 or more consecutive black pixels in one line of the original image signal e written to each line memory 7&~7d, carries g~j are output from the corresponding black pixel counters 8a~8d. , the corresponding flip-flops 9a to 9d are read, so if there is a ruled line in the main scanning direction on the document, the flip-flops corresponding to the line memories 7a to 7d in which the line of the original image signal e read from the ruled line is written 9a to 9d are set.

The correction signal generation circuit liF+12 converts the middle line of the three lines of original image signals e read out from the three line memories 71L to 7d that are not being written into, the contents of the remaining two lines, and the contents of the remaining two lines 9a to 9( 1,10a ~
IC1,11! L ~ 11 (the remaining 2 of 1
The corrected image signal fK is converted by referring to the outputs of the flip, flop, and register corresponding to the two lines. That is, if there is a one-dot fluff-like protrusion on the center line, the signal after removing it is output as the correction signal f.

The above-mentioned FIG. 8 shows the case where writing is performed in the line memory 7d while reading is performed from the other line memories 7&~7c, and the line read out from the line memory 7b is converted into a corrected image signal f. The connections and relationships between the corrected image signal generation circuit 12 and other circuits are shown. Next, FIG. 8 will be explained.

Reference numeral 13 indicates a read address and counter for the line memories 7a to 7c. It is a 14 to 17 digit comparator. The comparator 14 receives the read address, the address output from the counter 13, and the start address 9 output from the register 101L.

shall be. The comparator 15 has a read address.
Address output from counter 13 and register 111
The end and address output from L are compared, and when they match, the output is set to 1. The comparator 16 compares the read address output from the read address counter 13 and the start address output from the register 1oc, and sets its output to 1 when the two match. The comparator 17 compares the read address output from the read address counter 13 and the end address output from the register 11c, and sets the output to 1 when the two match. Reference numeral 18 is a clip-flop which is set when the output of the comparator 14 becomes 1 and reset when the output of the comparator 16 becomes 1. Flip 19 as well.

It is a flop, and is set when the output of comparator 16 becomes 1, and is set when the output of comparator 17 becomes 1. 2IO is frisoge flop 9 &, 9
21 is an inverter that receives the Q output of flip-flop 9b as input, and 22 is a two-person cam LiD gate that receives the output of OR gate 2o and inverter 21 as input. be. 23 is a two-person cam ND gate that receives the Q outputs of the clip and flops 9a and 18 as input; 24 is a two-person AND gate that uses the flip and the Q outputs of flops 9C and 19 as input; This is a two-man OR gate that takes the output as the input.

26 is an AND gate which receives the output of the ND gate 22 and the output of the OR gate 26 as inputs.

Reference numeral 27 denotes a demultiplexer, which uses the original image signal e of the line read from the line memory 7b as a data input, and uses the output of the ND gate 26 as a selection input.

28 is a black signal removal circuit that selectively removes the black signal, the specific configuration of which is shown in FIG. 9; 1 as data input, line memory 7a
, 7c is used as a control input. 29 is an O which takes the output kO selected when the select input of the demultiplexer 27 is "♂" as one input, and takes the output of the black signal removal circuit 28 as the other input.
This is the R gate. A corrected image signal f is obtained from the output of this OR gate 29.

Next, a specific configuration of the black signal removal circuit 28 will be explained with reference to FIG.

Reference numeral 30 denotes a two-man power AND gate which receives as input the line of the original image signal e read out from the line memory T&70.

31 is a selector, and 1 is input to the output of the demultiplexer 27 to the input 11 which is selected when the select input is "1", and the input which is selected when the select input is "O". "0" is always input to l12, and the output of gate 30 is input to the select input.

The output of this selector 31 becomes the output of the black-and-white conversion circuit 28.

Next, a line with the original image signal e is currently being written in the line memory 7d, and at this time, the line memory 7a to
The operation of the circuits shown in FIGS. 8 and 9 will be explained by taking as an example the case where the bits and patterns of the 3-tree line read from 7C are as shown in FIG. 10.

In FIG. 10, the line written in the line memory 7a is a line obtained by reading the ruled lines in the main scanning direction, and is a continuous black line of 1024 or more pixels with the start address 4, the address ~, and the end address 2044. Pixel exists (P indicates its first black pixel, Q indicates its last black pixel) Also, in the line written in the line memories 7b, 7c, 10
There are no consecutive black pixels of 24 or more, and there are black pixels R1S that read the ruled lines in the sub-scanning direction.

Further, in the line written in the line memory 7b, there is a black pixel T forming a one-dot fluff-like protrusion.

Therefore, while flip 86f and flop 9a are set in line memory 7&, line memory 7&
The flip-flops 13 and tabs 9b' and 90 corresponding to b and 7c have been reset, and the mum ND gate 22 is now disabled. I cut it.

Corresponding to the line memory 7a is the register 101L.

11aK holds a start address 4 and an end address "2o44", respectively.

In this situation, the read address.

The counter 13 starts operating and each line is read from the line memories 7a to 7C. When the output value of the counter 13 reaches 4, the output of the comparator 14 becomes 1, so the flip/flop 18 is set. . Also, after that, the output value of the counter 13 becomes 2044
Then, the output of the comparator 15 becomes 1, so the flip/flop 18t/i is reset.

Therefore, the output value of the counter 13 changes from 4 to "2044".
“Only when the values between 1 and 2 are being taken, that is, while the pixels from U to X in FIG. The output of becomes 1.

The output becomes 0 (!:), and during this time, the demultiplexer 27
The output kO of is selected, and the original image signal e read out from the line memory 7b is output as is as the 1-corrected image signal f through the demultiplexer 27 and the OR gate 29. This means that of the lines written in the line memory 7a, the portions that are not in the same section as the ruled lines in the main scanning direction written in the line memo IJ7a are output as they are as the corrected image signal f. means.

On the other hand, while the output of the ND gate 26 mentioned above is 1, 1 is selected as the output of the demultiplexer 27, so the original image signal e read out from the line memory 7b is passed through the demultiplexer 27 to the black signal. Removal circuit 2
8 is input to the input 11 of the selector 31. In this case, when a black pixel belonging to a ruled line in the sub-scanning direction, such as the black pixel R (or a black pixel belonging to a fluff-like protrusion of two or more dots), is read out from the line memory 7b,
Since the line memories 7a and 7c also produce a black image, input ll of the selector 310 is selected, so the black pixel R
etc. are output as is as the corrected image signal f without being removed.

However, when a one-dot fluff-like protrusion like the black pixel T in FIG. 10 is read out from the line memory 7b, a white pixel is read out from the line memory 7C.
Since the output of the ND gate 3o becomes O and the output lO of the selector 31 is selected, an image signal is output from the selector 31 for the black pixel forming the one-dot fluff-like protrusion, such as the pixel T. Ru.

That is, in the corrected image signal f, the fluff-like protrusion of one dot is removed.

In addition, when the white pixel signal is read out from the line memory 7b, the output of the ND gate 3o is ``1'' or ``0''.
In either case, the corrected image signal f becomes a white signal, and as a result, the original image signal e directly becomes the corrected image signal f.

By performing the above operations, the image signal in which only one dot of fluff-like protrusion is removed from the original image signal e, and only the ruled lines in the sub-scanning direction are left, is used as the corrected image signal f. You will get it.

In addition, although FIG. 10 shows a case where the line where the ruled line in the main scanning direction is read in the line memory 7a is overwritten, the line where the ruled line is read in the main scanning direction is overwritten in the line memory 7C. Even if there is a line written in the line memory 6, a similar operation is performed to remove the fluff-like protrusion from the line written in the line memory 6.

8 and 9 show the connection relationship between the corrected image signal generation circuit 12 and other circuits when writing is performed in the line memory 7d while reading is performed from other line memories 7a to 7C. Although shown, the line memories 7a~
Even when writing to and reading from 7d is performed in other combinations, the same operation as described above is performed by switching the connection relationship to correspond to the combination.

As is clear from the above description, the image signal processing method according to the present invention can remove fluff-like protrusions that occur in the image signal when the ruled lines in the main scanning direction are read, thereby improving the image quality and improving the image signal. This provides an excellent effect of improving the compression rate when performing band compression.

[Brief explanation of drawings]

Figure 1 is a plan view of a ruled original, Figure 2 is a schematic diagram for explaining the fluff-like protrusions that occur in the image signal when reading ruled lines in the main scanning direction, and Figure 3 is based on Figure 2. FIG. 4 is a block diagram showing a conventional facsimile E/IJ device, and FIG. 6 is a block diagram of a facsimile device using the image signal processing method according to the present invention. , FIG. 6 is a schematic diagram illustrating an image signal obtained by reading ruled lines in the main scanning direction and sub-scanning direction, and FIG. 7 is a block diagram of an embodiment of the image signal processing method according to the present invention.
FIG. 8 is a circuit configuration diagram showing the specific configuration of the corrected image signal generation circuit and its connection relationship with other circuits, and FIG. 9 is a circuit configuration diagram showing the specific configuration of the black signal removal circuit and connection relationships of other rotations. , FIG. 10 is a schematic diagram for explaining the bit pattern of the original image signal written in the line memory in the above embodiment. , 7a-7d...line memory, 8
a-8d...Black pixel counter, 1o2L~10
d, 111-11d...Register, 12...
...Corrected image signal creation circuit, 13...Read address, counter, 14-17...Comparator, 27...Mark/demultiplexer, 28...
・Black signal removal circuit, 31・Old...Selector. Name of agent: Patent attorney Toshio Nakao Haga1 person-1
Figure 2m Figure 3 Figure 4! ! l Fig. 5 Fig. 6 Fig. 19 Fig. 31 Fig. 10 2048b, O

Claims (1)

[Claims] Sequentially count three consecutive lines of white and black binary image signals obtained by a task scanning type reader, and determine whether there are N or more consecutive black pixels in the first or last line of these three lines. and there is at least one black pixel in the same section as the continuous black pixels in the middle line among the three lines, and in the first line or the last line. If the pixel in the same number as the black pixel in the middle line is a white pixel, the black pixel in the middle line of FIIF is changed to a white pixel.