JPH0413882Y2 - - Google Patents

Description

[Detailed explanation of the idea]

(Industrial Application Field) The present invention relates to a halftone data enlarging/reducing circuit using a dither method, and in particular to a dithering circuit that can obtain enlarged or reduced binary image data without deteriorating image quality. This invention relates to a circuit for enlarging/reducing halftone data using the method. (Prior Art) Conventionally, as a method of enlarging or reducing an image, a method of duplicating or thinning out image data is common. An example of the conventional method will be explained with reference to FIG. First, a method of binarizing image data using dither will be briefly explained. Now, assume that there is multi-tone read image data as shown in FIG. 8a. Further, it is assumed that the dither matrix is a 4×4 matrix surrounded by a thick black frame as shown in FIG. In such an example, when the read image data is binarized by dither processing, each piece of the read image data is
It is compared with the threshold value of the dither matrix at the corresponding position, and if the former is larger than the latter, it is determined to be black (or digitally "1"), and if the opposite, it is determined to be white (digitally "0"). , the data binarized by dither processing is as shown in FIG. 8c. In FIG. 8c, hatched pixels indicate black, and non-hatched pixels indicate white. Now, when enlarging or reducing a multi-tone read image using this dither method, the following method can be considered. That is, the read image data as shown in FIG. 8a is binarized using the dither matrix shown in FIG. 8b, and binarized data as shown in FIG. After obtaining this binarized data,
It is possible to perform duplication or thinning processing. (Problem to be solved by the invention) However, when the read image is enlarged or reduced using this method, the binarized data obtained with a predetermined regularity by the dither matrix changes to this regularity. There was a problem that the image quality deteriorated. The present invention has been made to solve the above-mentioned problems. (Means and operations for solving the problem) In order to solve the above-mentioned problem, the present invention makes it possible to divide each pixel of read image data into a column of a dither matrix corresponding to the column to which the pixel belongs. , and outputs the binary dither data that is the comparison result in parallel, and from the dither data output in parallel, according to the set reduction and enlargement magnification while maintaining the regularity of dither processing. The feature is that dither data is thinned out and duplicated. (Example) The present invention will be explained below with reference to an example. FIG. 1 shows a schematic block diagram of one embodiment of the present invention. In the figure, numeral 10 denotes a dither circuit that compares pixel information a read from a document with a threshold value of a dither matrix and outputs binary dither data _c0 to _c3 . Further, reference numeral 12 is a reduction processing device that performs enlargement, same-size, and reduction processing. First, the configuration and functions of the dither circuit 10 will be explained in detail. For example, suppose that there is multi-gradation read image data D as shown in FIG. It is assumed that input is made. That is, at a certain time _T1 , the first data "8" of the read image data D is output to the dither circuit 10.
At the next time T ₂ , the data of the pixel shifted by one pixel in the main scanning direction is "9", and at the next time T ₃ , the data of the pixel shifted by one pixel in the main scanning direction is "10".
Data of pixels shifted one pixel at a time in the main scanning direction is inputted sequentially. When all of the pixel data for one row in the main scanning direction has been input to the dither circuit 10, the data is moved by one pixel in the sub-scanning direction, and the time
It is assumed that the pixel data of the second column is sequentially input to the dither circuit 10 at T _n , T _{n +1} , T _{n +2 .} . . . Furthermore, when all of the pixel data of the second column has been input to the dither circuit 10, the data is further moved by one pixel in the sub-scanning direction, and time T _o , T _o + ₁ , T _o + ₂ . . .
Assume that the pixel data of the third column is sequentially input to the dither circuit 10. Next, when the read image information a is input pixel by pixel as described above, the dither circuit 10 compares each pixel with all the threshold values of the column of the dither matrix corresponding to the column to which the pixel belongs. Then, binary dither data _c0 to _c3 , which are the comparison results, are output in parallel. For example, as described above, when pixel data "8" is input to the dither circuit 10 at time T ₁ , the data "8" is input to the four threshold values "8" in the first column of the threshold values of the dither matrix. 0,” “8,” “2,” and “10.” If the pixel data “8” is greater than or equal to the threshold, an H level signal is output, and if it is smaller, an L level signal is output in parallel from the dither circuit 10. be done. In this column, pixel data "8" is greater than or equal to the first three of the four threshold values, so the dither data c ₀ which is the output of the dither circuit 10
~ _c2 becomes H level. Furthermore, since the pixel data "8" is smaller than the fourth threshold, the dither data _c3 output from the dither circuit 10 becomes L level. Next, at time _T2 , when pixel data "9" is input as pixel information a, the data "9" is also compared with the four threshold values in the first column of the dither matrix, as described above. Ru. Then, the results are outputted in parallel as dither data _c0 to _c3 of the dither circuit 10, as described above. Also at times T ₃ , T ₄ , T ₅ , ..., each pixel data input to the dither circuit 10 is compared with the four threshold values in the first column of the dither matrix, and the results are sequentially input to the dither circuit 10. Dither data of c ₀ ~ _{c 3}
are output in parallel. After the above-described dither processing of the pixel data in the first column of the read image data D shown in FIG. to go into. That is, the time
At T _n , when the leftmost pixel data "9" in the second column is input to the dither circuit 10 as pixel information a, the dither circuit 10 inputs the pixel data "9" and the second pixel data of the dither matrix. It is compared with the four threshold values "12", "4", "14", and "6" in the column. The comparison results are output in parallel as dither data c ₀ to _{c 3} that are output from the dither circuit 10. Thereafter, the pixel data in the second column of the read image data D is sequentially read out one by one in the main scanning direction and compared with the four threshold values in the second column of the dither matrix, and the results are used in the dither circuit 10. are output in parallel as dither data _c0 to _c3 . After the dither processing of the second column of pixel data of the read image data D is completed, next is the third column of the read image data D.
Dither processing of pixel data in the column begins. This dithering is performed using the four threshold values in the third column of the dither matrix shown in FIG. 2b. Similarly, the fourth column of the read image data D,
The dither processing of the pixel data of the 5th column, 6th column, 7th column... is performed on the 4th column, 1st column, 2nd column, 3rd column... of the dither matrix. 4 in
This is done using several threshold values. FIG. 3 shows a time chart of the dither data c ₀ -c ₃ which is the output of the dither circuit 10 performed as described above. Note that the times T ₁ , T ₂ , T ₃ ..., T _n , T _n + ₁ , T _n + ₂ ..., in Fig. 3 are
T _o , T _o + ₁ , T _o + ₂ . . . are drawn in correspondence with each of the above-mentioned times. As described above, the dither circuit 10 compares the input pixel information a with the four threshold values of the dither matrix of the corresponding column pixel by pixel, and divides the result into 2
It performs a function of outputting values in parallel as dither data _c0 to _c3 . Note that the select signal b input to the dither circuit 10 shown in FIG. 1 is a signal for selecting a column of the dither matrix. Next, with reference to FIG. 4, the configuration of an embodiment of the dither circuit 10 that performs the above function will be described. In the figure, 14, 16, 18 and 20 each represent a comparator, and 22 represents a selector. Also, 2
4, 26, 28 and 30 indicate four threshold values in the first, second, third and fourth columns of the dither matrix, respectively. _d0 to _d3 are the comparators 14 to 2
The line connected to the inverting input terminal of 0 is shown. Further, symbols other than those mentioned above indicate the same parts as in FIG. 1. In the circuit shown in FIG. 4, when the pixel information a belongs to the first column, fifth column, etc. of the read image data D, the select signal b is connected to each of the lines d ₀ to d ₃ and the dither matrix. When pixel information a belongs to the second column, sixth column, etc. of the read image data D, the lines d ₀ to d ₃ are connected to each of the four threshold values 24 in the first column. Connect each of the four threshold values 26 in the second column of the dither matrix,
Pixel information a is in the third and seventh columns of the read image data D.
When _the pixel information belongs to the _column . , the eighth column, ..., the lines d ₀ to d ₃ and the fourth column of the dither matrix
The four threshold values 30 in the column are connected to each other. In order to make the explanation easier to understand, the above explanation is based on an example in which pixels of image information read from a manuscript are dithered using a 4 x 4 dither matrix, but the invention is not limited to this, and a threshold value higher than that is used. Of course, the dither processing may be performed using a dither matrix having a size of, for example, an 8×8 dither matrix. In this case, eight comparators are provided,
It will be clear that the dither data output will be 8 bits. Next, as another specific example of the dither circuit 10, the RAM 32 shown in FIG. 5 can be used. In Figure 5, each read manuscript information is expressed in 64 gradations, and the dither matrix is 8 x 8.
An example is shown in which there are three threshold values. The RAM 32 contains 6-bit gradation data a expressed in multiple gradations and a 5-bit block select signal for selecting a dither threshold depending on the type of document (for example, photo, text, a mixture of these, etc.). b
enters. Then, the RAN 32 outputs 8-bit dither data _c0 to _c7 . RAN32
uses the 6-bit gradation data and 5-bit block select signal as addresses, performs the same processing as explained in FIG. 4, and outputs binary dither data in 8 bits. Next, the configuration and operation of the reduction processing device 12 (see FIG. 1) will be explained. FIG. 6 shows an embodiment of the reduction processing device 12 made of PAL.
In the figure, 40 is a 3-digit dither phase counter, 42 is a sequence decoder having functions to be described later, and _S0 to _S7 are the dither circuit 10 or RAN32.
As input, dither data c ₀ to c ₇ which is the output of A
Select either the terminal or the B terminal signal. The selectors U ₀ -U ₇ and U ₈ , U ₉ are D flip-flops (hereinafter abbreviated as DF and F) which latch the input signal of the D terminal with a clock. A reduction code is input to the dither phase counter 40. This reduced code consists of 2 bits and is defined as shown in Table 1, for example. In other words, when the scaling code is "00",

[Table] When the magnification code is ``01,'' it has the function of ``normal magnification,'' and when the magnification code is ``10,'' it has the function of ``enlargement.'' Note that the reduction code "11" is not necessary, so it is not used. Next, the scaling code is

[Table] When input to data 40, dither phase counter 4
0 performs a count-up function as shown in Table 2. That is, when the reduction code is "00", "01" and "10", the dither phase counter 40 is "0" and "+1" for each clock, respectively.
and counts up "+2". The sequence decoder 42 receives the reduced code and 3 which is the output of the dither phase counter 40.
A bit dither phase signal e is input. Then, the sequence decoder 42 outputs outputs Y ₀ to Y ₇ and Fi, Wi as shown in Table 3 according to these input signals. In Table 3, X indicates that all outputs Y ₀ to Y ₇ and Fi, Wi are 0. Also, Y ₀ ~
Y ₇ , Wi and Fi indicate that the output is 1, and other outputs not noted are 0.

[Table] The outputs Y ₀ to Y ₇ in Table 3 are S ₀ to _{S 7} respectively.
When the outputs Y ₀ to Y ₇ are 0, S ₀ to S ₇ select terminal A, and on the other hand, when the outputs Y ₀ to Y ₇ are 1, S ₀ to S 7 are selected. ₇ selects terminal B. Further, _U8 has a function of processing fractions generated during scaling, and _U9 has a function of outputting a strobe signal when latching of eight D-FFs _U0 to _U7 is completed. Next, the operation of the reduction processing device 12 shown in FIG. 6 will be explained. First, the operation when the magnification is 1, that is, the same magnification will be explained. When the image is at the same magnification, the magnification code is "01", and the magnification code is input to the dither phase counter 40 and the sequence decoder 42. Therefore, the dither phase counter 40 counts up by +1 every time one clock is input. now,
Before the clock is input, the count value of the dither phase counter 40 is 0, and its output, dither phase e, is "000". For this reason,
As is clear from Table 3, only the output _Y0 of the sequence decoder 42 becomes 1, the other outputs become 0, the selector _S0 selects the B terminal, and the other selectors _S1 to _S7 select the A terminal. Selected. When the first clock inputs, D-FFU ₀
latches the dither signal _c0 , which is the output of the selector _S0 . On the other hand, since each of D- _FFU1 to _U7 relatches its own output, there is no change in the latch data. Also, due to this clock, the dither phase counter 40 counts up by +1, and the dither phase d becomes "001". As a result, only the output Y ₁ of the sequence decoder 42 becomes 1, and the other outputs Y ₀ , Y ₂ .
_Y7 becomes 0. Note that here, since no end processing is performed, F ₀ =0. Therefore, only selector _S1 selects the B terminal, and the other selectors select the A terminal. As a result, when the second clock is input, the dither signal _c1 is latched in D-FFU ₁ , and the latched data of other D-FFs remain unchanged. The above operation is performed every time the clock is input, and as is clear from Table 3, when the seventh clock is input, the outputs Y ₇ and Wi become 1, so
D-FFU ₇ latches dither signal _c7 , and D-FFU ₉ latches 1. For this reason, D-
A strobe signal is output from FFU ₉ . When the strobe signal is output, the eight latch data D- _FFU0 to _U7 can be taken out in parallel. Next, when the eighth clock is input, the value of the dither phase counter 40 returns to "000".
Return to the initial state described above. Thereafter, the above operations are repeated in synchronization with the clock. The above-mentioned equal-magnification operation will be specifically explained using FIG. 7 as follows. In addition, Fig. 7 a, b
show read image data D' and 8×8 dither matrix F similar to FIGS. 2a and 2b, respectively. When the operation of the circuit shown in FIG. 6 is started, before the clock is input, the leftmost pixel data a ₁₁ in the first column of the read image data D' is dithered by the corresponding dither threshold b ₁₁ . Since the processed data C ₀ is input to D-FFU ₀ through selector S ₀ ,
The first clock changes the data _C0 to D-FF.
Latched to U ₀ . In the second clock,
Data c 1 obtained by dithering the second pixel data a ₁₂ from the left in the first column of the read image data D' using _the corresponding dither threshold b ₁₂ is latched in D-FFU ₁ . Thereafter, each time the clock is input, the third, fourth, etc. from the left in the first column of the read image data D', etc.
The data c ₂ , c ₃ , ... c ₇ obtained by dithering the 8th pixel data a ₁₃ , a ₁₄ , ... a ₁₈ using dither thresholds b ₁₃ , b ₁₄ , ... b ₁₈ are D- FFU ₂ , U ₃ ,
...Latched by U ₇ . When data c ₇ is latched to D-FFU ₇ , a strobe signal is output from D-FFU ₉ , and data c ₀ to c ₇ latched to D-FFU ₀ to U ₇ are not shown. Transferred to the line buffer in parallel. Thereafter, similar operations are repeated, so that conventional dither processing is performed. Next, the reduction processing device 12 in the case of reduction to 1/2
The operation will be explained. At this time, the reduction code input to the dither phase counter 40 is
Enter the codes "00" and "01" alternately. That is, as is clear from Tables 1 and 2,
The "Mabiki" and "Same size" functions are performed alternately,
The phase counter 40 counts up to 0.
and +1 are repeated alternately. Initially, the reduction code ``01'' is selected, and the dither phase output from the dither phase counter 40 is ``000'', so when the first clock is input, it is clear from Table 3. As such, dither data _c0 is latched to D- _FFU0 . For example, in the example of FIG. 7, this dither data c ₀ is the leftmost pixel data a 11 of the first column of the read image data D', and the pixel data a ₁₁ of the leftmost column of the dither matrix shown in FIG. 7 b. This corresponds to dither data obtained by applying the threshold value b ₁₁ at the leftmost end of the eye. Next, the scaling code is changed to "00". At this time, the output dither phase of the dither phase counter 40 is "001", but since the outputs Y ₀ to Y ₇ of the sequence decoder 42 are all 0,
On the second clock, all D- _FFU0 through _U7 relatch their data. For this reason,
These latch data do not change. In other words, the signal obtained by dithering the second pixel data _a12 from the left in the first column of the read image data D' in FIG. 7a is not latched to any of D- _FFU0 to _U7 . , will be thinned out. Also, the dither phase counter 40 does not count the second clock. Next, the scaling code is changed to "01". At this time, the dither phase is still "001", and only the output _Y1 of the sequence decoder 42 is 1. Therefore, the third clock latches dither data _c1 to _U1 . This dither data c ₁ is, for example, the third pixel data a ₁₃ from the left in the first column of the read image data D' in FIG. This is data that has been dithered using the second threshold value _b12 . Next, the scaled code is changed to "00" again. At this time, the dither phase is "010", but the output Y ₀ to Y ₇ of the sequence decoder 42
are all 0, and the dither data _c0 to _c7 are not latched to any of the corresponding D- _FFU0 to _U7 .
Therefore, the signal obtained by dithering the fourth pixel data _a14 from the left in the first column of the read image data D' in FIG. 7a is not latched to any of D- _FFU0 to _U7 . Thinned out. When the above operation is repeated, every other pixel of the read image data D' is sequentially compared with the threshold value of the dither matrix, and all of D-FFU ₀ to _{U 7} are filled with dither data c ₀ to c. ₇ is latched. Each time the dither data _c7 is latched to the D-FFU ₇ , a strobe signal is output from the D-FFU ₉ , and the dither data _c0 to _c7 latched to the D-FFUs ₀ to _U7 are not shown. Not transferred to line buffer. Therefore, the data transferred to the line buffer has 1/2 the number of pixels of the original read image data D', and the dither data of 1 to 2 pixels has the regularity of the dither matrix F. Since the image quality is maintained, it is possible to obtain a good 1/2 reduced pixel that solves the drawbacks of the conventional device. Next, the operation of enlarging the read image data D' by two times will be explained. At this time, the reduction code input to the dither phase counter 40 in FIG. 6 is fixed at "10". When the reduction code is "10", as is clear from Table 2 above, the dither phase counter 40 counts up by +2 per clock. Therefore, when the first clock is input, the output Y ₀ of the sequence decoder 42
and Y ₁ becomes 1, and Y ₂ to _{Y 7} become 0. Therefore, dither data c ₀ and c ₁ are D-FFU _0.
Latched to U ₁ . This dither data c ₀ and c ₁
Considering FIG. 7 as an example, the read image data
The leftmost pixel data a ₁₁ in the first column of D′ is the threshold value b ₁₁ in the first column of the dither matrix F in the figure b,
b This is the dithered data compared to ₁₂ .
In other words, the pixel data a ₁₁ of the read image data D'
is latched to D-FFU ₀ and U ₁ as two dither data. Next, when the second clock inputs,
Since the dither phase e which is the output of the dither phase counter 40 is "010," the third and fourth U ₂ and U ₃ latches dither data c ₂ and c ₃ , respectively. This dither data c ₂
and c ₃ is the second pixel data a ₁₂ from the left in the first column of the read image data D' to the third and fourth thresholds from the left in the first column of the dither matrix.
Dithered signal compared to b ₁₃ and b ₁₄ . The above operations are repeated. And D
−At the same time as the dither signal is latched to FFU ₇ ,
A strobe signal is output from D-FFU ₉ , and D
-The dither signal latched to FFU ₀ to U ₇ is
It is transferred to a line bus (not shown). Therefore, the data transferred to the line buffer has twice the number of pixels as the original read image data D', and the dither data with twice the number of pixels maintains the regularity of the dither matrix F. This results in a good 2x enlarged image. The operations of equal size, 1/2 reduction, and 2x enlargement have been described above, but according to this embodiment, by selecting the combination of the reduction codes, it is possible to obtain an arbitrary reduced or enlarged image. (Effects of the invention) As is clear from the above explanation, according to the present invention, the following effects are achieved. (1) Since dither processing for reduction or enlargement can be performed without impairing the regularity of dither processing, good reduced or enlarged images can be obtained. (2) Despite the simple configuration, the complex processing described in (1) above can be performed. (3) Since a reduction code and a clock signal are appropriately given to the dither phase counter according to each input pixel, it is possible to easily convert image data to any magnification.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.
Figure 2 is an explanatory diagram of read image data and a 4x4 dither matrix, Figure 3 is a time chart of the output signal of the reduction processing device in Figure 1, and Figure 4 is an implementation of the dither circuit in Figure 1. FIG. 5 is a block diagram showing another embodiment of the dither circuit, and FIG. 6 is a block diagram showing another embodiment of the dither circuit.
The figure is a block diagram showing an embodiment of the reduction processing device shown in Fig. 1, Fig. 7 is an explanatory diagram of read image data and an 8x8 dither matrix, and Fig. 8 is a diagram for explaining dither processing. be. 10... dither circuit, 12... reduction processing device,
32...RAM, 40...Dither phase counter, 42...Sequence decoder.

Claims (1)

[Claims for Utility Model Registration] Image data having multiple gradations is input for each pixel, and information indicating the column of the dither matrix to which the pixel belongs is input, and the multi-gradation data of the pixel is matched. dither data output means 10 which compares each of the rows of the dither matrix with the threshold values and outputs the comparison results in parallel as binary data; inputs the reduction code and a clock signal for counting; A dither phase counter 40 that performs a counting operation according to the reduced code in response to the signal, and a sequence decoder that outputs a select signal in response to the reduced code and the dither phase corresponding to the output of the dither phase counter. 42, and a plurality of selectors (S0
~S7), a plurality of latch means (U0~U7) for latching the signal selected by the selector, and a circuit for detecting that the signal is latched in all of the latch means and extracting the output in parallel. a synchronization output means U9 for outputting a synchronization signal; and a synchronization output means U9 for outputting the reduction code and counting clock signal to the dither phase counter 40 in synchronization with the input of image data of each pixel according to the scaling factor that changes the size of the image. 1. A circuit for enlarging/reducing halftone data using a dither method, characterized in that it is provided with a control means for giving