JP2636396B2 - Image reduction conversion method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reduction conversion for outputting a digital image in which one pixel is represented by one bit in black and white binary to an image output device capable of multi-value display. In this case, the present invention relates to an image reduction conversion method for obtaining a reduced conversion image with less image quality degradation by converting the image into a multi-valued image.

[Conventional technology]

Conventionally, as a reduction conversion method of a digital image (monochrome binary image) in which one pixel is represented by one bit in black and white binary,
The simplest method is a method of appropriately thinning out rows and columns of an original image to values required in a converted image, and is adopted as a reduction conversion method for displaying an image on a display such as a personal computer. This method is simple in processing, and is used as a simple method, for example, when it is desired to know only the layout using a word processor or the like. However, it is not appropriate to read the contents of a document because image quality is significantly degraded due to occurrence of cuts or crushing. On the other hand, as a reduction conversion method from a black and white binary image to a black and white binary image, SP
Method C (Proceedings of the 7th Annual Conference of the Institute of Image Electronics Engineers of Japan,
1975) and the area discrimination method (IEICE Technical Report RPL81-92) have been published. In these conversion methods, there is a disadvantage that the image quality is deteriorated due to breakage due to disappearance of a thin black line and collapse due to disappearance of a white thin line. On the other hand, the TP method (IEICE Technical Report ED84-26, 1984), which determines thin lines to solve these drawbacks and prevents them from deteriorating image quality by storing them, has also been announced. I have. Even this method does not eliminate cuts and crushes, and thus is insufficient as a reduction conversion method for outputting to an image output device capable of multi-value display such as a personal computer display. Furthermore, as a reduction conversion method for outputting to an image output device capable of multi-value display that prevents cuts and crushes, when a converted image is mapped to an original image, the values of surrounding original pixels with respect to the conversion pixel of interest are added. A method has been considered in which multi-valued data is used and this is used as the value of the converted pixel.

In this method, when the relationship between the original image and the converted image is as shown in FIGS. 7 (a) and 7 (b), the reduction ratio (vertical direction B /
(A, horizontal direction C / D), the position of the converted pixel and the reference pixel are obtained by calculation. As shown in FIG. 7, the values of the reference pixels around the conversion pixel of interest are added with the black pixel being “1” and the white pixel being “0”. In FIG. 7A, the added values of the reference pixels are five types of "0", "1", "2", "3", "4", and in FIG. 7B, "0", "1". ",“ 2 ”,“ 3 ”,“ 4 ”,“ 5 ”,“ 6 ”,“ 7 ”,
There are 10 types, “8” and “9”. A converted image with high quality can be obtained by displaying with a gradation value corresponding to the added value of the reference pixels.

In this conversion method, the added value of the reference pixels is the number of reference pixels +
There is a drawback that the data amount increases as compared with the case where the data becomes one-level multi-valued data and is reduced to binary data.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks in a reduced conversion method that uses the values of a plurality of surrounding original pixels around a converted pixel of interest when a reduced converted image is mapped to an original image. An object of the present invention is to provide an image reduction conversion method in which a small amount of high-quality multivalued reduced conversion images can be obtained at a high speed with a simple circuit configuration and a small number of operations.

[Means for solving the problem]

The invention of the image reduction conversion method according to the present invention includes a step of obtaining an addition value of a value of a reference pixel determined according to a reduction ratio;
There is a step of converting one pixel smaller than the number of digits M required when the sum of the reference pixels obtained in this way is represented by a binary number into N-plane data represented by one bit. Step 4 of converting the data into N-plane data expressed in bits is performed by converting each digit of the added value up to the number of digits M required when the added value of the reference pixel is expressed in a binary number, by one byte length determined by the order of the converted pixels or A process of converting one pixel into M-plane data represented by one bit by extracting one word-length data to a predetermined position, and converting the data of the M-plane into an N-plane represented by one bit less than M by one bit Logical operation process.

[Action]

According to the present invention, it is possible to obtain a high-quality converted image with a smaller amount of data than the conventional reduced conversion to a multi-valued image.
Furthermore, a converted pixel can be obtained at a high speed with a simpler circuit configuration and a small number of operations.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. However, here, for simplicity of explanation, the reduction ratios in the horizontal direction and the vertical direction are the same, that is, B / A. DATA is the number of reference pixels corresponding to the reduction ratio when the converted image is mapped to the original image,
Shows the position data of the reference pixel consisting of the reference pixel processing unit and the reference pixel group interval data, 1 is a shift register 1A,
The means for adding the value of the reference pixel consisting of the mask circuit 1B and the adding circuit 1C, the number of bits required when the added value of the reference pixel consisting of the shift register 2A, the mask circuit 2B and the OR circuit 2C is expressed in a binary number Means for converting each bit of the added value of the reference pixel up to M into M plane data consisting of one bit per pixel, 3 converts the data of the M plane consisting of one bit of one pixel into data of N planes smaller than M 4 is a memory for an added value of a reference pixel having an initial value of 0, 5 is a memory for data of an M plane with an initial value of 0, and 6 is a memory for data of an N plane.

Of the reference pixel position data, the number of reference pixels indicates the number of pixels to be added in the horizontal direction and the vertical direction. Has three pixels as a unit of addition. The number of reference pixels may be determined according to the relationship shown in FIG.

The reference pixel processing unit is a processing unit for adding reference pixels. When converting the sum of the reference pixels into multi-level data of the M plane and performing processing in units of 1-byte length, the reference pixel processing unit may be the number A of the denominator of the reduction ratio. At this time, the number of added values of the reference pixels corresponding to the converted pixels is 8 × (the number B of numerators of the reduction ratio). When processing is performed in units of one word, the reference pixel processing unit is (numerical number A of the denominator of the reduction ratio) × (one word length / 8).

The reference pixel group interval data is data indicating the overlap of a group of reference pixels (reference pixel group). When the reduction ratio and the reference pixels have the relationship shown in FIG. . At a reduction ratio of a non-integral fraction, values of 0 and −1 are taken, and repetition is performed at a period determined by the numerator B of the reduction ratio.
When adding reference pixels, the addition is started from a new reference pixel at the reference pixel group interval 0, while the addition is started from the immediately preceding reference pixel at −1.

A reduction conversion method according to the present invention will be described for a case where processing is performed with 1-byte data at a reduction ratio of 2/5.

The positional relationship between the reference pixel and the converted pixel is the same as in FIG. 7 (b). At this time, as the reference pixel position data, the number of reference pixels in the horizontal direction and the vertical direction is 3, the reference pixel processing unit is 5 bytes, and the reference pixel interval is a value obtained by repeating 0 and -1 each time.

The input data is described below assuming that the left pixel in FIG. 7 is stored from the right bit as shown in FIG.

In the data of FIG. 3, P ₁₁₁ , P ₁₁₂ and P ₁₁₃ are converted pixels Q ₁₁₁
, P ₁₁₃ , P ₁₁₄ , and P ₁₁₅ are reference pixels of the conversion pixel Q ₁₁₂ , P ₁₁₆ , P ₁₁₇ , and P ₁₁₈ are reference pixels of the conversion pixel Q ₁₁₃ , P ₁₁₈ , and P
₁₂₁ and P ₁₂₂ are reference pixels of the conversion pixel Q ₁₁₄ , P ₁₂₃ , P ₁₂₄ and P ₁₂₅ are reference pixels of the conversion pixel Q ₁₁₅ , and P ₁₂₅ , P ₁₂₆ and P ₁₂₇ are conversion pixels Q
Reference pixel _116, reference pixel P _128, P _131, reference pixel P ₁₃₂ is converted pixel _{Q 117, P 132, P 133} , P 134 is converted pixel Q _118,
P ₁₃₅ , P ₁₃₆ , P ₁₃₇ are reference pixels of the conversion pixel Q ₁₂₁ , P ₁₃₇ , P ₁₃₈ ,
Reference pixel P ₁₄₁ is converted pixel _{Q 122, P 142, P 143} , P 144 is the reference pixel P _144, P _145, P ₁₄₆ is a reference pixel of the converted pixel Q ₁₂₄ of the converted pixel _{Q 123, P 147, P 148} , P ₁₅₁ is the reference pixel of the conversion pixel Q ₁₂₅ , P
₁₅₁ , P ₁₅₂ , P ₁₅₃ are reference pixels of the conversion pixel Q ₁₂₆ , P ₁₅₄ , P ₁₅₅ , P
₁₅₆ reference pixels converted pixel _{Q 127, P 156, P 157} , P 158 is a reference pixel of the converted pixel Q _128.

 Next, the operation of the embodiment shown in FIG. 1 will be described.

First, the sum of the reference pixels is calculated. Description on a ₁₁ additional values to take into addition value memory 4 of the reference pixels of the reference pixel, a
₁₂ , a ₁₃ , a ₁₄ , a ₁₅ , a ₁₆ , a ₁₇ , a ₁₈ , a ₂₁ , a ₂₂ , a ₂₃ , a ₂₄ , a ₂₅ ,
They are represented by a ₂₆ , a ₂₇ and a ₂₈ .

1st byte of data per line is added to reference pixel adding means 1
To enter. Initially, the reference pixel interval data is 0. Since the value is 0, the values of P ₁₁₁ , P ₁₁₂ and P ₁₁₃ are added to a ₁₁ . This addition is performed by the following operation. Removed shift register 1A in the rightmost bit P ₁₁₁ as a 1-byte-length data by the mask circuit 1B, is added to a ₁₁ by the adding circuit 1C. next,
Shift 1 bit to the right with shift register 1A to set _P112 as first
Th moved to bit positions, similarly removed P ₁₁₂ by the mask circuit 1B, it adds to aP ₁₁ by the adding circuit 1C. Similarly, it added to a ₁₁ removed P _113. This completes the process for three reference pixels. Since the reference pixel group interval is following -1, the value of the P _113, which is one before the reference pixel P _114, P ₁₁₅ is added to a ₁₂ by the same operation as described above. Next, since the reference pixel group interval is 0, the values of P ₁₁₆ , P ₁₁₇ and P ₁₁₈ are added to a ₁₃ by the same operation as described above. Next, if the reference pixel group interval is-
For 1, it adds the value of P ₁₁₈ to a _14. This ends the first byte of data.

The second byte of the data input to the adding means 1 of the reference pixel, P _121, P ₁₂₂ to end the addition to the reference pixels corresponding to three processing to a _14. Thereafter, the same process is repeated to input the data of the fifth byte to obtain an added value of the reference pixels for the five bytes of the first line.

As mentioned above, a ₁₁ by processing to input data for each _{byte, a 12, a 13, a} 14, a 15, a 16, a 17, a 18, a 21, a
_{22, a 23, a 24,} a 25, a 26, a 27, a reference pixel processing unit is about a ₂₈ can be obtained 5-byte first line of the sum.

Subsequently, similarly, 5 bytes on the second line and 5 bytes on the 3rd line are sequentially input and added to the sum of the reference pixels up to that time.

In this way, an added value of 2 × 8 reference pixels as shown in FIG. 4 is obtained from the data of 5 bytes and 3 lines shown in FIG.

Second, the added value of the reference pixel is extracted for each digit represented by a binary number and converted into plane data. 2 planes
The number of digits must be up to M, which is required when expressed in base numbers. When the number of reference pixels 4 is 3, the maximum value of the sum of the converted pixels is 9, and M is 4. 8 obtained by the reference pixel adding means 1
Two sets of the added values are converted into two sets of 1-byte length data for four planes. Description on E ₁₁ the memory of the 1-byte length data, E _12, and _{E 13, E 14, E 21} , E 22, E 23, E 24.

The added values of the reference pixels are sequentially input one by one from the reference pixel added value memory 4 to the means 2 for converting the added values of FIG. 1 into M plane data. a Shift register 2A and mask circuit 2B from 1-byte binary representation “00000101” of value 5 of ₁₁
And the following processing is performed by the OR circuit 2C. a ₁₁
1 digit "1" in the first bit position of the 1-byte length data, taking extraction E ₁₁ ORed by the mask circuit 2B. Then, bit-shifts to the right the second digit "0" in the shift register 2A, after moving to the first position of the 1-byte length data, taken out by the mask circuit 2B, take the E ₁₂ and the logical sum. Similarly, the third digit “1” is extracted, and OR is calculated with E ₁₃ ,
Take the E ₁₄ and the logical sum is taken out the first digit "0".

The value of a ₁₂ "00000011" is taken out by the shift register 2A and the mask circuit 2B to the second bit position, in the OR circuit 2C
The logical sum of E ₁₁ , E ₁₂ , E ₁₃ and E ₁₄ is calculated. Similarly, a ₁₃ is the third bit position, a ₁₄ is the fourth bit position, a ₁₅ is the fifth bit position, a ₁₆ is the sixth bit position, a ₁₇
Is the seventh bit position, a ₁₈ is sequentially extracted to the eighth bit position, and E ₁₁ , E ₁₂ , E ₁₃ , and E ₁₄ for one byte and four planes shown in FIG. 5A are obtained. . obtain _{E 21, E 22, E 23} , E 24 shown in the figure the same for a ₁₂ ~a _28.

Third, the logical operation means 3 in FIG.
A case where the data is converted into plane data will be described. Description on D ₁₁ two sets of 1-byte length two planes worth data, D _12, D _21, D
₂₂ .

1 byte length of 4 planes worth data E ₁₁ to E ₁₄ and input to the logic operation unit 3, FIG. 6 (a) 2-plane of data D ₁₁ shown in FIG. 5 (b) in the relationship shown in, D ₁₂ Get. In this case, the logical operation means 3 only needs to be configured to realize the logical expression shown by the following expression.

However, the + symbol represents a logical sum, the * symbol represents a logical product, and the ￣ symbol represents a complement.

Similarly obtain D _21, D ₂₂ also E ₂₁ to E _24.

In addition, in the case where data for two planes as shown in FIG. 6B is used, the configuration may be changed so that the logical expression of Expression (1) becomes the following expression. That is, by changing the logical operation means 3, data for any two planes other than FIG. 6 can be obtained.

In the vertical direction, since the reference pixel group interval repeats the value of 0 and −1 each time, the use of the last line of the previous three lines of data as the first line is performed each time. It should be repeated. In this way, by converting all original pixels in the horizontal and vertical directions as reference pixels, a converted image of multi-level data for two planes, in which one pixel with a reduction ratio of 2/5 is represented by one bit, is obtained. be able to.

For example, a memory for displaying image data, such as a personal computer, has a configuration of a plurality of planes with one bit per pixel, and when a specific display color of a display is determined by a look-up table, the image data display is performed. The data for the two planes is transferred to the memory for the bus via the bus, and white and black and the intermediate color 2
You can decide the type.

Although the order of the original pixels has been described assuming that the right end is the first pixel, when the left end is the first pixel, the input data as the reference pixel processing unit is reversed in calculating the sum of the reference pixels. Then, the same processing can be performed.

〔The invention's effect〕

As described above, according to the present invention, when a black-and-white binary digital image is reduced and displayed on an output device capable of multi-level display, the value of nx around the conversion pixel of interest is used as the value of the conversion pixel.
An addition value of n reference pixels is calculated, and the value is converted into data of M plane in which one pixel is represented by one bit corresponding to the number of digits M required when the value is represented by a binary number. Since the data of the M plane of 1 bit per pixel is data of the N plane in which 1 pixel less than M is represented by 1 bit by a defined logical operation, a reduced converted image of good quality with a small data amount is obtained. With a simple circuit configuration, the number of operations is small, and high speed can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a diagram showing an example of the relationship between the reduction ratio and the number of reference pixels, and FIG. 3 is a diagram for explaining the flow of the reduction conversion method of the present invention. FIG. 4 shows an example of data of 5 bytes and 3 lines of a part of a monochrome binary digital image, FIG. 4 shows an addition value of a reference pixel and its binary representation in the data example of FIG. 3, and FIG. FIG. 5B is a diagram showing multi-valued data obtained by converting an added value of pixels into four planes of one bit per pixel, and FIG. 5B is a diagram showing multi-valued data of two planes of one bit per pixel obtained by a logical operation means; 6 (a) and 6 (b) are explanatory diagrams of an example of a logical operation means, and FIG. 7 is a diagram for explaining a conventional reduction conversion method in which an added value of a reference pixel is converted to multi-value data. In the figure, 1 is a reference pixel adding means, 1A is a shift register,
1B is a mask circuit, 1C is an addition circuit, and 2 is M plane data consisting of one bit per pixel for each bit of the reference pixel addition value up to the number M of bits required when the addition value of the reference pixel is expressed in binary. Conversion means, 2A is shift register, 2B
Is a mask circuit, 2C is a logical sum circuit, 3 is a logical operation means, 4
Is a memory for addition value, 5 is a memory for plane data, 6
Is a data memory for N planes.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-83587 (JP, A) JP-A-60-163080 (JP, A) JP-A-57-185078 (JP, A) JP-A-60-163 8892 (JP, A)

Claims (1)

(57) [Claims] A digital image in which one pixel is represented by one bit is reduced and converted at an arbitrary magnification and reduced and displayed on an output device capable of multi-value display. Is mapped to the original image before conversion, the reduction conversion method of the image, in which the value of the conversion pixel of interest is obtained by referring to the values of the original pixels of a plurality of surrounding original images around the conversion pixel, Summing the values of all original pixels inside the horizontal and vertical directions defined by the reference pixel values determined according to the above, and obtaining the added value of the obtained reference pixels in a binary system An M plane in which one pixel is represented by one bit by extracting each digit of the added value to a predetermined position of one byte length or one word length data determined by the order of the conversion pixel up to the number of digits M required when represented by Converting the data into N representing the data of lane one pixel by one bit
Convert to plane data (N is a positive integer less than M)
And a logical operation step of obtaining multi-value display data from N-plane data.