JP2658346B2 - Parallel image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel image processing apparatus that uses a scanner or a TV camera to process digital binary images obtained from images such as drawings in parallel, and more particularly, to a digital binary image processing apparatus. The present invention relates to a parallel image processing device that performs high-speed processing of a connected graph of images.

(Prior art)

Conventionally, in order to increase the processing speed of an image processing device,
Architectures such as a local parallel system, a pipeline system, a multiprocessor system, and a fully parallel system have been proposed.

Among them, the completely parallel method is similar to the processing by human visual cells, and is a parallel pixel processing method in which processing elements (processor elements) equal to the number of pixels of a processed image are used and outputs of respective pixels are calculated simultaneously. Thus, the highest speed is expected.

This type of device is discussed in, for example, "Journal of the Institute of Electronics and Communication Engineers, vol. 67, No. 1, pp. 90-98".

On the other hand, as a method of processing a binary image, a method of converting a binary image into a connected graph and performing processing on the connected graph has been proposed.

In this method, first, a center line image obtained by thinning the binary line graphic data is converted into a graph in which pixels on the center line are set as nodes and sides between adjacent nodes are sides and stored. Next, the graph obtained by removing oblique sides from the obtained graph by a predetermined conversion rule and further removing horizontal and vertical sides from the removed graph by a predetermined conversion rule is changed to a two-stage process. Repeat until no more. further,
In the graph thus obtained, a shaping process for moving the intersection of the side to the node is performed. Finally, nodes (feature points) whose number of connected edges is not 2 are extracted from the graph thus obtained, and the node sequence obtained by tracking between the two feature points is linearly approximated and converted into a vector sequence. .

As a result, the center line image obtained by thinning the input binary image is converted into vector information that is faithful to the shape of the original image and has a small amount of data, thereby speeding up processing such as graphic recognition. .

This method is described in, for example, “Japanese Patent Application No. 62-1728.
No. 75 ".

[Problems to be solved by the invention]

In the above prior art, when processing a connected graph obtained from a binary image, parallel processing can be executed for each edge. However, since there is no one-to-one correspondence between pixels and edges, an existing relationship is obtained. There is a problem that it cannot be processed by the parallel image processing device.

In addition, in the connected graph processing, the types of edges that can be processed in parallel differ depending on the processing content. Therefore, when processing elements are assigned to each edge and processed in parallel, there is a problem that the number of idle processing elements increases and efficiency is poor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a parallel image processing apparatus which can solve such problems and can process a connected graph of a digital binary image at high speed.

[Means for solving the problem]

In order to achieve the above object, a parallel image processing apparatus according to the present invention is configured such that one pixel constitutes a digital binary image.
Means (image memory unit) for accumulating digital binary images on a pixel-by-pixel basis in a parallel image processing apparatus that allocates a number of processing elements and simultaneously performs the same processing on the processing elements
And operating the processing elements in parallel, inputting the state of the pixel corresponding to each processing element and the pixels in the vicinity of the pixel,
A means for converting a pixel into a partial graph corresponding to one-to-one to obtain a connected graph (image-graph conversion unit), and a means for storing the connected graph in units of a partial graph (graph memory unit)
Means for operating the processing elements in parallel, inputting a subgraph corresponding to each processing element and a subgraph in the vicinity thereof, and converting the corresponding subgraph according to a predetermined rule (graph-graph conversion unit) It is characterized by having:

[Action]

In the present invention, the graph-graph conversion unit includes processing elements equal to the number of subgraphs, and there is a one-to-one correspondence between pixels and subgraphs.

As a result, digital 2
The connected graph processing of the value image can be executed at high speed.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is an explanatory diagram showing conversion from a digital binary image to a connected graph in one embodiment of the present invention.

In FIG. 2, (a) is a digital binary image to be processed, and (b) is a pixel having a value 1 in the digital binary image of (a), where a node represented by a black circle is placed, and an adjacent pixel having a value 1 is placed. It is a connected graph in which an edge shown by a solid line is placed. (C) shows the conversion from the digital binary image to the subgraph (6,4) by the processing element (6,4). Each processing element corresponds to a pixel of the digital binary image.

In the present embodiment, the processing of the processing element (6, 4) corresponding to the pixel at 6 rows and 4 columns is shown as (c).

That is, the values of pixels at 6 rows and 4 columns, 6 rows and 5 columns, 7 rows and 4 columns, and 7 rows and 5 columns in (a) are input, and whether or not a node exists at 6 rows and 4 columns of the connected graph is determined. , Whether there is an edge between the node at 6 rows and 4 columns and the node at 6 rows and 5 columns,
Whether an edge exists between the node at 6 rows and 4 columns and the node at 7 rows and 4 columns, and an edge exists between the node at 6 rows and 4 columns and the node at 7 rows and 5 columns Whether or not there is an edge between the node at 6 rows and 5 columns and the node at 7 rows and 4 columns is output.

The existence of a node is determined depending on whether the value of the corresponding pixel is 1. The existence of an edge between two nodes is determined by whether the values of the pixels corresponding to these nodes are both 1.

Further, in this embodiment, since the number of processing elements in the means for converting a digital binary image into a graph (image-graph conversion unit) is equal to the number of pixels, the number of obtained partial graphs is also the number of pixels of the digital binary image. be equivalent to. Therefore, the subgraph output from each processing element is identified by the position of the processing element. For example, a subgraph output from a processing element located at 6 rows and 4 columns is a subgraph (6,
Call 4). Moreover, there is a feature that there is no overlapping edge or node between the obtained subgraphs.

FIG. 3 is an explanatory diagram showing processing of each processing element when converting a connected graph into another connected graph in one embodiment of the present invention.

In FIG. 3, black circles represent input or output nodes, and solid lines represent input or output sides.
Each processing element corresponds to each subgraph, inputs a subgraph corresponding to each processing element and a subgraph in the vicinity thereof, and obtains and outputs a new state of the corresponding subgraph according to a rule according to processing.

In this embodiment, the input and output of the processing element corresponding to the subgraph (i, j) are shown. That is, the processing elements are the corresponding subgraph (i, j) and its neighboring subgraphs (i + 1, j), subgraph (i + 1, j + 1), subgraph (i, j + 1), and subgraph (i−1). , j + 1), subgraph (i−1, j), subgraph (i−1, j−1), subgraph (i, j−1), and subgraph (i + 1, j−1).
A new state of the subgraph (i, j) is obtained by a rule according to the processing content.

FIG. 1 is a configuration diagram of a parallel image processing apparatus according to an embodiment of the present invention, and FIG. 4 is a logic circuit diagram of processing elements constituting an image-graph conversion unit of FIG.

1, reference numeral 11 denotes a processing unit including a CPU and a memory, 12 denotes an input device such as a scanner, 13 denotes an output device such as a CRT, 100 denotes an image memory unit, 101 denotes an image-graph conversion unit, and 102 denotes a graph. A memory unit 103 is a graph-graph conversion unit, and 104 is a control unit.

The image memory unit 100 stores a map, a drawing, and the like as a digital binary image, and is supplied with a digital image from the input device 12. Further, reading from the image memory unit 100 can be performed simultaneously and independently for all pixels in pixel units. In order to perform such parallel output, for example, if the size of a binary image is M × N, the image memory unit 100 is configured using an M × N bit register.

The image-graph conversion unit 101 is a unit that converts the digital binary image stored in the image memory unit 100 into a connected graph as shown in FIG. The image-graph conversion unit 101 has processing elements equal to the number of pixels of the digital binary image, and operates these processing elements as shown in FIG. 2 (c). Further, in order to perform a fixed process, the image-graph conversion unit 10
One processing element includes, for example, four AND circuits as shown in FIG. This is a processing element that creates a subgraph (i, j), and includes a pixel (i, j) and a pixel (i, j + 1),
Pixel (i, j) and pixel (i + 1, j), Pixel (i, j) and pixel (i + 1, j + 1), Pixel (i, j + 1) and pixel (i + 1, j)
Are input to the AND circuit, and the nodes (i,
j), the existence of an edge between the nodes (i, j) and (i, j + 1), the existence of an edge between the nodes (i, j) and (i + 1, j),
The presence / absence of a side between the node (i, j) and the node (i + 1, j + 1) and the presence / absence of a side between the node (i, j + 1) and the node (i + 1, j) are output.

Further, the graph memory unit 102 includes an image-graph conversion unit 10.
1, the input of the graph-graph conversion unit 103, or (and)
This section stores a graph to be output, and supplies a graph of a processing result to the output device 13. In addition, the graph memory unit 10
Reading and writing to 2 can be performed simultaneously and independently for all subgraphs in subgraph units. In order to perform such parallel input / output, if the size of the binary image is M × N, the graph memory unit 102 is configured using five M × N-bit registers. The five registers correspond to the information of the five subgraphs shown in FIG. 2 (c).

Further, the graph-graph conversion unit 103 includes the graph memory unit 1
This is a part that converts the graph stored in 02 into another graph according to a rule according to the processing, and stores it in the graph memory unit 102. It also has processing elements equal to the number of subgraphs,
These processing elements are operated as shown in FIG.
Each processing element has a local memory and can operate independently. That is, as shown in FIG. 3, each processing element inputs a bit sequence representing a state of a corresponding subgraph and a neighboring subgraph, performs a given process, and performs a given process, and a bit sequence representing a state of a graph corresponding to the processing element. Is output. In this case, the bit string of each subgraph can be regarded as a binary number. So, for the processing of each element, input 9 variables,
It can be considered that a given process is performed and one variable is output. Therefore, the graph-graph conversion unit 103 performs pixel-by-pixel perfect parallel processing for a grayscale image as described in, for example, “Journal of the Institute of Electronics and Communication Engineers, vol. 67, No. 1, pp. 90-98”. This processing is realized by diverting the processing element group of the image processing apparatus.

The control unit 104 includes an image memory unit 100, an image-graph conversion unit 101, a graph memory unit 102, and a graph-graph conversion unit.
This is a part that controls 103 as described below, and is configured by a CPU.

First, in accordance with an instruction from the control unit 104, the image-graph conversion unit 1
In step 03, the digital binary image stored in the graph memory unit 102 is read, converted into a connected graph, and stored in the graph memory unit 102.

Next, according to an instruction from the control unit 104, the graph-graph conversion unit 103 reads the graph stored in the graph memory unit 102, converts the graph into another graph according to the conversion rule given by the control unit 104, and It is stored in the memory unit 102.
Further, the graph-graph conversion unit 103 notifies the control unit 104 whether or not there is a difference between the input graph and the output graph.

The operation of the graph-graph conversion unit 103 is repeated according to an instruction from the control unit 104 based on the number of repetitions and the graph change status obtained from the graph-graph conversion unit 103. At this time, the conversion rule can be changed for each iteration according to the processing content.

〔The invention's effect〕

According to the present invention, by providing a circuit that configures a connected graph as a subgraph corresponding to pixels on a one-to-one basis, processing of the connected graph (feature point extraction, vectorization, etc.) can be performed at high speed. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a parallel image processing apparatus according to one embodiment of the present invention, FIG. 2 is an explanatory diagram showing conversion of a digital binary image into a connected graph in one embodiment of the present invention, and FIG. FIG. 4 is an explanatory diagram showing processing of each processing element when converting a connected graph into another connected graph according to an embodiment of the present invention. FIG. 4 is a logic circuit diagram of a processing element constituting an image-graph conversion unit of FIG. It is. 11: processing device, 12: input device, 13: output device, 100: image memory unit, 101: image-graph conversion unit, 102: graph memory unit, 103:
Graph-graph conversion unit 104: control unit.

Claims (1)

(57) [Claims] 1. A parallel image processing apparatus in which one processing element is assigned to one pixel constituting a digital binary image and the same processing is simultaneously performed on a plurality of processing elements.
Means for accumulating a digital binary image in pixel units, and operating the processing elements in parallel, inputting the state of the pixels corresponding to each processing element and the pixels in the vicinity of the pixels, and making a one-to-one correspondence with the pixels Means for converting to a corresponding subgraph to obtain a connected graph, means for accumulating the connected graph in units of subgraphs, operating the processing elements in parallel, subgraphs corresponding to the respective processing elements and the subgraphs Means for inputting a subgraph in the vicinity of the subgraph and converting the subgraph according to a predetermined rule.