JPH06152568A - Data processing method for digital signal of fm multiple broadcasting - Google Patents

Abstract

PURPOSE:To simplify the structure and enable high-speed processing while the successive start timing being independent of the presence or absence of data error by correcting errors a batch in prior to error detection. CONSTITUTION:An error correction section 4 constructed by hardware reads data written in a memory 3a, making an error correction in the horizontal direction to write data in a memory 3b. A CRC circuit 5 reads out the data to detect error. If the data is normal, error corrected data are sent to a memory 7a. If the data is abnormal, uncorrected data are sent to the memory 7a. Then, a CPU 6 reads out data from the memory 7a in the vertical direction, gives them to an error correction section 8 to correct errors. If the number of errors is less than N bit, the corrected data are written in the memory 7b. If it exceeds the N bit, the data before correction are written in the memory 7b. In short, the error correction in the horizontal or vertical direction can be made constant for each unit regardless of the presence or absence of data error, and the start timing of the next stage processing can be stabilized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of processing data of a digital signal of FM multiplex broadcasting, and particularly proposes a synchronizing method useful when applied to a mobile receiver thereof.

[0002]

2. Description of the Related Art In FM multiplex broadcasting, another program is transmitted by mounting a digital signal on a 76 kHz subcarrier.
As shown in FIG. 1, this digital signal comprises one packet consisting of a 16-bit header section and 272-bit data.
A format in which two packets form one frame has been proposed. To explain this in more detail, one packet of 272
The rear 82 bits of the bit data are data for data error correction. The last 14 bits of the 190-bit data are CRC data. The remaining 190 bits of a specific packet are also used for data error correction. This data (parity block data) is used for vertical data error correction, and the rear 82-bit data is used for horizontal data error correction.

The header portion has a 16-bit structure, and 13 packets (hereinafter referred to as group 1) from the head of the frame provided for synchronization are BIC1. Next 123 packets
The parity block (hereinafter referred to as group 2) is BIC4, and the others are BIC3. A parity block is provided at the end of each group of 3 packets, one for every 3 packets. Continue
The header part of 13 packets (hereinafter referred to as group 3) is BIC2
Is. Last 123 packets (hereinafter referred to as group 4)
The header part of BIC3 and BIC4 is the same as that of group 2. In addition, the above-mentioned place is a conceptual one,
A packet whose header part is BIC3 is interleaved with a packet whose header part is BIC4 (parity block).

[0004]

When a mobile unit receives such digital data, some bits are often lost, and a countermeasure against this is essential. Therefore CR
C. Although error correction is performed, it is required that the correction data have high reliability and that the processing be performed at high speed. The present invention has been made to meet such a demand, and can increase the dependency of hardware,
It is an object of the present invention to provide a method capable of high speed and highly reliable data processing.

[0005]

A data processing method for a digital signal of an FM multiplex broadcast according to the present invention is a method for processing data having horizontal and vertical error correction codes. Step to be performed Step for performing horizontal error detection on the data after error correction, adopt the data after error correction when the result of horizontal error detection is normal, and if there is an error, the data before error correction If the number of bits of error correction in the vertical direction is less than a predetermined value, the data after error correction is adopted and the predetermined value is set. If it exceeds, it is characterized by including the step of adopting the data before error correction and determining the data.

[0006]

[Function] The error is uniformly corrected prior to the error detection. Therefore, for horizontal data processing as well, the processing time for one unit is constant regardless of the presence or absence of data errors, and the start timing of subsequent processing does not depend on the presence or absence of data errors. The configuration can be simplified, which results in high-speed processing and leads to highly reliable data. In addition, since error correction is performed uniformly, the peripheral circuit is simplified, and it is advantageous to implement this part in hardware. Moreover, error correction can generally be faster in hardware than in software. Be advantageous

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments. FIG. 2 is a block diagram of a main part of an FM multiplex broadcast receiver using the method of the present invention, and FIG. 3 is a flowchart showing a processing procedure of the method of the present invention. The received data is input to the synchronization unit 1, the head of the frame is detected based on the content of the header, and the synchronization is established accordingly. The received data is taken into the data taking-in section 2 by the synchronizing pulse which the synchronizing section 1 outputs after the synchronization is established, and the taken-in data is sequentially stored in the memory.
It is written in 3a (or 3b).

The memories 3a and 3b each have a capacity of one frame and are used alternately for each frame. The error correction unit 4 composed of hardware stores one packet of data in the memory.
When it is written in 3a (or 3b) (S1), it is sequentially read out to perform horizontal error correction (S2), and the corrected data is written in the memory 3b (3a). The CRC circuit 5 reads this data
Error detection by CRC is performed (S3). If the error is normal (no error), the data after error correction is transferred from the memory 3b (or 3a) to the memory 7a having a capacity of one frame (S4). CRC is abnormal
In the case of (with error), the data before correction is transferred from the memory 3a (or 3b) to the memory 7a via the CPU 6 (S5). This is repeated until the end of all packets (S6).

Next, the CPU 6 moves 272 vertically from the memory 7a.
The bit data is read and given to the hardware error correction unit 8 to perform vertical error correction (S7). In this error correction, it is checked whether the number of errors is N bits or less (S7). If it is N bits or less, the corrected data is written in the memory 7b having a capacity of 1 frame (S9).
If the error exceeds N, the data before correction is stored in the memory 7b.
Write to (S10). The processing of steps S7 to S10 is performed for 272 bits in the horizontal direction.

As described above, although some error corrections have been performed in both horizontal and vertical directions, error detection is performed again in the horizontal direction. CRC in step S2 to simplify processing
Only those that have errors are selected (S11), and the CRC is calculated only for those packets (S12). And CRC
If there is an error in the recalculation result (S13), the content of the memory 7a is written to the memory 7b for that packet (S14).
This is based on the idea that it is better to leave the data as it may be because the error correction may make the data worse. If there is no error, exit as is. The contents of the memory 7b thus obtained are sent to the processing circuit of the next stage.

[0011]

According to the present invention as described above, horizontal and vertical error correction is performed for each unit regardless of the presence or absence of data error.
It can be made constant for every packet or every 272 bits in the embodiment, and the start timing of the processing of the next stage is stabilized. Although there is some variation in the above-described embodiment due to the existence of steps S11 to S14, if this step is omitted or step S11 is omitted, CRC is applied to all packets.
When recalculating, the processing time is stabilized. In this way, by stabilizing the processing start timing of the next stage, the software and hardware for the next stage processing are simplified, and as a result, high-speed and highly reliable data processing is possible. .

Further, since the error correction is uniformly performed, the peripheral circuits can be simplified, and it is advantageous to implement the error correction portion by hardware, and further, it is possible to enjoy the advantage of speeding up by hardware implementation.

[Brief description of drawings]

FIG. 1 is a format diagram of data to be processed.

FIG. 2 is a block diagram of an apparatus used to carry out the method of the present invention.

FIG. 3 is a flow chart of the method of the present invention.

[Explanation of symbols]

 3a, 3b, 7a, 7b Memory 4, 8 Error correction unit 5 CRC circuit 6 CPU

Claims (1)

[Claims] 1. A method of processing data having horizontal and vertical error correction codes, wherein horizontal error correction is performed, horizontal error detection is performed on the data after error correction, and horizontal error detection is performed. The step of tentatively determining the data by adopting the data after the error correction when the error detection result is normal, and the data before the error correction when the error is detected, the step of performing the error correction in the vertical direction , And, if the number of bits of error correction in the vertical direction is less than a predetermined value, adopt the data after error correction, and if it exceeds the predetermined value, adopt the data before error correction to determine the data. Data processing method of digital signal of FM multiplex broadcasting characterized by.