JPS60208170A - White level detecting circuit of picture signal - Google Patents

Abstract

PURPOSE:To detect a correct white level without being affected by noise by providing a white level data storage means, comparing it with a white level data having an input picture signal data so as to allow the output to decrease or increase the white level. CONSTITUTION:A white level data of a picture signal is stored in an up-down counter 21. An input picture signal is given to a comparator 32 via a line 24 and compares with the white level data from the counter 21. When the level of the input picture signal is large, the white level of the counter 21 is increased. When the white level data from the counter 21 is larger, the white level data of the counter 21 is decreased. Thus, even when the white level is detected in error due to effect of noise or the like, the correct white level is detected.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an improvement in a circuit for detecting the white level of an image signal obtained in a device having a photoelectric conversion section such as a facsimile device Pt. be.

[Technical background of the invention]

The conventional nuclide circuit was constructed as shown in Figure 1.

For example, the image signal is transferred to memory 2 using 4-bit image signal line 1.
The white level data and [7] are stored. The output of this memory 2 is led to a comparator 4 through a 4-bit data line 3, and the image signal is led to the comparator 4 through the image signal line 1. The comparator 4 compares the image signal with the white/pel data output from the memory 2, and when the level of the image signal is high, the output is set to a high level and is sent to the memory 2 via the signal line 5. Enable memory 2. As a result, the new image signal is written into the memory 2 as white level data. Therefore, it is assumed that the maximum white level data up to the present stage is stored in the memory 2, and from now on, rewriting will be performed every time an image signal with a higher white level arrives.

[Problems with background technology]

However, according to the above circuit, when an image signal having a white level higher than the original background color of the original due to the influence of noise or both signals having a higher white level due to wrinkles or distortion of the original arrive, These image signals are stored in the memory 2 as white level data and are never restored. For this reason, there was a drawback that the correct white level could not be detected.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a white level detection circuit for an image signal that can detect a correct white level without being affected by noise or the like.

[Summary of the invention]

Therefore, in the present invention, a holding means for holding white level data of an image signal is provided, and the output of this holding means is compared with input image signal data, and the white level data held by the holding means is determined based on the output. A comparison means for raising the white level data by a predetermined number of steps in synchronization with the image signal clock, and a control means for lowering the white level data held by the holding means by a predetermined number of steps in synchronization with the image signal clock. A signal white level detection circuit was constructed.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a schematic diagram of one embodiment of the present invention. In the figure, 21 indicates an up/down counter. The up/down counter 21 is a holding means for holding the white level data of the image signal, and outputs the 4-bit,
output white level data.

This output is applied to a comparator 23 which is a comparison means, and a 4-bit image signal is applied to the comparator 23 via an image signal line 24. When the image signal is larger than the output of the up/down counter 21, the comparator 23 sets its output to a no-y level, and otherwise sets its output to a low level. The output of the comparator 23 is sent from the output line 25 to the enable terminal ( ) of the up/down counter 21 via the OR gate 26 .

Further, it is a 27-digit n (n is a predetermined positive number) counter. The counter 27 is the image signal black.

When the signal is input from the clock line 28 to the clock terminal, and n pulses are inputted, the output of the carry terminal is changed from low level to no level.

The output of the counter 27 is given to the up/down defining terminal U/D of the up/down counter 21. The up/down counter 21 has an up/down specification terminal, U/
When the signal applied to D is at a low level, a rising operation is performed, and when it is at a high level, a falling operation is performed. Further, the output of the counter 27 is applied to the enable terminal of the up/down counter 21 via the OR gate 26.

Such a counter 27 is a control means for decreasing the white level data of the up/down counter 21 by one step. Furthermore, the up/down counter 21 is supplied with both signal clocks from the black and red terminals, and operates at the rising edge of the pulse of both signal clocks.

In the circuit configured as described above, assume that the image signal applied to the comparator 523 is now larger than the white level data output from the up/down counter 21. Then, the output of the H' comparator 23 becomes a high level, and the up/down counter 21 receives an output signal via an OR gate 26.
level signal is given. On the other hand, since a low level signal is generally given to the up/down specification terminal U/D, the up/down counter 21 is counted up by one step at the rising edge 9 of the image signal clock pulse. As a result, the counted up white level data is output from the output line 22.

Further, when n pulses of the image signal clock arrive, the counter 27 makes its output high level.

Therefore, a high level signal is given to the up/down specification terminal U/D and the enable terminal of the up/down counter 210, and the up/down counter 21 counts down by one step at the rising edge of the image signal black and red pulses. . As a result, the counted down white level data is output via the output line 22.

Therefore, even if the up/down counter 21 counts up by one step due to the influence of noise or the like, the counter 27
This will count down one step and return to the original state. Also,
If the count up is correct, it is counted down once every n@ of the image signal clock pulse and then counted up immediately, so that correct white level data can be held.

In the embodiment, the white level data changes one step at a time, but in cases where the color of the document conveyance path changes to the color of the background of the document, or when the color of the background of the document changes. In this case, it may be changed in multiple stages. On the other hand, when using a manuscript paper with a lot of noise, it is desirable to make the change more gradual than in the embodiment.

In such a case, when changing in multiple stages, the lower bits may be used as the output bits of the up/down counter 21. For example, if the upper 4 bits of the 5 bits output are used, the lower 4 bits may be used.

In addition, in order to make the change gradual, the image signal clock is guided to the counter 27 via a multiplier circuit, and the output of the comparator 23 is guided to the OR gate 26 via a counter with a predetermined advance. good.

〔Effect of the invention〕

As explained above, according to the present invention, even if the white level is erroneously detected due to the influence of noise, the white level data of the holding means is corrected by the function of the control means until the correct white level is obtained. , the correct white level can be detected. Depending on the application, the white level data may be increased or
Alternatively, it is possible and convenient to make small changes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional image signal white level detection circuit, and FIG. 2 is a block diagram of an embodiment of the present invention. 21...-- Up/down counter 23-
−−−・Comparator 26・・・・・・・−・ Or gate 27・・・・・・ Counter agent Patent attorney Noriyuki Chika (and 1 other person) Figure 1

Claims (2)

[Claims] (1) A holding means for holding white level data in the image signal data, and comparing the output of the holding means with both input signal data, and the white level data held by the holding means based on the comparison output. a comparison means for increasing the white level data by a predetermined number of steps in synchronization 17 with the image signal clock; and a control means for lowering the white level data held by the former holding means by a predetermined number of steps in synchronization with the image signal clock. White level detection circuit. (2) The holding means is an up-down counter that operates in synchronization with the image signal clock, and the comparing means is an up-down counter that operates when the white level data in the input image signal data is greater than the output of the up-down counter. A comparator that outputs an active signal from the enable terminal.
The control means is a counter that outputs an active signal to the enable terminal of the up-down counter every time a predetermined number of pulses of the image signal clock are input, and that output specifies the upward and downward operations of the up-down counter. Claim No. 1 characterized in that (
The image signal white level detection circuit described in item 1).