KR920008896B1 - Page edge detecting circuit of image data for fax - Google Patents

Abstract

The circuit is for detecting end of page signal to decrease load on CPU of facsimile system. The circuit includes an end of line detector (eol) for detecting EOL signal, an EOL signal generator triggered by EOL signal to generate count clock and trigger signal and sending the signals through a first and a second terminal respectively, a pulse generator enabled by trigger signal of the EOL signal generator for generating a first logic pulse with a certain period and for generating a second logic pulse when the next trigger signal is not received within the period of the first logic signal, and an page end signal generator for generating page end signal when the number of count clock reaches a value and for resetting the counter by the second logic signal.

Description

Page end detection circuit of facsimile image data

1 is a conventional end of page detection method.

2 is a block diagram of a system for detecting end-of-page of data transmitted by a plurality of facsimile using the present invention.

3 is a page end detection circuit according to the present invention.

4 is an operating waveform diagram of each part of FIG.

* Explanation of symbols for the main parts of the drawings

FAX: Facsimile EX: Exchange

MD: Modem ECC: Page end detection circuit

INTC: Interrupt control unit CPU: Control unit

CNT1, CNT2: Counter IG1, IG3: Inverter

AG1, AG2: Endgate FF1, FF2: Flip-flop

MM1-MM2: Multivibrator

The present invention relates to circuitry for detecting the end of page of data transmitted in a facsimile.

In general, in a facsimile system, when transmitting image data for an arbitrary document, an end-of-line signal indicating that image data of a corresponding line is terminated in units of one line, as shown in FIG. 1c, is referred to as an End Of Line Signal. At the end of one page, six EOL signals are transmitted to indicate that image data of the corresponding page is finished. In the conventional method for detecting the EOL signal as described above, as shown in FIG. 1A, the controller CPU first stores data input into the modem MD in the memory MEM, and then stores the data in the memory MEM. After analyzing the stored data to find the EOL signal, there is a method of classifying and processing the line EOL signal and the page EOL signal. As another method, as illustrated in FIG. 1B, the presence or absence of an EOL signal is detected through the EOL detection unit, and an interrupt signal is output to the control unit (CPU) whenever the EOL signal is generated. There was a method of analyzing whether the EOL signal is a line EOL signal or a page EOL signal.

However, in the case of using the two methods as described above, when one facsimile machine is used, one controller must process a plurality of modems at the same time.

Accordingly, an object of the present invention is to provide a circuit that can easily detect the end of the page of the image data transmitted in the facsimile system.

Another object of the present invention is to provide a circuit that can reduce the system load by generating a page end detection signal of each facsimile and applying it to the control unit even when using a plurality of facsimile.

Hereinafter, the present invention will be described in detail with reference to the drawings.

2 is a circuit for detecting and applying each page end of n faxes to the control unit using the present invention, wherein the N faxes FAX1 to FAXn, the exchanger EX, and the exchanger EX are connected to each other. End of page signal by analyzing EOL signal generated by the modem (MD1-MDn) and the modem (MD1-MDn) that generate data clock at the same time converting image signal to digital data A page end detection circuit (ECC1-ECCn) for generating a signal and an interrupt control unit (INTC) for transmitting each signal of the page end detection circuit (ECC1-ECCn) as an interrupt signal to the control unit (CPU).

FIG. 3 is a detailed circuit diagram of the page end detection circuit of FIG. 2 and includes an inverter IG1, IG2, a counter CNT1, and an AND gate AG1-AG2, and receives data RxD and clock RxC that are transmitted. A line end detector for detecting a line end signal EOL having a specific bit strip from the received data, and a flip-flop (FF1-FF2), receiving an output of the line end detector, and triggering when the line end signal EOL is received. A line end signal generator for generating a count clock having a first logic to a first output terminal and a trigger signal having a second logic to a second output terminal, and a second end of the line end signal generator as a multivibrator MM1. Is connected to an output terminal and is enabled when the trigger signal of the second logic is received to generate a pulse of the first logic having a predetermined period and has a second logic when the trigger signal of the first logic is not received within the period. It is composed of a pulse generator for generating a load signal, a counter (CNT2), an inverter (IG3) and a noah gate (NG1), the first output terminal and the clock terminal of the line end signal generator is connected, the output terminal and the load of the pulse generator A stage is connected, and when the load signal is not received, the count clock is counted, and when the line end signal EOL is received a predetermined number or more, a page end signal EOP is generated. It consists of a page end signal generator for initializing.

In the above description, the first logic indicates a 'high' logic state and the second logic indicates a 'low' logic state.

4 and 5 are waveform diagrams showing the operation of each part of FIG. 3, and the waveform diagram of FIG. 4 receives the EOL signal (000000000101) having a specific bis stream by analyzing the received data RxD. After detecting in synchronization with the waveform, the waveform of the process generated by the count clock is shown. The waveform diagram of FIG. 5 continuously counts the number of occurrences of the count clock generated at a predetermined period by the count clock and the trigger signal. When four or more EOL signals are generated, this signal is generated as a page ending signal.

Based on the above-described configuration, the present invention will be described in detail with reference to the second, third, fourth and fifth degrees.

2 is a configuration diagram of a facsimile interface unit (FIU), wherein the facsimile (FAX1-FAXn) can transmit image data to a control unit (CPU) axis through a private exchange (EX). Image data stored in the FIU can be received. Accordingly, the control unit CPU receives image data transmitted from each of the facsimiles FAX1-FAXn through the modem MD1-MDn and records the data in the memory unit of the FIU. Therefore, the page end detection circuits ECC1-ECCn are connected 1: 1 to the modems MD1-MDn, respectively, and receive an EOL signal having a bit stream of a specific type from the image data received from the modem MD1-MDn. When a predetermined number or more of the EOL signals are detected, the interrupt request signals IRQ1 to IRQn are generated to the interrupt control unit INTC using the page end signal.

Here, a process in which an arbitrary page end detection circuit ECC receives the data RxD and the clock RXC from the modem MD and generates the page end signal as described above will be described. When transmitting the image data, the modem MD transmits one EOL signal at the end of the image data of each line as shown in FIG. 1C, and transmits six EOL signals at the end of the image data of one page. Therefore, when six EOL signals are received in succession, it means that all the image data of the corresponding page have been received. The EOL signal is recommended to be configured as "000000000001" in the CCITT regulations. At this time, the data RXD transmitted from the modem MD has a bit stream form of serial data which is output by converting analog data transmitted from the facsimile FAX into digital data, and is shown in FIG. As shown in (4b), it becomes a bit stream form. In addition, the clock RXC is a clock used when the modem MD outputs the data RXD. The clock RXC has a shape as shown in FIG. 4A.

At this time, the counter CNT1 receives the data RXD output from the modem MD through the inverter IG1 through the load terminal / LD, and the clock output from the modem MD through the clock terminal CLK. Receive (RXC). Therefore, when the data RXD is in the "high logic" state, the counter CNT1 loads "0000" into the input terminals D3-D0, and when the data RXD is in the logic low state. Up counting the same clock RXC as the received 4a. At this time, the AND gate AG1 outputs a 'high' signal when the output of the counter CNT1 is '1011'. Therefore, when the modem MD outputs an EOL signal as shown in (4b) of FIG. 4, the counter CNT1 is initialized when the received data RXD is in the “high” state. RXC) counts the number of 0 'of the EOL signal as shown in (4b). At this time, if the low signal is not received by the load terminal / LD while the number of # 0 is counted to 11, the counter CNT1 outputs # 1011 \ through the output terminals Q3-Q0. The AND gate AG1 outputs a “high” signal as shown in (4c). At this time, if the output of the AND gate AG1 such as (4c) is applied to the AND gate AG2 and the data RXD is an EOL signal such as (4b), the AND gate AG2 has both input signals high. In this state, as shown in (4d) of FIG. 4, the EOL signal having the high logic having the first logic is output.

Therefore, the line end detection unit analyzes the received image data and detects and outputs a line end signal indicating a line end.

Then, the flip-flop FF1 receives the EOL signal output from the AND gate AG2 as a clock, and is triggered when the EOL signal is received as shown in (4d) of FIG. 4 to transfer the first logic to the first output terminal Q. The high signal is applied to the count clock of the counter CNT2, and the count clock is again applied to the data of the flip-flop FF2. Then, the flip-flop FF2 synchronizes the count clock outputting the flip-flop FF1 to the clock RXC to output a low signal to the inverted output terminal / Q, and outputs the inverted output of the flip-flop FF2. Since the signal is applied to the clear terminal of the flip-flop FF1, the flip-flop FF1 is cleared. Therefore, when the flip-flop FF1 receives the EOL signal, the first output stage Q generates a high-clock count clock such as (4e), and the second output terminal (/ Q) generates a low clock clock such as (4f). Generates a trigger signal for the state.

At this time, since six EOL signals such as (4b) are continuously generated at the end of the page, the count clock for outputting the first output Q of the flip-flop FF1 is the same as the shape (5a) of FIG. The trigger signal for outputting the two output terminals / Q has the same form as (5b). The counter CNT2 counts the count clocks as described above and generates an interrupt signal when a predetermined number or more are detected. During the predetermined period of counting the count clocks, the counter CNT2 should not be initialized. The above function is performed by the multivibrator MM1. When the EOL signal is continuously input at the end of the page, the interval becomes 1.1 msec. Therefore, the time constants of the resistor R1 and the capacitor C1 of the multivibrator MM1 are set to exceed 1.1 msec. Then, the multivibrator MM1 is continuously triggered when the trigger signal for outputting the second output terminal / Q of the flip-flop FF1 is input with a pulse string such as (5b) generated at a 1.1 msec period ( Maintain a high state, which is the first logic as in 5c). Accordingly, the multivibrator MM1 prevents the counter CTN2 from being initialized while the EOL signal is continuously generated.

While maintaining the first logic high state signal in the multivibrator MM1 as shown in (5C), the counter CNT2 receives a count clock such as (5a) at the clock end to count the number of occurrences of the EOL signal. In consideration of an error on the transmission line, if a predetermined number of EOL signals are detected, the end of page is determined. Therefore, when the counter CNT2 counts four EOL signals and outputs # 0100 to the output terminals Q3-Q0, the NOA gate NG1 outputs the counter CNT2 to the end of the page as shown by (5d). An interrupt request signal (IRQ) signal is generated indicating that the signal has been detected.

When the generation of the EOL signal is terminated, the AND gate AG2 is kept in a low state because the EOL signal is not detected by the counter CNT1. Thus, the flip-flop FF1 also has the mount clock and the trigger signal. Does not occur, and thus the multivibration MM1 remains low in the second logic. At this time, since the output of the multivibrator MM1 is applied as a load signal of the counter CNT2, when the multivibrator MM1 outputs a load signal having a second logic in a low state, the counter CNT2 is initialized. Enters the ready state to detect the end of the next page.

As shown in FIG. 2, the page-end detection circuit ECC of FIG. 3 performing the above operation is connected to the modem MD1-MDn in a one-to-one manner, and thus occurs in the facsimile FAX1-FAXn. The end-of-page signal can be detected independently, and an interrupt request signal is generated to the interrupt controller INTC when detecting the end-of-page. At this time, the interrupt control unit INTC outputs the interrupt request signal that occurs first to the control unit CPC, and the interrupt request signal that occurs at the same time gives priority to each interrupt request signal due to rotation in a round robin manner. To be processed. When the interrupt signal is received from the interrupt control unit INTC, the control unit CPU receives image data transmitted from the facsimile, stores the image data in the memory, and terminates the operation.

As described above, the image data of the facsimile can be processed in units of pages, and there is an advantage of reducing the system load when operating a system using a plurality of facsimile.

Claims (1)

A plurality of modems connected to a plurality of faxes and outputting a line end signal having a specific bit stream form at a line end of the received image data and continuously outputting a predetermined number of the line end signals at the end of a page; And a page end detection circuit for detecting a page end of imposition data transmitted and connected respectively, and a control unit for storing image data received from a corresponding modem in units of pages when a page end signal is received from the page end detection circuit. The page end detection circuit of claim 12, wherein the line for receiving data and a clock transmitted from the modem, synchronizing the received data to the clock, and checking the received data to detect a line end signal EOL having a specific bit stream. An end detector and an output of the line end detector. And a line end signal generator for generating a count clock having a first logic to a first output terminal and a trigger signal having a second logic to a second output terminal when the line end signal EOL is received. A second logic connected to the second output terminal of the generator and enabled when the trigger signal of the second logic is received to generate a first logic pulse having a predetermined period and the trigger signal of the first logic is not received within the period; A pulse generator for generating a pulse and outputting it as a load signal, a clock terminal is connected to a first output terminal of the line end generation generator, and a load terminal is connected to an output terminal of the pulse generator, and a first logical pulse is received from the pulse generator And counting the received count column as a signal for detecting the end of the page when the line end signal is received a predetermined number or more, and outputting the signal from the pulse generator. And a page end signal generator for initializing the data being counted when a load signal of the second logical pulse is received.

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