JPH08123703A - Failure detecting system for parity check circuit - Google Patents

Abstract

PURPOSE: To provide a failure detecting system capable of detecting a failure in a parity check circuit at a shorter period during the operation of the system. CONSTITUTION: An operation monitoring signal sending means 105 sends an operation monitoring signal to be periodically inverted based upon an instruction sent from a switching instruction sending means 106. A parity checking means 103 receives transfer data obtained by adding a parity bit to data transmitted from a data register 101 as an input signal together with the operation monitoring signal, outputs a parity check result for the transfer data as a parity error signal independently of the value of the operation monitoring signal at the time of normal operation, and at the occurrence of a failure, a parity check result changed in accordance with a change in the value of the operation monitoring signal as a parity error signal. A failure detecting means 104 detects the existence of failure occurrence in accordance with a change in the value of the parity error signal generated before and after a change in the value of the operation monitoring signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure detection method for a parity check circuit, and more particularly to a failure detection method for detecting a failure of a parity check circuit for detecting a data bit error.

[0002]

2. Description of the Related Art Conventionally, when data is transmitted inside a computer or a communication path, a bit value is different from an original value due to noise or other causes (that is, 1 when 0, 0 when 1). Therefore, a parity check circuit for adding a parity bit to data and performing a parity check is provided.

FIG. 4 is a block diagram showing an example of a conventional fault detection method for a parity check circuit. In the figure, the data once held in the data register 401 is added with a parity bit P, and the data
And is output to the subsequent stage as a parity check circuit 4
02.

The parity check circuit 402 checks whether the number of 1's in the input transfer data signal 403 is an odd number (even number in the case of even parity) when odd parity, and an odd number (in the case of even parity). If there is no even number), a parity error signal is output.

Here, the parity check circuit 402 may also fail, and it is impossible to detect a data error at the time of failure. Therefore, conventionally, failure detection is performed by periodically executing the diagnostic program of the parity check circuit 402. Is going. That is, the above diagnostic program is
Stop the operation of the system and all data registers 401
In response to this, a parity error is generated by giving pseudo-failure occurrence data such that a pseudo-failure occurs sequentially, and a parity error signal is output when the parity check circuit 402 is normal. Checking that it is working.

[0006]

However, in the above-described conventional failure detection method, in order to confirm whether or not all the parity check circuits in the device have a failure, the operation of the system is stopped and a dedicated diagnostic program is executed. It must be executed, and the execution time is relatively long, so that it cannot be executed frequently.

For this reason, even if the parity check circuit has failed, no failure of the parity check circuit can be found until the next execution of the diagnostic program. As a result, even if data corruption occurs, the parity check circuit continues to operate. There is a problem that the influence is very large.

Further, since the above diagnostic program needs to be created in accordance with the hardware, if the hardware is modified or changed, the diagnostic program must be modified each time. There is a problem that man-hours are required.

[0009] The present invention has been made in view of the above points,
It is an object of the present invention to provide a parity check circuit failure detection method capable of detecting a failure of a parity check circuit in a shorter cycle during system operation.

It is another object of the present invention to provide a parity check circuit failure detection system capable of detecting a failure of a parity check circuit regardless of hardware modification / change.

[0011]

In order to achieve the above object, the present invention has an operation monitor signal generating means for generating an operation monitor signal which is periodically inverted, and a transfer in which a parity bit is added to transmitted data. Receives data as an input signal together with the operation monitoring signal, outputs the parity check result of the transfer data as a parity error signal regardless of the value of the operation monitoring signal during normal operation, and changes according to the change in the value of the operation monitoring signal when a failure occurs. Parity check means for outputting the parity check result as a parity error signal, and whether the value of the parity error signal before and after the value of the operation monitoring signal has changed by receiving the parity error signal and the operation monitoring signal as input signals It is configured to include a failure detection unit that detects whether or not a failure has occurred.

The parity check means of the present invention receives the transfer data and the operation monitoring signal and performs a parity check on the transfer data, and performs an exclusive OR operation on the result of the parity check and the operation monitoring signal. A first arithmetic circuit for outputting a signal obtained by performing the operation, and a second operation circuit for outputting, as a parity error signal, a signal obtained by performing an exclusive OR operation of an output signal of the first arithmetic circuit and the operation monitoring signal. When the parity check is performed normally, the result of the parity check does not change regardless of the value of the operation monitoring signal. On the other hand, when the parity check is not performed normally, the operation is performed. It is desirable to easily obtain a signal whose parity check result changes according to the value of the monitoring signal.

[0013]

According to the present invention, the parity check means performs a parity check on input transfer data, and performs a logical operation based on the parity check result and an operation monitoring signal whose value is periodically inverted. The parity check result is output as a parity error signal irrespective of the value of the operation monitoring signal, and when a failure occurs, the parity check result that changes according to the change in the value of the operation monitoring signal is output as a parity error signal. When the detecting means detects that the value of the parity error signal has not changed immediately before and immediately after the change of the value of the operation monitoring signal, no failure of the parity error circuit occurs, and the value of the parity error signal changes. The parity error circuit can detect that a failure has occurred. That.

[0014]

Next, an embodiment of the present invention will be described. FIG. 1 shows a block diagram of an embodiment of the present invention. As shown in the figure, this embodiment comprises a data register 101, an error detection means 102, an operation monitoring signal transmission means 105 and a switching instruction transmission means 106. The operation monitoring signal transmitting means 105 and the switching instruction transmitting means 106 constitute the operation monitoring signal generating means. Data register 1
01 holds, for example, 8-bit data and 1-bit parity bit (even parity).

The error detecting means 102 performs a parity check and outputs a parity error signal 109 having a predetermined value when an error is detected. The fault detecting means 1 outputs a fault detection signal 110 when a fault is detected.
04 and 04. Operation monitoring signal sending means 10
5 transmits an operation monitoring signal 108 indicating whether the parity check means 103 is operating normally. The switching instruction sending means 106 is a means for sending an instruction for switching the value of the operation monitoring signal 108 at a constant cycle.

As shown in FIG. 2, for example, a transfer data signal 107 from the data register 101 and an operation monitoring signal 108 from the operation monitoring signal transmitting means 105 are input to the parity check means 103, and exclusive use of all these bits is performed. Exclusive OR (EXOR) circuit 20 for performing a logical OR operation
1 and an exclusive OR (E) for performing an exclusive OR operation of the output signal of the EXOR circuit 201 and the operation monitoring signal 108
XOR) circuit 202.

The failure detecting means 104 is, for example, as shown in FIG.
The operation according to the flowchart shown in FIG. That is,
A parity error signal 109 sent from the parity check unit 103 and an operation monitoring signal 108 from the operation monitoring signal sending unit 105 are received as input signals, and the value of the operation monitoring signal 108 falls from “1” to “0”. That is, it is detected that the signal has risen from "0" to "1" (step 301). At that time, a check signal is output, and the parity error signal 109 changes from "0" to "1" before and after the output point. It is detected whether "or" has changed from "1" to "0" (step 302).

Next, the operation of this embodiment will be described with reference to FIGS.
Will be explained together. Normally, the switching instruction sending means 106
When the operation of the apparatus is started, the value of the operation monitoring signal 108 to the operation monitoring signal transmitting means 105 is set to "1" if the value is "0" at that time every time a predetermined fixed time comes.
Then, if it is "1", an instruction to invert to "0" is sent.

Therefore, the operation monitoring signal transmitting means 105 receiving the switching instruction uses the above-mentioned signal inverted at regular intervals as the operation monitoring signal 108 as the parity checking means 103 and the failure detecting means 104 in the error detecting means 102. Output to each of.

The error detecting means 102 constantly carries out a parity check, and when it is operating normally, the result of the parity check is sent normally. That is, when the parity check means 103 is normal and there is no parity error in the input transfer data signal 107, the output of the EXOR circuit 201 shown in FIG.
Is “0”, and the operation monitoring signal 108 is “1”.
In this case, the signal becomes "1", but a signal indicating that there is no parity error of "0" is taken out from the EXOR circuit 202 at the next stage regardless of whether the operation monitoring signal 108 is "0" or "1". . Similarly, when there is a parity error, the operation monitoring signal 108 is output from the EXOR circuit 202 to “
Whether "0" or "1", a "1" signal indicating a parity error is output.

That is, the parity check means 103
Indicates that the EXOR circuit 2 having the same operation monitoring signal 108 has two
01 and 202, the input transfer data signal 107 is checked by the parity check means 103 when the operation monitoring signal 108 is "1" or "0". The result obtained as a result is normally output as the parity error signal 109 (that is, the result of the parity check does not change depending on the value of the operation monitoring signal 108).

Therefore, when the operation monitoring signal 108 changes from "0" to "1" or from "1" to "0", a check signal is generated in the failure detecting means 104 and the parity is detected in step 302 of FIG. The value does not change even when it is detected whether or not the value of the error signal 109 has changed before and after that, so the failure detection signal 110 remains "0", that is, normal operation is indicated (step 30).
3).

However, when the parity check means 103 fails, the failure detection signal 110 becomes "1". That is, the first-stage EXOR circuit 201 which performs the parity check in the parity check means 103 is “0”.
When a stack failure occurs, when the operation monitoring signal 108 is "0", the two input signals of the EXOR circuit 202 in the second stage are both "0", so that the parity error signal 109 becomes "0".
When the operation monitoring signal 108 is “1”, the two input signals of the second-stage EXOR circuit 202 are “0”.
And "1", the parity error signal 109 becomes "1".
Becomes

Further, the EXOR circuit 20 of the first stage which is performing the validity check in the parity check means 103.
When the “1” stack failure occurs, the operation monitoring signal 108
Is "0", the two input signals of the EXOR circuit 202 in the second stage are "0" and "1", so the parity error signal 1
09 becomes “1”, while the operation monitoring signal 108 becomes “1”.
When the value is “1”, the two input signals of the second-stage EXOR circuit 202 are both “1”, so that the parity error signal 109
Becomes “0”.

As shown in FIG. 3, the failure detecting means 104 changes the operation monitoring signal 108 from "0" to "1" or "1".
When the change from 1 "to" 0 "is detected (step 301), it is detected whether or not the parity error signal has changed before and after the detection (step 302). In this case, since the value of the parity error signal changes as described above, it is known that the parity check circuit has failed, and the failure detection signal 110 is set to "1" (step 304).

When the failure detection signal 110 becomes "1", it can be determined whether the data register 101 has generated a parity error or the parity check circuit has failed.

The present invention is not limited to the above-described embodiment, and for example, the operation monitoring signal 108 may be inverted at a predetermined cycle (in short, periodically) even if it is not a constant cycle. Also, the parity check means 103
It is needless to say that the EXOR circuit 201 can have a circuit configuration that performs a parity check using an odd parity and performs an exclusive OR operation with an operation monitoring signal.

[0028]

As described above, according to the present invention,
When it is detected that the value of the parity error signal has not changed immediately before and immediately after the change of the value of the operation monitoring signal, no failure of the parity error circuit occurs, and when the value of the parity error signal changes, the parity is not changed. Because the error circuit detects that a failure has occurred,
The parity check circuit failure can be detected even during the operation of the system, and therefore the parity check circuit failure can be detected in a much shorter cycle than in the past, and the occurrence of a problem that the system continues to operate with a data bit error almost eliminated. Can be.

Further, according to the present invention, the failure is detected using the operation monitoring signal, and it is not necessary to execute the conventional diagnostic program for detecting the failure. Also, no modification of the diagnostic program is required, and the man-hour can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of a parity check unit of FIG. 1;

FIG. 3 is a flowchart for explaining the operation of the failure detection means in FIG. 1;

FIG. 4 is a block diagram of an example of a conventional method.

[Explanation of symbols]

 101 data register 102 error detection means 103 parity check means 104 failure detection means 105 operation monitoring signal transmission means 106 switching instruction transmission means 201, 202 exclusive OR (EXOR) circuit

Claims (2)

[Claims] 1. An operation monitor signal generating means for generating an operation monitor signal which is periodically inverted, and transfer data in which a parity bit is added to transmitted data is received as an input signal together with the operation monitor signal, and at the time of normal operation. The parity check result of the transfer data is output as a parity error signal regardless of the value of the operation monitoring signal, and the parity check result that changes according to the change of the value of the operation monitoring signal is output as a parity error signal when a failure occurs. Depending on whether the parity check means receives the output parity error signal of the parity check means and the operation monitoring signal as an input signal, and the value of the parity error signal before and after the value of the operation monitoring signal changes. A parity check characterized by having a failure detection means for detecting the occurrence of a failure. Failure detection method of circuit. 2. The parity check means receives the transfer data and the operation monitor signal to perform a parity check on the transfer data, and an exclusive OR of the result of the parity check and the operation monitor signal. A first arithmetic circuit that outputs a signal obtained by performing an arithmetic operation, and a signal obtained by performing an exclusive OR operation of the output signal of the first arithmetic circuit and the operation monitoring signal as the parity error signal. The fault detection system for a parity check circuit according to claim 1, further comprising a second arithmetic circuit for outputting.