JPH05235907A - Error counter circuit monitor - Google Patents

Error counter circuit monitor

Info

Publication number
JPH05235907A
JPH05235907A JP3739692A JP3739692A JPH05235907A JP H05235907 A JPH05235907 A JP H05235907A JP 3739692 A JP3739692 A JP 3739692A JP 3739692 A JP3739692 A JP 3739692A JP H05235907 A JPH05235907 A JP H05235907A
Authority
JP
Japan
Prior art keywords
error
counting circuit
circuit
error counting
transmission line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3739692A
Other languages
Japanese (ja)
Inventor
Hiroto Iguchi
浩人 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3739692A priority Critical patent/JPH05235907A/en
Publication of JPH05235907A publication Critical patent/JPH05235907A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To execute the confirmation of an operation of the counter circuit to transmission data through a transmission line even when the monitor is in operation. CONSTITUTION:A specific pattern generating circuit 1 generates a specific pattern S2 and an error insertion circuit 2 inserts an error in the pattern. A selection circuit 3 selects either a specific pattern S3 with the error inserted thereto or a data signal S1 and sends the selected signal to a transmission line 11. An error counter circuit 4 detects and counts an error bit from transmission data of the transmission line 11A special pattern detection circuit 5 detects an output pattern of the special pattern generating circuit 1 and its output S6 is changed, then an inhibit circuit 6 suppresses the count result S5 thereby preventing mis-resistance by the a monitor system such as the monitor due to the result of count of the counter circuit for the confirmation of operation.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は誤り計数回路監視装置に
関し、特に伝送装置を含む伝送路上の伝送データの誤り
を検出し計数する計数回路の正常性を監視する装置に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error counting circuit monitoring device, and more particularly to a device for monitoring the normality of a counting circuit for detecting and counting errors in transmission data on a transmission line including a transmission device.

【0002】[0002]

【従来の技術】従来、伝送路の誤り監視用として装置が
有する誤り計数回路において、誤り計数回路が誤り発生
により正常に動作するかどうかの監視は、装置が動作状
態になると実際に伝送路誤りが生じないかぎり誤り計数
回路の動作確認ができないので、実施していなかった。
2. Description of the Related Art Conventionally, in an error counting circuit included in a device for monitoring a transmission line error, whether or not the error counting circuit normally operates due to the occurrence of an error is monitored when the device is in an operating state. Since the operation of the error counting circuit cannot be confirmed unless the error occurs, it was not carried out.

【0003】[0003]

【発明が解決しようとする課題】従来の誤り計数回路の
動作監視手段では、装置が動作中の回路動作確認を実施
していないため、実際に伝送路の誤りが発生するまで動
作監視ができず、誤り計数回路が故障状態にあっても故
障状態が検出できない。
In the operation monitoring means of the conventional error counting circuit, the circuit operation is not checked while the device is operating, and therefore the operation cannot be monitored until an error occurs in the transmission line. Even if the error counting circuit is in a failure state, the failure state cannot be detected.

【0004】たとえば、現用予備を有する冗長系の伝送
路において、予備側の誤り計数回路が故障状態でも誤り
計数回路の障害検出ができないため、現用系障害の際、
予備側に切替を行なってしまうという欠点があった。
For example, in a redundant transmission line having a working protection, even if the error counting circuit on the protection side is in a failure state, the failure of the error counting circuit cannot be detected.
There was a drawback that it would switch to the spare side.

【0005】[0005]

【課題を解決するための手段】本発明による第1の誤り
計数回路監視装置は、伝送路の伝送データの誤りを計数
する誤り計数回路の動作確認を行なう装置において、ビ
ット誤りを含む特定パターンの信号を発生する特殊パタ
ーン発生誤り挿入手段と、前記特定パターンの信号と前
記伝送路で伝送すべきデータ信号とを入力し前記誤り計
数回路の動作確認試験を指定する監視制御信号に応じて
入力された前記信号のいずれか一方を選択し前記誤り計
数回路が接続された前記伝送路に送出する選択手段と、
前記伝送路から前記特定パターン信号を検出する特殊パ
ターン検出手段と、この特殊パターン検出手段の検出出
力を受け前記誤り計数回路の誤り検出出力の装置監視系
への伝達を抑制するインヒビット手段とを備えている。
A first error counting circuit monitoring apparatus according to the present invention is an apparatus for checking the operation of an error counting circuit that counts errors in transmission data on a transmission line, and a specific pattern including a bit error is detected. A special pattern generation error inserting means for generating a signal, a signal of the specific pattern and a data signal to be transmitted through the transmission line are input, and are input according to a supervisory control signal designating an operation confirmation test of the error counting circuit. Selecting means for selecting one of the signals and transmitting it to the transmission line to which the error counting circuit is connected,
Special pattern detecting means for detecting the specific pattern signal from the transmission path, and inhibit means for receiving the detection output of the special pattern detecting means and suppressing the transmission of the error detection output of the error counting circuit to the device monitoring system. ing.

【0006】本発明による第2の誤り計数回路監視装置
は、伝送路の伝送データの誤りを計数する誤り計数回路
の動作確認を行う装置において、ビット誤りを含む特定
パターンの信号を発生する特殊パターン発生誤り挿入手
段と、前記特定パターンの信号と前記伝送路で伝送され
てくるデータ信号とを入力し前記誤り計数回路の動作確
認試験を指定する監視制御信号に応じて入力された前記
信号のいずれか一方を選択し前記誤り計数回路へ送出す
る選択手段と、前記監視制御信号に応じて前記誤り計数
回路の誤り検出出力の装置監視系への伝達を抑制するイ
ンヒビット手段とを備えている。
A second error counting circuit monitoring device according to the present invention is a device for confirming the operation of an error counting circuit for counting errors in transmission data on a transmission line, and a special pattern for generating a signal of a specific pattern including a bit error. Any of the signals input in response to a supervisory control signal for inputting a generation error insertion means, a signal of the specific pattern and a data signal transmitted through the transmission line and designating an operation confirmation test of the error counting circuit. A selection means for selecting one of them and sending it to the error counting circuit, and an inhibiting means for suppressing the transmission of the error detection output of the error counting circuit to the device monitoring system according to the monitoring control signal are provided.

【0007】[0007]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0008】図1は本発明の第1の実施例を示すブロッ
ク図である。特殊パターン発生回路1,誤り挿入回路2
及び選択回路3で送信側10が構成され、誤り計数回路
4,特殊パターン検出回路5及びインヒビット回路6で
受信側12が構成され、伝送路11により互いに接続さ
れている。
FIG. 1 is a block diagram showing a first embodiment of the present invention. Special pattern generation circuit 1, error insertion circuit 2
The selection circuit 3 constitutes a transmission side 10, the error counting circuit 4, the special pattern detection circuit 5 and the inhibit circuit 6 constitute a reception side 12, which are connected to each other by a transmission line 11.

【0009】次に動作について説明する。送信側10の
特殊パターン発生回路1はある特定パターンの信号、す
なわち特殊パターンS2を発生しており、誤り挿入回路
2にてこの特殊パターンS2にビット誤りを発生,挿入
する。選択回路3は、装置制御回路(図示せず)からの
誤り計数回路4の動作確認試験を指定する監視制御信号
S0の値に応じて誤りを挿入された特殊パターンS3あ
るいは伝送すべきデータ信号S1のいずれか一方を選択
し、伝送路11へ送出する。ここでデータ信号S1と特
殊パターンS2,S3とはパリティビット等の誤り検出
機能を有している。
Next, the operation will be described. The special pattern generation circuit 1 on the transmission side 10 generates a signal of a certain specific pattern, that is, the special pattern S2, and the error insertion circuit 2 generates and inserts a bit error in this special pattern S2. The selection circuit 3 includes a special pattern S3 in which an error has been inserted or a data signal S1 to be transmitted, which corresponds to the value of the supervisory control signal S0 that specifies an operation confirmation test of the error counting circuit 4 from a device control circuit (not shown). Either of them is selected and sent to the transmission line 11. Here, the data signal S1 and the special patterns S2 and S3 have an error detecting function such as a parity bit.

【0010】受信側12の誤り計数回路4は、伝送路1
1から受信したデータ信号S1あるいは特殊パターンS
3より誤りビットを検出し、その計数を行ない、計数結
果S5を出力する。これにより誤り計数回路4の正常性
が確認できる。一方、特殊パターン検出回路5は、伝送
路11上のデータを監視し送信側10の特殊パターン発
生回路1の出力の特殊パターンS2を検出する。ここで
は特殊パターンS2に誤りが挿入されていても(すなわ
ち特殊パターンS3であっても)、特殊パターンを検出
できる機能を有する。特殊パターン検出回路5は特殊パ
ターンS2を検出すると、誤り計数回路4に対する動作
確認試験中であることを認識し、出力S6を変化させ、
インヒビット回路6は、誤り計数回路4の誤り計数結果
出力S5が装置の監視系へ伝達されることを抑制する。
The error counting circuit 4 on the receiving side 12 is connected to the transmission line 1
Data signal S1 or special pattern S received from
The error bit is detected from 3, the counting is performed, and the counting result S5 is output. As a result, the normality of the error counting circuit 4 can be confirmed. On the other hand, the special pattern detection circuit 5 monitors the data on the transmission path 11 and detects the special pattern S2 output from the special pattern generation circuit 1 on the transmission side 10. Here, even if an error is inserted in the special pattern S2 (that is, even if it is the special pattern S3), it has a function of detecting the special pattern. When the special pattern detection circuit 5 detects the special pattern S2, it recognizes that the operation check test for the error counting circuit 4 is being performed, and changes the output S6,
The inhibit circuit 6 suppresses the error counting result output S5 of the error counting circuit 4 from being transmitted to the monitoring system of the apparatus.

【0011】たとえば現用・予備を有する伝送路11に
おいて、予備側の誤り計数回路4を監視するため、送信
側10では定期的に選択回路3の出力S4として誤りを
含んだ特殊パターンS3を選択する。受信側12では、
誤り計数回路4が送信側10で挿入した誤りを計数し計
数結果S5を出力する。同時に特殊パターン検出回路5
は特殊パターンを検出し出力S5をインヒビット回路6
で抑制し、誤り計数回路4の動作確認試験の計数結果に
よる装置の監視系への波及を防止する。
In order to monitor the error counting circuit 4 on the protection side in the transmission line 11 having working / protection, for example, the transmission side 10 periodically selects the special pattern S3 containing an error as the output S4 of the selection circuit 3. .. On the receiving side 12,
The error counting circuit 4 counts the errors inserted on the transmitting side 10 and outputs a counting result S5. At the same time, the special pattern detection circuit 5
Detects a special pattern and outputs the output S5 to the inhibit circuit 6
To prevent the influence of the counting result of the operation check test of the error counting circuit 4 on the monitoring system of the device.

【0012】また送信側10で誤り挿入された特殊パタ
ーンS3を選択していない場合、すなわち通常のデータ
信号S1を選択している場合は、インヒビット回路6は
計数結果S5を抑制せず、監視結果S7として監視系へ
伝達するので、送信側10及び伝送路11におけるデー
タ伝送の正常性を監視できる。
If the transmitting side 10 does not select the error-inserted special pattern S3, that is, if the normal data signal S1 is selected, the inhibit circuit 6 does not suppress the counting result S5 and the monitoring result. Since it is transmitted to the monitoring system as S7, it is possible to monitor the normality of data transmission on the transmission side 10 and the transmission path 11.

【0013】図2は本発明の第2の実施例を示すブロッ
ク図である。本実施例は伝送路15の受信側のみに適用
した例を示し、図1の実施例と同様機能を有する特殊パ
ターン発生回路1,誤り挿入回路2,選択回路3,誤り
計数回路4及びインヒビット回路6から成る。図1の実
施例との相異点は、選択回路3側と誤り計数回路4側と
が同一装置内にあるため、誤り計数回路4に対し動作確
認試験中であることと認識する手段として特殊パターン
検出回路5を必要とせず、インヒビット回路6へ制御信
号線13を介して監視制御信号S0を直接入力している
ことである。
FIG. 2 is a block diagram showing a second embodiment of the present invention. This embodiment shows an example applied only to the receiving side of the transmission line 15, and has a special pattern generating circuit 1, an error inserting circuit 2, a selecting circuit 3, an error counting circuit 4 and an inhibit circuit having the same functions as those of the embodiment of FIG. It consists of six. The difference from the embodiment of FIG. 1 is that as the selection circuit 3 side and the error counting circuit 4 side are in the same device, it is a special means for recognizing that the error counting circuit 4 is undergoing an operation confirmation test. That is, the supervisory control signal S0 is directly input to the inhibit circuit 6 via the control signal line 13 without requiring the pattern detection circuit 5.

【0014】次に動作について説明する。選択回路3に
は、特殊パターン発生回路1及び誤り挿入回路2で生成
されたビット誤りを含む特殊パターンS3と、伝送路1
5より受信されるデータ信号S1とが入力され、監視制
御信号S0の値に応じていずれか一方が選択され誤り計
数回路4へ送出される。誤り計数回路4はこれらの信号
S1またはS3の誤りを計数し計数結果S5を出力す
る。これにより誤り計数回路4の正常性を確認できる。
Next, the operation will be described. The selection circuit 3 includes the special pattern S3 including the bit error generated by the special pattern generation circuit 1 and the error insertion circuit 2, and the transmission line 1.
The data signal S1 received from the input terminal 5 is input, and one of them is selected according to the value of the monitor control signal S0 and is sent to the error counting circuit 4. The error counting circuit 4 counts the errors in these signals S1 or S3 and outputs a counting result S5. Thereby, the normality of the error counting circuit 4 can be confirmed.

【0015】一方、インヒビット回路6は、監視制御信
号S0が誤り計数回路4の動作確認試験を示している場
合は計数結果S5を装置監視系へ伝達せず、誤り計数回
路4の動作確認試験を示していない場合、すなわち通常
のデータ信号S1の監視を示している場合のみ計数結果
S5を監視結果S7として装置監視系へ伝達する。
On the other hand, when the supervisory control signal S0 indicates the operation confirmation test of the error counting circuit 4, the inhibit circuit 6 does not transmit the counting result S5 to the device monitoring system, but performs the operation confirmation test of the error counting circuit 4. Only when not shown, that is, when the normal monitoring of the data signal S1 is shown, the counting result S5 is transmitted to the device monitoring system as the monitoring result S7.

【0016】この第2の実施例についても、たとえば現
用・予備を有する伝送路において予備側の誤り計数回路
を監視するこことが、定期的に監視制御信号S0を変化
させることで実施できる。
Also in the second embodiment, it is possible to monitor the error counting circuit on the spare side in the transmission line having the working / spare by periodically changing the monitor control signal S0.

【0017】[0017]

【発明の効果】以上説明したように本発明による第1の
誤り計数回路監視装置は、送信側で誤り計数回路の動作
確認試験を指定する監視制御信号に応じて誤りを挿入し
た特殊パターンを送出し、受信側で誤り計数回路を実際
に動作させることで動作チェックを行ない、同時に特殊
パターン検出手段にてこの特殊パターンを検出して誤り
計数回路の試験中であることを受信側に認識させ、誤り
計数回路の動作試験の計数結果による装置監視系への影
響を防止するので、誤り計数回路の動作確認を任意の時
期に行なうことができ、故障発生を早期に検出すること
ができる。また、冗長系の伝送路における予備側の誤り
検出回路の障害検出もできる。
As described above, the first error counting circuit monitoring apparatus according to the present invention sends a special pattern in which an error is inserted according to a monitoring control signal designating an operation check test of the error counting circuit on the transmitting side. Then, the operation check is performed by actually operating the error counting circuit on the receiving side, and at the same time, the special pattern detecting means detects this special pattern to make the receiving side recognize that the error counting circuit is being tested. Since the influence of the counting result of the operation test of the error counting circuit on the device monitoring system is prevented, the operation check of the error counting circuit can be performed at any time, and the occurrence of failure can be detected early. Further, it is possible to detect a failure in the error detection circuit on the spare side in the redundant transmission line.

【0018】また、本発明による第2の誤り計数回路監
視装置も、監視制御信号に応じて誤りを挿入した特殊パ
ターンで誤り計数回路を実際に動作させて動作チェック
を行ない、同時にこの監視制御信号により誤り計数回路
の試験中であることを認識し、誤り計数回路の動作試験
の計数結果による装置監視系への影響を防止するので、
上記と同様の効果を有する。
Also, the second error counting circuit monitoring device according to the present invention also actually operates the error counting circuit with a special pattern in which an error is inserted according to the monitoring control signal to perform an operation check, and at the same time, this monitoring control signal. Recognizes that the error counting circuit is being tested, and prevents the counting result of the error counting circuit operation test from affecting the device monitoring system.
It has the same effect as above.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示すブロック図であ
る。
FIG. 1 is a block diagram showing a first embodiment of the present invention.

【図2】本発明の第2の実施例を示すブロック図であ
る。
FIG. 2 is a block diagram showing a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 特殊パターン発生回路 2 誤り挿入回路 3 選択回路 4 誤り計数回路 5 特殊パターン検出回路 6 インヒビット回路 11,15 伝送路 1 special pattern generation circuit 2 error insertion circuit 3 selection circuit 4 error counting circuit 5 special pattern detection circuit 6 inhibit circuit 11, 15 transmission path

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 伝送路の伝送データの誤りを計数する誤
り計数回路の動作確認を行なう装置において、ビット誤
りを含む特定パターンの信号を発生する特殊パターン発
生誤り挿入手段と、前記特定パターンの信号と前記伝送
路で伝送すべきデータ信号とを入力し前記誤り計数回路
の動作確認試験を指定する監視制御信号に応じて入力さ
れた前記信号のいずれか一方を選択し前記誤り計数回路
が接続された前記伝送路に送出する選択手段と、前記伝
送路から前記特定パターン信号を検出する特殊パターン
検出手段と、この特殊パターン検出手段の検出出力を受
け前記誤り計数回路の誤り検出出力の装置監視系への伝
達を抑制するインヒビット手段とを備えることを特徴と
する誤り計数回路監視装置。
1. A device for checking the operation of an error counting circuit that counts errors in transmission data on a transmission line, and a special pattern generation error inserting means for generating a signal of a specific pattern including a bit error, and a signal of the specific pattern. And a data signal to be transmitted through the transmission line are input, and one of the input signals is selected according to a supervisory control signal that specifies an operation confirmation test of the error counting circuit, and the error counting circuit is connected. Selection means for sending to the transmission line, special pattern detection means for detecting the specific pattern signal from the transmission line, and device monitoring system for receiving the detection output of the special pattern detection means and the error detection output of the error counting circuit. An error counting circuit monitoring device, comprising: inhibit means for suppressing transmission to the error counting circuit.
【請求項2】 伝送路の伝送データの誤りを計数する誤
り計数回路の動作確認を行う装置において、ビット誤り
を含む特定パターンの信号を発生する特殊パターン発生
誤り挿入手段と、前記特定パターンの信号と前記伝送路
で伝送されてくるデータ信号とを入力し前記誤り計数回
路の動作確認試験を指定する監視制御信号に応じて入力
された前記信号のいずれか一方を選択し前記誤り計数回
路へ送出する選択手段と、前記監視制御信号に応じて前
記誤り計数回路の誤り検出出力の装置監視系への伝達を
抑制するインヒビット手段とを備えることを特徴とする
誤り計数回路監視装置。
2. A device for checking the operation of an error counting circuit that counts errors in transmission data on a transmission line, and a special pattern generation error insertion means for generating a signal of a specific pattern including a bit error, and a signal of the specific pattern. And a data signal transmitted through the transmission line, and selects one of the input signals according to a supervisory control signal designating an operation confirmation test of the error counting circuit and sends it to the error counting circuit. An error counting circuit monitoring device, comprising: selecting means for controlling the error counting circuit; and inhibiting means for suppressing transmission of an error detection output of the error counting circuit to a device monitoring system according to the monitoring control signal.
JP3739692A 1992-02-25 1992-02-25 Error counter circuit monitor Withdrawn JPH05235907A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3739692A JPH05235907A (en) 1992-02-25 1992-02-25 Error counter circuit monitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3739692A JPH05235907A (en) 1992-02-25 1992-02-25 Error counter circuit monitor

Publications (1)

Publication Number Publication Date
JPH05235907A true JPH05235907A (en) 1993-09-10

Family

ID=12496373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3739692A Withdrawn JPH05235907A (en) 1992-02-25 1992-02-25 Error counter circuit monitor

Country Status (1)

Country Link
JP (1) JPH05235907A (en)

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990518