JPH0810197Y2 - 半導体素子収納用パッケージ - Google Patents

半導体素子収納用パッケージ

Info

Publication number
JPH0810197Y2
JPH0810197Y2 JP8604689U JP8604689U JPH0810197Y2 JP H0810197 Y2 JPH0810197 Y2 JP H0810197Y2 JP 8604689 U JP8604689 U JP 8604689U JP 8604689 U JP8604689 U JP 8604689U JP H0810197 Y2 JPH0810197 Y2 JP H0810197Y2
Authority
JP
Japan
Prior art keywords
convex portion
semiconductor element
insulating frame
metal
metal base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8604689U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0325242U (US20110009641A1-20110113-C00256.png
Inventor
敏幸 千歳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP8604689U priority Critical patent/JPH0810197Y2/ja
Publication of JPH0325242U publication Critical patent/JPH0325242U/ja
Application granted granted Critical
Publication of JPH0810197Y2 publication Critical patent/JPH0810197Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Die Bonding (AREA)
JP8604689U 1989-07-21 1989-07-21 半導体素子収納用パッケージ Expired - Lifetime JPH0810197Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8604689U JPH0810197Y2 (ja) 1989-07-21 1989-07-21 半導体素子収納用パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8604689U JPH0810197Y2 (ja) 1989-07-21 1989-07-21 半導体素子収納用パッケージ

Publications (2)

Publication Number Publication Date
JPH0325242U JPH0325242U (US20110009641A1-20110113-C00256.png) 1991-03-15
JPH0810197Y2 true JPH0810197Y2 (ja) 1996-03-27

Family

ID=31635462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8604689U Expired - Lifetime JPH0810197Y2 (ja) 1989-07-21 1989-07-21 半導体素子収納用パッケージ

Country Status (1)

Country Link
JP (1) JPH0810197Y2 (US20110009641A1-20110113-C00256.png)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007069306A1 (ja) * 2005-12-14 2007-06-21 Nakamura Sangyo Gakuen Led道路交通信号灯

Also Published As

Publication number Publication date
JPH0325242U (US20110009641A1-20110113-C00256.png) 1991-03-15

Similar Documents

Publication Publication Date Title
JPH0936186A (ja) パワー半導体モジュール及びその実装方法
JPH0810197Y2 (ja) 半導体素子収納用パッケージ
JP3210835B2 (ja) 半導体素子収納用パッケージ
JPH083009Y2 (ja) 半導体素子収納用パッケージ
JP2604621B2 (ja) 半導体素子収納用パッケージの製造方法
JP2571571Y2 (ja) 半導体素子収納用パッケージ
JP3850313B2 (ja) 半導体装置
JP2537835Y2 (ja) 半導体素子収納用パッケージ
JP3420469B2 (ja) 配線基板
JP2537834Y2 (ja) 半導体素子収納用パッケージ
JP4174407B2 (ja) 電子部品収納用パッケージ
JPH0617303Y2 (ja) 半導体素子収納用パツケ−ジ
JP2570765Y2 (ja) 半導体素子収納用パッケージ
JPH0610695Y2 (ja) 半導体素子収納用パッケージ
JP2510585Y2 (ja) 半導体素子収納用パッケ―ジ
JP2764340B2 (ja) 半導体素子収納用パッケージ
JP2543153Y2 (ja) 半導体素子収納用パッケージ
JP2849865B2 (ja) 放熱体の製造方法
JPH06334077A (ja) 半導体素子収納用パッケージ
JPH07211822A (ja) 半導体素子収納用パッケージ
JP4028808B2 (ja) 電子部品収納用パッケージ
JP2670208B2 (ja) 半導体素子収納用パッケージ
JP3881542B2 (ja) 配線基板
JP2515672Y2 (ja) 半導体素子収納用パッケージ
JP3559457B2 (ja) ロウ材