JPH0797823B2 - Image processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing device, and more particularly to an image processing device that outputs a pulse width modulated signal that is pulse width modulated by a pattern signal.

[Prior Art] Conventionally, for example, a dither method using a threshold matrix and a density pattern method are well known as a method of binarizing a halftone image. However, especially when the halftone image is binarized by these methods, there is a drawback that the moire fringes are generated due to the beat of the periodic structure of the halftone dot and the threshold matrix and the image quality is remarkably deteriorated. Further, not only the halftone image but also the line drawing such as characters has a drawback that the edge portion becomes jagged on the stairs.

In order to solve such a drawback, the applicant of the present application has already proposed an image processing apparatus which screens a multi-valued image signal with a pattern pulse signal having a plurality of periods and forms an image based on the screened signal. FIG. 8 is a block diagram of the proposed device. The apparatus includes an identification circuit 13 that recognizes an image tone by detecting whether or not the input image signal 1a corresponds to an edge portion of an image, and a SELECT that changes its value according to the identification result of the identification circuit 13. A signal 19, a timing signal generation circuit 7'for generating a screen clock 12 having a corresponding cycle according to the value of the SELECT signal 19, and a pattern pulse generation for generating a pattern pulse signal 42 according to the screen clock 12. Circuit 3, the pattern pulse signal 42 and the multi-valued image signal
Binary image signal with pulse width modulation by comparing 43 levels 45
Is provided with a comparator 4.

FIG. 9 is an operation timing chart of the configuration of FIG.
The figure is a conceptual diagram showing the density by the ratio of black and white in one cycle of the pattern pulse. Under the above configuration, the identification circuit 13
The SELECT signal 19 changes according to the image tone of the input image signal 16b. The timing signal generating circuit 7'and the pattern pulse generating circuit 3 interlocked therewith are generated by changing the cycle of the pattern pulse signal 42 (screen) at each change of the image tone, and the cycle is the image tone identified by the identifying circuit 13. It is a cycle according to. Therefore, the screen processing is performed with a pattern pulse signal of a short cycle when fine screen adjustment is required, and with a pattern pulse signal of a long cycle when rough screen formation is sufficient. By doing this, each pattern pulse signal 1
The density can be expressed by the ratio of black and white in the cycle (first
(See FIG. 10), the density resolution can be obtained in a portion such as an image edge portion (see FIG. 9).

However, as shown in FIG. 9, for example, if the change of the SELECT signal 19 is switched in the middle of a pattern pulse signal having a long cycle, a black signal will appear twice in the image area per cycle, which is a so-called "black line". Caused the deterioration of the image quality.

[Problems to be Solved by the Invention] The present invention has been made in view of the above conventional example, and an object of the present invention is to provide an image processing apparatus that prevents deterioration of image quality that occurs when pattern signals are switched.

[Means for Solving Problems] In order to achieve the above object, the image processing apparatus of the present invention has the following configuration. That is, a first pulse width modulation signal is generated by pulse width modulating the input image signal with a pattern signal of a predetermined period.
A pulse width modulation signal generating means and a second pulse width for generating a second pulse width modulation signal by pulse width modulating the input image signal with a second pattern signal having a period different from that of the first pattern signal. Modulation signal generation means, selection means for selectively switching between the first pulse width modulation signal and the second pulse width modulation signal for output, and the switching timing in the selection means for the pulse width previously selected And a control means for synchronizing the end of one cycle of the pattern signal used for modulation of the modulation signal.

[Operation] In the above configuration, the first pulse modulation signal generating means generates the first pulse width modulation signal by pulse width modulating the input image signal with the pattern signal of the predetermined cycle,
The second pulse modulation signal generation means generates a second pulse width modulation signal which is pulse width modulated by a second pattern signal having a period different from that of the first pattern signal. These first
When the pulse width modulated signal and the second pulse width modulated signal are selectively switched and output, the switching timing is set to one cycle of the pattern signal used to modulate the pulse width modulated signal selected until then. Works to sync at the end.

[Embodiment] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, an outline of the present embodiment will be described before describing the present embodiment. The image processing apparatus of the embodiment shown in FIGS. 1 (a) and 1 (b) detects image tone (image characteristics) by detecting, for each pixel, whether the input image signal 1a corresponds to, for example, an edge portion of an image. Alternatively, the identification circuit 13 for recognizing
And SE that changes its value according to the discrimination result of the discrimination circuit 13
LECT signal 19 and a synchronous SELECT in which the SELECT signal 19 is changed in synchronization with the synchronization signal 51 having the least common multiple of a plurality of cycles
A synchronous circuit 70 for generating a signal 71 (see FIG. 1 (b)),
A timing signal generating circuit 7 for generating a screen clock signal 12 having a corresponding cycle according to the value of the synchronous SELECT signal 71, and a pattern pulse generating circuit 3 for generating a pattern pulse signal 42 according to the screen clock signal 12. And a comparator 4 which compares the levels of the pattern pulse signal 42 and the multi-valued image signal 43 and outputs a binary image signal 45 which is pulse width modulated.

FIG. 4 is an operation timing chart of FIGS. 1 (a) and 1 (b). In FIG. 4, the SELECT signal 19 of the identification circuit 13
Detects a change in image tone of the input image signal 16b (edge portion, non-edge portion of image, etc.) for each pixel and changes. Furthermore, the SELECT
The signal 19 is input to the synchronizing circuit 70, synchronized in synchronization with the least common multiple cycle of a plurality of cycles (points a and c in FIG. 4), and becomes a synchronous SELECT signal 71. As a result, the timing signal generating circuit 7 changes the cycle of the screen clock 12 each time the synchronous SELECT signal 71 changes. Therefore, the pattern pulse signal 42
Is switched at the end of the least common multiple cycle, the "black streak" as shown in FIG. 9 does not occur and the image quality is improved.

<Arrangement of First Embodiment> FIGS. 1A and 1B are block diagrams of the image processing apparatus according to the first embodiment. In the figure, reference numeral 1 is a video data output unit, which performs A / D conversion of image data from a CCD sensor or a video camera (not shown) and outputs digital image data 1a of a predetermined bit (6 bits in this example) having density information. Output. This digital image data 1a may be temporarily stored in a memory (not shown), or may be input from an external device by communication or the like. The image data 1a from the digital data output unit 1 is 6-bit image data as shown in the figure and is input to the buffer memory 11 in the next stage. The buffer memory 11 is used by the discriminating circuit 13 to take out a desired pixel in the image data in order to discriminate the image tone. The discrimination circuit 13 discriminates the image tone and outputs a SELECT signal 19 corresponding to the image tone. SELECT signal 19 is synchronous circuit 70
Input to the synchronous SE that is synchronized with the common multiple of multiple cycles
It becomes the LECT signal 71. The synchronous SELECT signal 71 is input to the timing signal generating circuit 7 to determine the cycle of the screen clock signal 12. The screen clock signal 12 is input to the pattern pulse generation circuit 3 to form a pattern pulse signal 42 having a corresponding period. Comparator 4 is a pattern pulse signal
42 is compared with the level of the multi-valued image signal 43 analog-converted by the D / A converter 2 via the delay circuit 14 to form a pulse width modulated binary image signal (PWM) 45. In this way, the cycle of the screen clock signal 12 is changed according to the image tone, and the coarse density of the "screen" applied to the multi-valued image signal 43 is changed.

<Image Tone Recognition> The output signal from the buffer memory 11 enters the discrimination circuit 13 at the next stage shown in FIG. The function of this identification circuit 13 is the third
It is the image tone recognition for detecting the edge of the image by the Laplacian filter operation shown in FIG. The hardware circuit of this Laplacian filter is shown in FIGS. 3 (b) and 3 (c).
That is, the image signals 16a, 16 of each line sequentially arranged in the sub-scanning direction.
5b and 16c pass through delay circuits 20a to 20d for one pixel clock and
It is output from two types 17a to 17e. The matrix element which is not "0" of the filter shown in FIG. 3 (a) corresponds to each tap. The outputs of the taps, that is, the parts (17a, 17b, 17d, 17e) corresponding to the coefficient "-1" in FIG. 3 (a) are all added by the adder 52. In addition, the coefficient “4” portion (17c) is multiplied by 4 by the multiplier 50. Then, both are subtracted by the adder 18 to obtain the desired Laplacian output 18a.
This Laplacian output 18a is to be called the amount of edge of the image, that is, the amount representing the "degree" of the edge. This edge amount is compared with the reference data 22 by the comparator 21, and SELECT
Get signal 19. At this time, the output of the identification circuit 13, SELE
The CT signal 19 is a binarized output that outputs "1" when the image edge amount> k and outputs "0" when the image edge amount≤k. However, the parameter "k" at this time
Can be appropriately determined by the reference data 22. In this way, the identification circuit 13 recognizes the image tone of the area formed by the eight image data around the image data of the tap 17c, and outputs the recognition result.
It is output as the SELECT signal 19. Of course, if the step of image adjustment is finely set, for example, if the parameter "k" is set to a plurality of values, the output SELECT signal 19 is set to several bits long, and more detailed image adjustment can be performed.

<Generation of Timing for Selecting Pattern Pulse> The SELECT signal 19 is input to the synchronizing circuit 70, and the synchronizing SELECT signal 71 is obtained from the synchronizing circuit 70. Here, the synchronizing circuit 70 will be described. FIG. 1B shows an example of the synchronizing circuit 70. For example, it is composed of a D type flip-flop 75, the D input of which is the SELECT signal 19, the clock input of which is the synchronizing signal 51 having the least common multiple period, and the Q output of which is the synchronizing SELECT signal 71. Therefore, the SELECT signal generated at any time 19
Changes in synchronization with the end of the least common multiple cycle of a plurality of cycles. This results in which pattern pulse signal 42
Since it is always switched at the end of the pattern cycle, the "black streak" as shown in FIG. 9 does not occur and the image quality is improved.

<Pulse for Screen> The synchronous SELECT signal 71 is input to the timing signal generating circuit 7, and the image clock 15 and the screen clock signal 12 are obtained from the timing signal generating circuit 7. Here, the timing signal generating circuit 7 will be described in detail. FIG. 2 is a block diagram of an example of the timing signal generating circuit 7. The inputs are the master clock 40, the synchronous SELECT signal 71 and the horizontal synchronization signal 41, and the outputs are the pixel clock signal 15 and the screen clock signal 12. The pixel clock signal 15 is generated from the counter 46 in synchronization with the horizontal synchronization signal 41 generated for each line from the horizontal synchronization signal (HSYNC) generation circuit 5.
The horizontal synchronizing signal may be generated internally or may be given from the outside. Further, since this embodiment is applied to a laser beam printer, the horizontal synchronizing signal corresponds to a well-known beam detect (BD) signal. The master clock 40 is cycled down by the counter 46 to become the pixel clock signal 15. The degree of the cycle down is determined according to how much the "fluctuation" occurring in each line of the screen clock signal 12 is suppressed as described later, but is 1/4 in the present embodiment. That is, four master clocks 40
For one pixel clock signal 15 is generated. This pixel clock signal 15 is used for the image data transfer clock and D / A.
Used for latch timing of the converter 2. The frequency divider circuit (1/3) 31 further counts down the pixel clock signal 15. That is, the clock signal 51 obtained from the frequency dividing circuit 31 becomes a clock having a cycle three times coarser than that of the pixel clock signal 15. In the embodiment, it is also the synchronous clock signal 51 having the least common multiple period. The selector 30 is a pixel clock signal 15 or a coarse clock signal having a cycle three times that of the pixel clock signal 15 according to the synchronous SELECT signal 71.
Select 51. The one selected by the selector 30 becomes the screen clock signal 12.

Since the synchronous SELECT signal 71 takes the value of logic "1" for the image edge part, the screen clock signal 12 is selected as the image edge part → pixel clock signal 15 image non-edge part → clock signal 51. The screen clock signal 12 is converted into a pattern pulse signal 42 having a predetermined shape by the pattern pulse generation circuit 3. In the case of this embodiment, it is a triangular wave signal. This pattern pulse signal is input to the comparator 4 for binarizing image data by PWM (pulse width modulation).

<Second Embodiment> FIG. 5 is a block diagram of an image processing apparatus according to the second embodiment. The same components as those in FIG. 1A are designated by the same reference numerals and the description thereof will be omitted. The image processing apparatus shown in FIG. 5 includes an identification circuit 13 for recognizing the image tone of a multi-valued image signal 16b, and a plurality of pattern pulse generating means 3a, 3b for generating pattern pulse signals 42a, 42b of two different cycles, for example. And a plurality of screening processing means 4a, 4b for performing the screening processing of the multi-valued image signal 43 for each of the pattern pulse signals 42a, 42b having different periods and outputting the binary image signals 45a, 45b pulse-width modulated.
And a binary image signal 45a, 45b of a different system is selectively applied based on the recognized image tone to change the substantial screening period to cycle switching means, and a minimum of a plurality of periods based on the time when the recognized image tone changes. A synchronizing circuit 70 and a selector 72 for switching the screening period in synchronization with the common multiple period are provided.

<Timing Generation Circuit> FIG. 6 is a circuit diagram of the timing signal generation circuit, and FIG. 7 is an operation timing chart of the configuration of FIG. In FIG. 6, the timing signal generation circuit 90 divides the master clock signal 40 by counters 91 and 92, respectively. The counter 91 forms the screen clock signal 12a, which corresponds to the pixel clock signal. The counter 92 forms the screen clock signal 12b by further dividing the pixel clock signal by three.
The clocks are input to the pattern pulse generation circuits 3a and 3b, respectively. The screen clock signal 12b is used as a clock signal for synchronization. Therefore, the end of the LCM cycle is always the next screen clock signal 12a or 12b.
Is the beginning of. The counters 91 and 92 are reset by the HSYNC signal 41 in order to synchronize each line. Thus, the continuity of the selection of the pattern pulse signal and its modulation can be easily obtained.

<Screen Processing> In FIG. 7, the pattern pulse signals 42a and 42b are simultaneously generated. Along with this, the binarized image signals 45a and 45b are simultaneously formed. The synchronous SELECT signal 71 selectively outputs the binarized image signals 45a and 45b in synchronization with the least common multiple cycle. Therefore, the screened image signal 45 having the resolution of the image edge portion and being continuous as a whole is output.

In the screening process of the above embodiment, the fine image is composed of the pixel clock signal 15 (or 12a) and the coarse image is composed of the clock of 3 pixel cycles. However, this is only an example, and there is a difference between the two. If you choose, you will meet the original purpose. Also,
It is obvious that it is within the scope of the present invention to have not only two kinds of screen cycles to be switched but also several kinds and to switch the screen clock signal in synchronization with the least common multiple cycle thereof.

EFFECTS OF THE INVENTION As described above, according to the present invention, the first pulse width modulation signal obtained by the first pattern signal and the second pulse width modulation signal obtained by the second pattern signal are combined. As the timing for selectively switching and outputting, since it is arranged to synchronize with the end of one cycle of the pattern signal used for the modulation of the pulse width modulation signal selected until then,
There is an effect that it is possible to prevent the rounding of edges and the inadvertent edge enhancement that have occurred at the timing of the conventional switching selection, and it is possible to reproduce an image with high gradation and high resolution.

Further, not the first and second pattern signals but the pulse width modulated first and second pulse width modulated signals themselves are selectively switched and output, so that the above-mentioned edge rounding and undesired edges are generated. This has the effect of more reliably preventing the occurrence of emphasis.

[Brief description of drawings]

1A and 1B are block diagrams of the image processing apparatus of the first embodiment, FIG. 2 is a block diagram of an example of the timing signal generating circuit 7, and FIG. 3A is a concept of a Laplacian filter. FIGS. 3 (b) and 3 (c) are block configuration diagrams of an example for realizing a Laplacian filter, FIG. 4 is an operation timing chart of the configuration of FIGS. 1 (a) and (b), and FIG. FIG. 6 is a block diagram of the image processing apparatus of the second embodiment, FIG. 6 is a circuit diagram of an example of the timing signal generation circuit 90, FIG. 7 is an operation timing chart of the configuration of FIG. 5, and FIG. A block diagram, FIG. 9 is an operation timing chart of the configuration of FIG. 8, and FIG. 10 is a conceptual diagram showing the density by the ratio of black and white in one cycle of the pattern pulse. In the figure, 1 ... video data output section, 2 ... D / A converter,
3,3a, 3b …… Pattern pulse signal generator, 4,4a, 4b …… Comparator, 5 …… Horizontal synchronization signal generation circuit, 6 …… Master clock oscillator, 7,90 …… Timing signal generation circuit,
11 …… Buffer memory, 12,12a, 12b …… Screen clock signal, 13 …… Identification circuit, 19 …… SELECT signal, 14 ……
Delay circuit, 15 …… Pixel clock signal, 40 …… Master clock signal, 43 …… Analog image data, 44 …… Digital image data, 45,45a, 45b …… PWM signal, 51 …… Synchronous clock signal, 70 …… Synchronous circuit, 71 ... Synchronous SELECT signal.

Claims (1)

[Claims] 1. A first pulse width modulation signal generating means for generating a first pulse width modulation signal by pulse width modulating the input image signal with a pattern signal of a predetermined cycle; and the input image signal, Second pulse width modulation signal generating means for generating a second pulse width modulation signal which is pulse width modulated by a second pattern signal having a period different from that of the first pattern signal; the first pulse width modulation signal and the second pulse width modulation signal generating means. Selecting means for selectively switching and outputting the pulse width modulated signal and switching timing in the selecting means at the end of one cycle of the pattern signal used for modulating the pulse width modulated signal which has been selected so far. An image processing apparatus, comprising: a control unit that synchronizes the control unit.