JPH0131344B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal processing device that processes a video signal so that it can be used for image display, printing, recording, or the like.

For example, in a video signal processing device such as a facsimile machine or a digital copying machine, the image signal is divided into two values, white and black, and transmitted, so when the original has gradation such as a photograph, the screen becomes mosaic-like. It becomes very difficult to see. For this reason, a so-called dither method has been used in which the threshold level for binarization is switched for each pixel of video data to perform binarization, thereby transmitting gradations based on the area ratio of black points. However, this method has poor performance for expressing thin lines.
In particular, it had the disadvantage that thin lines with low contrast in midtones disappeared. Moreover, the above-mentioned drawbacks tend to be exacerbated as the dither value is increased to improve the gradation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video signal processing device that eliminates the above-mentioned drawbacks and can obtain high-quality reproduced images.

That is, the present invention includes a video signal input means for inputting a video signal, and a halftone processing means 10 for performing halftone processing on the video signal input from the video signal input means and outputting a halftone-processed binary signal.
13, 15 to 19, 24 to 27, 29, the video signal input from the video signal input means is converted into a binary signal for each pixel, and the 2 value of the central pixel is
Edge correction signal output means 2 that determines whether or not the center pixel is an edge portion based on the value signal and the binary signals of pixels before and after it, and outputs an edge correction signal.
3, 14, 28, 31 to 41, correction means for correcting the binary signal output from the halftone processing means based on the edge correction signal output from the edge correction signal output means and outputting a reproduced signal; 42,
43, the correction means outputs the edge correction signal as a reproduction signal regardless of the binary signal output from the halftone processing means when the edge correction signal output means determines an edge portion. , when the edge correction signal output means does not discriminate the edge portion, the 2 output from the halftone processing means
The present invention provides a video signal processing device that outputs a value signal as a reproduction signal. The present invention will be explained in detail below based on illustrated embodiments.

FIG. 1 is a functional block diagram of a video signal processing device, such as a facsimile machine, according to the present invention. 1 is an image reading device, 2 is a signal binarization circuit, 3
is an image writing device. The reading device 1 includes, for example, a light source, a solid-state image sensor (CCD), and, if necessary, a mechanical sub-scanning device. The image signal read by the CCD is converted into binary values of white or black by the binarization circuit 2, and transmitted to the writing device 3 for image reproduction. The writing device 3 is constituted by a device capable of expressing binary values, such as an inkjet printer or a laser beam printer. Various methods have been published in the past in which analog contour enhancement is performed in front of the binarization circuit 2 in order to clarify fine lines. Furthermore, regarding the binarization circuit 2 itself, various measures have been devised such as modulating the threshold level with an image signal to enhance contours and prevent shading. For example, there are Japanese Utility Model Application Publication No. 54-17313, Japanese Utility Model Application Publication No. 54-37039, and Japanese Patent Application Publication No. 54-21219.

Figure 2 shows a dither circuit that prepares a large number of the above-mentioned binarization circuits, binarizes them by changing the threshold level of each binarization circuit, and selects and reads out their outputs in time series for transmission. 1 is a block diagram of a video signal processing device having a video signal processing device; Here, the case where the dither value is four values is shown, where 4 is a reading device, 5 is a quaternary circuit, 6 is a dither circuit, 7 is a control circuit, and 8 is a writing device. FIG. 3 shows an example of the dither matrix. For four mutually adjacent pixels, the density is 1 to 4 as shown in Figure 3a.
If a threshold level of up to is given, five gradations from b to f in the figure can be obtained. In other words, four pixels come together to express five levels of gradation. However, one of the drawbacks of this method is that the ability to express fine lines is lower than when dithering is not performed. For example, if there is a thin black line with a density of 5 on a white background with a density of 0,
Although there is no problem in principle, in reality, the density of the black thin line usually decreases due to the limited resolution of the optical system of the reading device 4. When the density falls below density 4, thin lines begin to be missing. Therefore, if there is a thin line with low contrast on a midtone background, a significant drop in resolution will occur. The situation is shown in Figure 4 A and B.
and shown in FIGS. 5A and 5B. FIG. 4A shows a case where there is a thin line with a density of 3.5 and a width of 5 pixels on a ground with a density of 1.5, and the entire line is binarized at a threshold level of density 2.5 without dithering. FIG. 4B is an example of a binarized image, in which thin lines are perfectly reproduced. FIG. 5A shows a case where the same original as in FIG. 4A has been subjected to the dithering shown in FIG. 3. In this case, the reproduced image after binarization becomes as shown in FIG. 5B, and the distinction between the background and thin lines becomes unclear. In this embodiment, in order to eliminate such a drawback, the end of the black line is made black regardless of the dither value, and the ground portion close to the black line is made white regardless of the dither value. We are getting results. FIG. 6B shows an image obtained when the original shown in FIG. 5A is binarized by the method of the embodiment of the present invention. Compared to FIG. 5B, the resolution of fine lines has been greatly improved. Note that FIG. 6A shows how the threshold level changes to obtain FIG. 6B. FIG. 7 is a specific example of an applied circuit of a binarization circuit realizing the present invention. 10-13 is 4
These are comparators for value conversion, and their threshold levels are created by resistors 15-19. 14 is a comparator provided independently of the comparators 10 to 13, the threshold level of which is applied via the resistor 22 from the dividing point of the resistors 20 and 21, and the input video signal Vin.
The low frequency components of the video signal are added and applied via a low pass filter 23. For example, a Butterworth filter as shown in FIG. 8 is used as the low-pass filter 23. Assuming that the resistance value of the resistor 48 is R and the capacitance of the capacitor 19 is C, this filter exhibits a delay amount CR in the DC region.
A delay circuit is provided at 9 in FIG. 7 for time correction. For the delay circuit 9, for example, an LC delay line as shown in FIG. 9 is used. 50-53 are coils, 5
4 to 58 are capacitors, and 59 and 60 are matching resistors. The DC resistance 48 and resistance 22 of the low-pass filter 23 shown in FIG. 7 provide a constant amount of attenuation even in the DC region. The comparator 14 configured in this manner can pick up video signals whose duty is significantly different between white and black of an original, and even signals of thin black lines with low density. The outputs of all comparators are transmitted to the next stage via latch circuits 24-28. 29 is a data selector circuit, for example, manufactured by Texas Instruments in the United States.
Uses SN74S151. The lower bit ψ _A of the address signal line is switched for each pixel, and the upper bit ψ _B is 1
It is switched for each line. 46 and 47 are flip-flops, 45 is an inverter, 2ψt is a transfer clock signal synchronized with the video signal Vin, and _ψSYNC is a synchronization signal generated for each line. 44 is a delay circuit which provides the same amount of delay as 9 to achieve synchronization with the video signal. The signal passing through the latch circuit 28 is sequentially delayed one pixel by one pixel by shift registers 31 and 32, exclusive OR gates 33, 34, AND gates 35-38, and
3. A black emphasis signal P and a white emphasis signal q are obtained by the OR gate 40. The time chart is shown in Figure 10. The symbol used in Figure 10 is the 7th
These correspond to the symbols written near each signal line in the diagram. Here, for example, when the black emphasis signal p becomes H, the video signal becomes H unconditionally at the output of the OR gate 42. Further, when the white emphasis signal q becomes H, the video signal becomes L unconditionally and is outputted by the inverter 41 and the AND gate 43. 30
is a shift register, which is used to delay the video signal by one pixel since contour correction is performed centering on the signal n. Therefore, in the circuit shown in FIG. 7, the low-pass filter 23, comparator 14, latch circuit 28, shift registers 31, 32, gate circuits 33 to 40, and inverter 41 convert the input video signal into a binary signal for each pixel. Based on the binary signal (n) of the central pixel and the binary signals (mo) of the pixels before and after it, it is determined whether the central pixel is an edge portion or not, and an edge correction signal (p,
q) is output. Final binarized output
As shown in FIG. 10, Vout is dithered only in the shaded areas, resulting in a signal in which the edge areas of the image are clearly defined in white and black. That is, the OR gate 42 and the AND gate 43 output the emphasis signal with priority over the dither output. When the image signal obtained in this manner is sent to a writing device, an image as shown in FIG. 6, for example, is obtained.

Only one of the black emphasis signal p and the white emphasis signal q may be used. Furthermore, the shift registers 31 and 32 may be delay circuits. Latch circuits 24-28 may be omitted if the video signal is sampled and held and latching is not necessary. That is, the shift registers 30 and 31 can also have a latch function. Comparator 14 threshold level
Vs may be fixed. In that case, the low-pass filter 23 and delay circuits 9 and 44 may be omitted. Furthermore, instead of providing the comparator 14, the edge emphasis signal m may be obtained from another comparator, for example 11 or 12. Furthermore, comparator 14, latch 2
8. Although one system of shift registers 31, 32 and gate circuits for obtaining signals p and q is shown, by preparing multiple systems and having different threshold levels for each comparator, it is possible to apply a wide range of intermediate tones. It is also possible to use a method that emphasizes the contour. A block diagram of a specific circuit example in that case is shown in FIG. Here, an example of a four-level dither will be shown. Reference numeral 61 denotes an A/D converter, which consists of a group of comparators and a latch function. 62
is a data selector. 63 to 66 are contour detection circuits, for example, in FIG. 7, comparator 1
4. There are four groups of circuits corresponding to the latch 28, shift registers 31, 32, and gates 33-40. Since the contour detection circuits 63 to 66 output black emphasis signals P ₀ to p ₃ and white emphasis signals q ₀ to q ₃ respectively, they are passed through AND gates 67 and 68 to the final black emphasis signal P and white By obtaining the emphasis signal Q, fine outline emphasis can be realized. Note that FIG. 11 shows only functional elements, and other control circuits and the like are not shown.

As described above, this embodiment includes a dither processing circuit that dithers a video signal, an emphasizing circuit that emphasizes the outline of the video signal, and an output of the emphasizing circuit that is prioritized over an output of the dither processing circuit. Therefore, it is possible to obtain an image signal that can clearly reproduce fine lines regardless of the dither output, and it is also possible to obtain gradation in areas other than the contour areas. In other words, according to this embodiment, a video signal processing device that satisfies both gradation and edge enhancement can be realized. 12th
The figure shows a block diagram of a digital copying machine to which the binarization circuit of this embodiment is applied. The original 72 is sub-scanned by the optical reader 73 and the one-dimensional CCD 7
Step 4 converts it into an electrical signal. 83 is a driver circuit that controls charge transfer of CCD 74, and oscillator (1) 87
serves as its master clock. 75 is a video intensifier for amplifying the video signal to a required level, and has an AGC circuit 84 for level stabilization. 76 is an A-D converter (multi-value circuit), 77
is a dither circuit (binarization circuit) according to an embodiment of the present invention, 8
5 is its control circuit. Here, the binarized video signal is stored in buffer memory 78. The buffer memory 78 is used for time adjustment since the clock read by the CCD 74 and the clock written by the laser 80 are generally different. Therefore, when reading, the oscillator for CCD74
(1) Receive the clock from 87, and when writing, receive the clock from the write oscillator (2) 89. The switching is performed by the horizontal synchronizing signal H_SYNC generated by the writing device 81. 86 is an address counter necessary for its control. 79 is a laser drive circuit, and 80 is a semiconductor laser. A writing device 81 includes a polygon scanner, an electrostatic latent image forming device, a developing device, a fixing device, etc., and outputs a copy 82. A counter 88 is used to operate the AGC 84 outside the image band of the video signal. Reference numeral 91 denotes a sequence controller that controls the operation of the entire apparatus, and performs copying operations by manually operating the operation panel 90.

As explained above, according to the present invention, when an edge portion is determined, the edge correction signal is output as a reproduction signal regardless of the binary signal output from the halftone processing means, and when an edge portion is not determined, the edge correction signal is output as a reproduction signal. Since the apparatus is configured to output a binary signal outputted from the halftone processing means as a reproduced signal, it is possible to reproduce both halftones and fine lines, for example, and to obtain a high-quality reproduced image.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a video signal processing device, Fig. 2 is a block diagram of a video signal processing device using a dither method, Fig. 3 is a diagram showing an example of a four-level dither matrix, and Fig. 4 A, B 5A and 5B are diagrams for explaining line representation without dithering, Figures 5A and B are diagrams illustrating halftone line representation with dithering, and Figures 6A and B are diagrams showing lines according to the present invention. A diagram for explaining the expression, FIG. 7 is a circuit example diagram for realizing the present invention, FIG. 8 is a diagram showing an example of the delay circuit used in FIG. 7, and FIG. 9 is a diagram for explaining the expression.
The figure shows an example of the low-pass filter used in Fig. 7, Fig. 10 is an operation timing diagram of Fig. 7, Fig. 11 is another implementation circuit diagram, and Fig. 12 is a digital copy to which the present invention can be applied. FIG.

Claims (1)

[Scope of Claims] 1. Video signal input means for inputting a video signal; Halftone processing means for performing halftone processing on the video signal input from the video signal input means and outputting a halftone-processed binary signal. , converting the video signal inputted from the video signal input means into a binary signal for each pixel, and determining whether the central pixel is an edge portion based on the binary signal of the central pixel and the binary signals of the pixels before and after it. edge correction signal output means for outputting an edge correction signal; correcting the binary signal output from the halftone processing means based on the edge correction signal output from the edge correction signal output means; and a correction means for outputting the edge correction signal, and the correction means reproduces the edge correction signal regardless of the binary signal output from the halftone processing means when the edge correction signal output means determines an edge portion. A video signal processing device characterized in that the binary signal output from the halftone processing means is output as a reproduction signal when the edge correction signal output means does not discriminate an edge portion.