JPS62183676A - Picture processor - Google Patents

Abstract

PURPOSE:To prevent the generation of moire of a picture and stripes by providing a comparison means for comparing an analog picture signal and a reference signal and a decision means for deciding a generation timing and a cycle fo a reference signal based on a set value and changing the conversion characteristic of a gamma converting means correspondingly to the set value. CONSTITUTION:A delay signal generating circuit 16 outputs a delay signal 18 having plural different delay times in which a preset time is delayed. A select signal output device 19 changes over the select signal 20 corresponding to the input of a horizontal synchronizing signal 13 according to a mode preset to a preset circuit 25. An analog switch 17 selects and outputs one signal of the delay signals 18 correspondingly to the select signal 20. The conversion is performed by a digital picture signal D/D converter 24, the output value thereof is latched to a latch circuit 1 and converted into the analog picture signal 15 by a D/A converter 2. This D/D converter 24 changes the conversion characteristic based on the set value of the preset circuit 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that manually processes image information and outputs it as binary image information by pulse width modulation.

[Prior Art] Conventionally, methods of reproducing halftone images using a dither method or a density pattern method are known. However, in any case, using a small size threshold matrix
Sufficient gradation cannot be obtained. Therefore, when trying to express gradation using a large-sized threshold matrix,
There was a problem in that the resolution was extremely reduced.

Separately, the applicant has proposed a new method for expressing gradation while maintaining high resolution with a relatively simple device configuration. This method involves converting the manually generated digital image signal into an analog signal in order to obtain halftone gradation when converting the digital image signal into a binary value and forming an image using a laser beam printer, etc. By comparing the signal with a periodic pattern signal such as a triangular wave, a binarized signal subjected to pulse width modulation is generated.

FIG. 2 shows an example of a block diagram of a circuit for realizing this method.

A digital image input signal is latched by a latch circuit 1 in synchronization with a video clock 11. This video clock 11
is a clock obtained by dividing the frequency of the master clock 12 by two using the flip-flop 4 to J-. In addition, the master clock 12
is assumed to be synchronized with the horizontal synchronization signal 13 in advance. Here, the horizontal synchronization signal 13 may be generated internally or may be provided externally. Further, as long as the present device is applied to a laser beam printer, for example, a well-known beam detect (BD) signal may be used. The digital image signal of the latch circuit 1 is converted into an analog image signal by the D/A converter 2, and then
is input to one input terminal of On the other hand, the master clock 12 is frequency-divided to a predetermined period by the frequency divider 5 and the period switching signal, and further divided by two by the J- flip-flop 8, resulting in a clock signal 14 with a duty ratio of 50%. The ratio of the periods of the clock signal 14 and the video clock 11 corresponds to the frequency division ratio of the frequency divider 5. Furthermore, the frequency divider 5 is loaded with a frequency division ratio by the OR signal of the horizontal synchronization signal 13 described above and the ripple carry oud (RCO) signal of the frequency divider 5, so the image signal 15 and the clock signal 14 are , each line is completely synchronized. Clock signal 14 is passed through buffer 9 to pulse pattern generator 10
The image signal 1 is input to the
Matching with the dynamic range of 5 is taken. The pulse pattern generator 10 is composed of a well-known integrating circuit composed of, for example, a resistor and a capacitor, a buffer amplifier for dynamic range adjustment, and the like.

The triangular wave pattern signal output from the pulse pattern generator 10 is input to the other input terminal of the comparator 3 and compared with the analog image signal 15, and pulse width modulation of the image signal 15 is performed.

Here, depending on the image tone of the image, that is, whether emphasis is placed on resolution rather than halftones as in character images, or on reproducibility of halftones as in photographic images, a period switching signal is manually input to the frequency divider 5. This changes the cycle of the clock signal 14 to, for example, the same cycle as the video clock 11 when emphasis is placed on resolution, and the same cycle as the video clock 11 when emphasis is placed on reproducibility of halftones.
The cycle is switched to 2 to 4 times that of 1.

[Problem to be Solved by the Invention 1] In the apparatus using the above-mentioned method, as a result of examination by the present applicant, it is difficult to solve problems that require high resolution such as character images, or delicate gradation such as silver halide photographs. For originals that require high resolution, high-resolution images that are several orders of magnitude better than images obtained using conventional binary processing or dithering methods were obtained. On the other hand, when the document is an image with periodicity in a specific direction, such as a tint image, the conventional 2
It was also found that the so-called moiré phenomenon, which was a major problem in value processing and dithering methods, was significantly reduced.
It has also become clear that this may be noticeable depending on the conditions. This condition refers to cases in which the periodicity of the output image is emphasized; for example, in order to emphasize the reproducibility of halftones, the period of the clock signal is set to be more than twice that of the video clock. Another example is when a well-known process such as edge enhancement is performed in order to sharply make thin lines in an image where resolution is important.

The present invention has been made to improve the above-mentioned drawbacks, and an object of the present invention is to provide an image processing device that can obtain high-quality reproduced images.

[Means for Solving the Problem] As a means for solving this problem, for example, the image processing apparatus of the embodiment shown in FIG.
, a D/A converter 2 as a means for converting multivalued image information into an analog image signal, a comparator 3 as a comparison means, a delay signal generation circuit 16 as a determination means, and a selection signal output device 19
, an analog switch 17 and a frequency divider 15.

[Operation] In the configuration shown in FIG. 1, the delayed signal generating circuit 16 outputs the delayed signal 18 having a plurality of different delay times obtained by delaying the horizontal synchronizing signal 13 by a preset time.

The select signal output device 19 switches the select signal 20 in accordance with the mode preset in the preset circuit 25 in response to the input of the horizontal synchronizing signal 13. In response to this select signal 20, the analog switch 17 outputs a delay signal 18.
One of the signals is selected and output. The digital image signal is subjected to γ conversion by the D/D converter 24, and its output value is latched by the latch circuit 1, and then the D/A converter 2
It is converted into an analog image signal 15 by. Note that this D/D converter 24 changes the γ conversion characteristic based on the setting value of the preset circuit 25.

The frequency divider 5 determines the frequency division ratio of the master clock 12, outputs a signal according to the frequency division ratio in synchronization with the output of the analog switch 17, and inputs the signal to the pulse pattern generator 10 through the flip-flop 8 to J-. . The pulse pattern generator 10 generates a pattern signal 2 having the same period as the manually generated signal.
3 is output to comparator 3. The comparator 3 compares the analog image signal 15 and the pattern signal 23, performs pulse width modulation (PWM), and outputs the signal as a binary code 26.

[Examples] Examples of the present invention will be described in detail below with reference to the accompanying drawings.

[Description of Pulse Width Modulation Circuit (FIG. 1)] FIG. 1 is a block diagram of a pulse width modulation circuit of an image processing apparatus showing an embodiment of the present invention. Here, the same parts as in FIG. 2 are indicated by the same symbols. Descriptions of these same parts will be omitted because they are the same as those described above.

16 is a delay signal generation circuit which inputs a horizontal synchronizing signal and outputs a plurality of (m) output signals obtained by applying a plurality of different types of delays to the horizontal synchronizing signal. Since the delay signal generation circuit 16 inputs the master clock 12, the delay time can be an integral multiple of the master clock 12, or an (integer + α) times (0 × α × 1). Reference numeral 17 denotes an analog switch that selects one of the m delay signals 18 output from the delay signal generation circuit 16. The selection instruction for this analog switch 17 is made by a select signal 20 from a select signal output device 19. The select signal output device 19 counts the horizontal synchronizing signal 13 and determines the select signal 20 corresponding to the count value according to the value set in the preset circuit 25. In this way, information such as 200 types of select signals and their repetition patterns are set in the preset circuit 25. Further, 24 is a D/D converter for adjusting the gradation of the digital image signal, and has, for example, a plurality of γ conversion tables, and one γ conversion table is selected by the preset circuit 25 and the period switching signal. It has become. In addition,
It is assumed that the select signal 20 is composed of nm class (15 m) codes or signal levels, and is sequentially switched in synchronization with the horizontal synchronizing signal 13.

Now, the delay signal generation circuit 16 is set so that two signals are generated: a signal a with zero delay, that is, a timing equal to the horizontal synchronization signal 13, and a signal A with a delay amount of three pulses of the master clock 12. and select signal output device 1
The analog switch 1 is connected to the analog switch 9 so that the signal a and the signal A are alternately selected each time the horizontal synchronizing signal 13 is input.
7 to output the select signal 20. Next, the frequency divider 5 is set to divide the master clock 12 by three based on the synchronization switching signal.

[Timing Description (FIG. 3)] FIG. 3 shows the timing of each signal under the above settings.

In FIG. 3, signals a and b are output signals with different delay times from the aforementioned delayed signal generation circuit 16, and signal A rises at timing T1 delayed by three pulses of the master clock from the rise of signal a. . master clock 1
The output signal of the frequency divider 5, which divides 2 into 3, is further divided by 2 by the flip-flop 8 to J-, and the duty ratio is 50%.
It becomes a signal. The clock signal 22 which is the output of the flip-flop 8 at J- when the signal a is selected is shown as a clock a', and the clock signal 22 when the signal is selected is shown as a clock b'. The clock a' is raised at the falling edge of the signal a (the falling edge of the horizontal synchronizing signal 13) (timing T2), and the clock b' is raised at the falling edge of the signal S (timing T3), and then the horizontal synchronizing signal 13 is input. The signal continues to be output as a square wave with a duty of 50% at a cycle equal to six cycles of the master clock 12 until the signal is output.

The video clock 11 outputted from the flip-flop 4 to J- is a clock obtained by dividing the master clock 12 by two, as shown in the figure, and is reset by the horizontal synchronizing signal 13.
At timing T2, the horizontal synchronization signal 13 falls and becomes HIGH when the master clock 12 rises.
Thereafter, until the horizontal synchronizing signal 13 is input manually, it is output as a clock No. 8 having the above-mentioned period. In synchronization with this video clock 11, for example, a third
An analog image signal 15 as shown in the figure is output. Here, To is a non-image area from generation of the horizontal synchronization signal 13 until actual drawing is performed.

Also, when the signal a is selected, the pulse pattern generator 1
Triangular wave pattern signal 23 (23-1
) and the triangular wave pattern signal 23 (23-2) when the signal is selected are also shown, and the corresponding waveforms of the binarized signal 26 are also shown.

As mentioned above, the select signal 20 from the select signal output device 19 is output by switching the analog switch 17 for each horizontal line, and outputting the signal a from the delayed signal generating circuit 16.
The pattern signal 23 changes line by line like triangular waves 23-1 and 23-2 in FIG. 3 because the signals 2 and 2 are output alternately.

Therefore, when the analog image signal 15 has a waveform as shown in FIG. 3 for two consecutive lines, the output of the comparator 3
The value code 26 becomes an output signal 30.31 for each triangular wave 23-1 and 23-2, respectively.

[Explanation regarding pixel growth (Fig. 4 (a) (b), Fig. 5 (a) (b))] Fig. 4 (a) shows how the pixel grows when the above operation is performed.
Shown in (b).

FIG. 4(a) is a diagram showing pixel growth when the circuit shown in FIG. 2 is used, and FIG. 4(b) is an example of a reproduced pixel when the circuit shown in FIG. 1 of this embodiment is used. This figure shows the same as described above. Now, since the period of the pattern signal 23 is three times that of the video clock, each pixel grows centered on the hatched portion near the center of each three pixels.

In the case of FIG. 4(a), it can be seen that strong correlations appear as lines at three dot intervals in the vertical direction. On the other hand, in Figure 4(b), the vertical correlation is weakened, and a new weak correlation appears in the diagonal direction.
It can be seen that the strong correlation disappears as a whole.

In order to investigate the degree of moiré when reproducing tint images using a laser beam printer, we actually used an image reader with a resolution of 400 dots/inch (1 inch = 2.54 cm) and a laser beam printer. I read the image of a commonly used 75-line dot document using an image reader and reproduced it using a laser beam printer. As a result, when the circuit shown in FIG. 2 was used, line-shaped moiré occurred at approximately 15 dot intervals in the sub-scanning direction, but when the circuit shown in FIG. It was at a level with almost no problems.

The moiré described above is thought to be caused by the beat phenomenon caused by the synchronization of the halftone image and the output pixels. The results of the simulation are shown below. In this figure, Taniuchi shows one dot of a 75-line halftone original, and each square is one dot expressed at a resolution of 400 dpi.
Shows pixels.

FIG. 5(a) shows the output level of the comparator 3 when processed by the circuit configured as shown in FIG. 2. , a dot that is wider than the other dot rows appears in every fourth row. Therefore, moiré occurs at this dot interval. On the other hand, in FIG. 5B, which is applicable to this embodiment, the dots in each row in the main scanning direction have approximately the same size, and it can be seen that there is almost no correlation between the dots.

[Explanation of other pixel growth examples (Fig. 6(a) to (C)
, FIGS. 7(a) to (c))] FIGS. 6(a) to (C) show an example of pixel growth when the generation timing of the pattern signal 23 is changed from the case of FIG. 4(b). It is a diagram.

Compared to FIG. 4(a), the growth centers of the pixels indicated by diagonal lines are dispersed, and moiré is reduced. However, in Figure 6(b), the correlation in the sub-scanning direction has disappeared, but instead, a line appears diagonally from the upper left to the lower right, although it is slightly weakened, and this is the cause. Moiré occurs. Therefore, in FIGS. 6(a) to (-C), the shape of FIG. 6(a) or FIG. 6(C) tends to be less likely to cause moiré than the shape of FIG. 6(b). be.

By the way, in the above study, the following facts were found.

That is, (a), (b) in FIG. 4 and (a) in FIG.
As shown in ~(C), the timing of the pattern signal for each scanning line is shifted, the same image signal is input as a digital image signal, and the same γ table of the D/D converter 24 is used for image output. The fact is that if this is done, the gradation of the output image will be different in each case. This trend shows a strong vertical correlation as shown in Figure 4 (a).
This is due to the fact that γ is the lowest, and in FIG. 4(b), where no particularly strong correlation appears, γ is the highest. This seems to be due to the following reasons.

To explain using FIGS. 7(a) to 7(d), first, in a region with low density, there is little correlation between each pixel in FIG. 7(a) to (d).
The density in b) is lower than that in FIG. 7(a). This is because the image shown in FIG. 7(a), where the correlation between pixels is strong, appears darker due to edge effects in the development characteristics of electrophotography and visual characteristics. On the other hand, in a region where the density is higher than that to a certain extent, it is presumed that the image shown in FIG. 7(d) becomes darker than that shown in FIG. 7(c) for the same reason. Of course, it is fully conceivable that characteristics such as the MTF of the photoreceptor may also be taken into consideration. Therefore, in order to correct this, the γ table of the D/D converter 24 is switched by the signal of the preset circuit 25 shown in FIG.
In various cases such as those in (C), it is sufficient to ensure that the output image always has the optimum gradation.

In the present embodiment, the shift amount of the pattern signal 23 in the main scanning direction is an integer multiple of the master clock 12, but as described above, this is (integer + α) times (0<
Of course, α(1) may also be used. Furthermore, the method of shifting in the sub-scanning direction is explained using an example in which the shift returns to the original state every 2 to 4 main-scan line periods in the above explanation.
Of course, the period itself may be any period larger than this.

[Description of other embodiments (FIG. 1) (FIG. 8)] In the embodiments described above, the period of the pattern signal 23 is set to be three times that of the video clock 11 in order to emphasize the reproducibility of halftones. On the other hand, if resolution is important, it has been confirmed that it is better to make the period of the pattern signal 23 equal to that of the video clock 11. Even when a halftone image is reproduced in this manner, moire hardly occurs in many cases, but periodicity may be emphasized by performing well-known edge enhancement processing, for example, and moire may become more noticeable. Even in such a case, it is possible to make moire inconspicuous as in the case of the above-mentioned example.

To give a specific example, the delay signal generation circuit 16 in FIG.
For example, as in the previous embodiment, settings are made so that a signal a with zero delay and a signal C with a delay amount of one period of the master clock 12 are generated. In addition, the select signal output device 19
In this case, the symbol a and the signal C are alternately selected each time the horizontal synchronizing signal 13 is input. As a result, the analog switch 17 outputs the signal a and the signal C alternately for each scanning line. Frequency divider 5 is master clock 1
2 is not divided into a null state by the period switching signal.

FIG. 8 shows the pixels of the output image output by the circuit of FIG. 1 set as described above. In this figure, the pixels of each output image grow around the shaded area.

Of course, even in this case, the shift ff1 (main scanning direction) of the pattern signal does not have to be one time the master clock 12, but may be (integer+α) times (0<α<1). However, if the shift 2 is too large,
Since distortion is noticeable in line drawings and the like, it is desirable to keep the amount of shift within the range of 0 to ±1 pixel, especially in the case of images where resolution is important.

As can be seen from FIG. 8, the pattern signals on the first and second lines are delayed by one cycle of the master clock 12 (that is, 1/2 of the video clock 11), so the pattern signals on the first and second lines are Each pixel is shifted by 172 pixels. In this way, the occurrence of stripes and moiré in the sub-scanning direction are suppressed.

In this embodiment, since the settings are made to place emphasis on resolution, there is a tendency that no emphasis is placed on the deterioration of gradation itself as in the case of the above-mentioned embodiments. but,
It is effective to select the γ conversion table of the D/D converter 24 as in the case of the previous embodiment. Incidentally, as described above, one type of γ conversion table is determined by the combination of the period switching signal of the frequency divider 5 and the output of the preset circuit 25.

Furthermore, although not shown, a relationship is created between the output of the preset circuit 25 and the amount of edge enhancement such that one determines the other, and for example, the amount of edge enhancement is determined depending on the degree of phase evenness of the pattern signal. By changing it, you can make more precise adjustments to the image.

In FIG. 1, a random number generator is used instead of the select signal output device 19, and a random number is generated as the select signal 2o in synchronization with the horizontal synchronization signal 13, and the analog switch 1
7, the output signal of the delayed signal generating circuit 16 may be randomly selected manually.

Furthermore, instead of using the select signal output device 19, the delay amount of the delay signal generation circuit 16 can be arbitrarily switched by the horizontal synchronization signal 13, and the phase of the pattern number 23 can be shifted periodically or randomly. Of course, you can do it in any other way.

As explained above, according to this embodiment, the pattern signal 2
By adjusting the phase of 3 for each horizontal line and adjusting the γ of the image signal, it is possible to practically eliminate the moiré phenomenon that is a problem when reproducing images with peripheral texture such as halftone images. It can be made inconspicuous to the point where there is no problem. In addition, at this time, strong correlation in the vertical direction (sub-scanning direction) is removed from the pixel arrangement of the output image, and as a result, pixels are dispersed even in images other than halftone dots, resulting in a visually natural image quality.

[Effects of the Invention] As described above, according to the present invention, there is an effect that moiré, stripes, etc. are eliminated and a high-quality reproduced image can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a pulse width modulation processing circuit of an image processing device according to an embodiment of the present invention, Fig. 2 is a block diagram of a previously proposed circuit, and Fig. 3 shows signals of various parts of the circuit of this embodiment. Timing charts showing an example of waveforms; Figures 4(a) and (b) are diagrams showing pixel growth when using the circuits in Figures 2 and 1, respectively; Figures 5(a) and (b) are diagrams showing pixel growth when using the circuits in Figures 2 and 1, respectively. Figures showing the simulation results. Figures 6 (a) to (C) are diagrams showing pixel growth when the pattern signal generation timing is changed in this example circuit. Figures 7 (a) and (b) are ideal 7(c) and 7(d) are diagrams showing pixel states when FIGS. 7(a) and (b) are printed, respectively. FIG. 8 is a diagram showing an example of a dot arrangement in another embodiment. FIG. 3 is a diagram showing an example of pixel growth. In the figure, 1...Latch circuit, 2...D/A converter, 3
... Comparator, 4.8... Flip-flop in J-, 5... Frequency divider, 10... Pulse pattern generator, 11... Video clock, 12... Master clock, 13... Horizontal synchronization signal, 15... Analog image signal, 16... Delay signal generation circuit, 17... Analog switch, 19... Select signal output device, 2o.
...Select signal, 23...Pattern signal, 24...
・D/D converter, 25... Preset circuit, 26...
・It is a binary code. Patent applicant: Canon Co., Ltd.

Claims (2)

[Claims] (1) An image processing device that inputs multivalued image information, converts it into binary image information, and outputs it, comprising a conversion means for converting the multivalued image information, and multivalued image information converted by the conversion means. a means for converting the analog image signal into an analog image signal, a comparing means for comparing the analog image signal and a reference signal, and a determining means for determining the generation timing and cycle of the reference signal based on a set value, the converting means An image processing apparatus characterized in that a conversion characteristic is changed in accordance with the set value. (2) The image processing apparatus according to claim 1, wherein the conversion means is a gamma conversion means.