JPS62188561A - Picture processor - Google Patents

Abstract

PURPOSE:To smoothly execute the switching of screening period and to improve the resolution of a picture edge by improving the switching timing of the screening period. CONSTITUTION:A SELECT signal 19 of an identification circuit 13 detects a picture tone change (such as edge and non-edge parts) of an input picture signal 16b at each picture element and is changed. Further, the SELECT signal 19 is inputted to a synchronizing circuit 70, where it is synchronized with a screen clock signal 12 applied at that point of time (points (a), (c)) to form a synchronization SELECT signal 71, and a timing signal generating circuit 7 changes the period of the screen clock signal 12 at each change in the synchronization SELECT signal 71. Thus, a pattern pulse signal 42 is switched to be generated newly in synchronism with the end of the period so fat at all times. Thus, no delay time is generated and the resolution of the picture edge is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and in particular to an image processing device that processes a multivalued image signal into a screen using a pattern pulse signal having a plurality of periods and forms an image based on the screening process. The present invention relates to an image processing device that improves images when switching the screening cycle.

[Prior Art] For example, the dither method and the density pattern method using a threshold matrix are well known as methods for binarizing halftone images. However, when halftone images are binarized using these methods, moiré fringes are generated due to beats in the periodic structure of the halftone dots and the threshold matrix, resulting in a significant deterioration of image quality. Furthermore, not only dot images but also line drawings such as characters have the disadvantage that the edges become jagged like stairs.

In order to solve this drawback, the present applicant has proposed an image processing device that screens a multi-value image signal using a pattern pulse signal having a plurality of periods and forms an image based on the screening process. An image processing apparatus has already been proposed that changes the screening cycle by selectively applying pattern pulse signals with different cycles depending on the image tone. However, since this device switches and applies pattern pulse signals of different cycles when the image tone changes, black streaks, white streaks, etc. may occur in the resulting image depending on the timing of the image tone change and the pattern pulse signal switching, for example.

Therefore, the applicant further proposed an image processing device as shown in FIG. The proposed device includes an identification circuit 13 that recognizes the image tone by detecting whether the human image signal 1a corresponds to, for example, an edge portion of an image, and changes its value in accordance with the identification result of the identification circuit 13. 5ELECT signal 19,
a synchronous circuit 70' that generates a synchronous 5ELECT signal 71' which is changed by synchronizing the 5ELECT signal 19 with a signal 51 of the minimum period (longest period) among various pattern pulse periods; a timing signal generation circuit 7' that generates a screen clock 12' of a corresponding period according to the value; a pattern pulse generation circuit 3 that generates a pattern pulse signal 42' according to the screen clock 12'; and a pattern pulse signal 42'.
A comparator 4 is provided which compares the level of the multivalued image signal 45' with the level of the multivalued image signal 45' and outputs a pulse width modulated binary image signal 45'.

FIG. 9 is an operation timing chart of FIG. 8. 9th
In the figure, the 5ELECT signal 19 of the identification circuit 13 changes upon detecting a change in image tone of the human-powered image signal 16b. Furthermore, the 5ELECT signal 19 is input to a synchronization circuit 70',
It is synchronized with the signal 51 of the minimum public debt cycle among the cycles of the various pattern pulse signals 42' (points a and b in the figure), and the synchronization 5EL
EII: becomes T signal 71'.

Therefore, the timing signal generation circuit 7' is synchronous 5ELECT.
The period of the screen clock signal 12' is changed every time the signal 71' changes.

However, if this method is used, the screen clock signal 12
' can not be switched faster than the minimum period of the pattern pulse signal 42', so the time t1, t2 from the edge of the image
This has the drawback of causing a switching delay, resulting in poor edge resolution.

[Problems to be Solved by the Invention] The present invention has been made to eliminate the drawbacks of the previously proposed devices described above, and its purpose is to improve the switching timing of the screening cycle. An object of the present invention is to provide an image processing device that improves the resolution of image edge portions.

Another object of the present invention is to provide an image processing device that can smoothly switch the screening period.

[Means for Solving the Problems] In order to achieve the above-mentioned problems, the image processing apparatus of the embodiment shown in FIGS. an identification circuit 13 that recognizes the image tone for each pixel by detecting whether or not the
A synchronization circuit F0( 1st
(see Figure (b)), a timing signal generation circuit 7 that generates a screen clock signal 12 of a corresponding period according to the value of the synchronized 5ELECT signal 71, and a pattern pulse that generates a pattern pulse signal 42 according to the screen clock signal 12. a generating circuit 3; and a comparator 4 that compares the levels of the pattern pulse signal 42 and the multivalued image signal 43 and outputs a pulse width modulated binary image signal 45.
Equipped with.

[Operation] FIG. 4 is an operation timing chart of FIGS. 1(a) and (b). In FIG. 4, 5ELEC of the identification circuit 13
The T signal 19 changes by detecting a change in image tone (edge portion, non-edge portion) of the input image signal 16b for each pixel. Furthermore, said 5
The ELECT signal 19 is input to a synchronization circuit 70 and is synchronized with the screen clock signal 12 currently being applied (
point a, point 0 in FIG. 4), the synchronous 5ELECT signal 71 is obtained. This causes the timing signal generation circuit 7 to output the synchronous 5EL.
The screen clock signal 12 changes every time the ECT signal 71 changes.
change the period of Therefore, the pattern pulse signal 42 is always switched so that it is newly generated in synchronization with the end of the previous cycle, so the delay time t2 as shown in FIG. 9 described above does not occur, and the resolution of the image edge portion is improved. do.

[Examples] Examples of the present invention will be described in detail below with reference to the accompanying drawings.

<Configuration of First Embodiment> FIGS. 1(a) and 1(b) are block configuration diagrams of an image processing apparatus according to a first embodiment. In the figure, 1 is a video data output unit which A/D converts image data from a CCD sensor or video camera (not shown), and outputs digital image data 1 of predetermined bits (6 bits in this example) having density information.
Output a. This digital image data 1a may be temporarily stored in a memory (not shown), or may be input from an external device through communication or the like. The image data 1a from the digital data output section 1 is 6-bit image data as shown in the figure, and is input to the buffer memory 11 at the next stage. The buffer memory 11 is used by the identification circuit 13 to extract desired pixels from image data for image tone identification. The identification circuit 13 identifies the image tone (characteristics or properties of an image) for each pixel, and outputs a 5ELECT signal 19 corresponding to the image tone. The 5ELECT signal 19 is input to the synchronization circuit F0, and the synchronous 5ELECT signal 19 is synchronized with the screen clock signal 12 that is being applied at the time.
The signal becomes 71. The synchronous 5ELECT signal 71 is input to the timing signal generation circuit 7 and changes the period of the screen black signal 12. The screen clock signal 12 is input to the pattern pulse generation circuit 3 to form a pattern pulse signal 42. The comparator 4 compares the levels of the pattern pulse signal 42 and the multivalued image signal 43 converted into analog by the D/A converter 2 via the delay circuit 14, and outputs a pulse width modulated binary image signal (PWM) 45. Form.

In this way, the period of the screen clock signal 12 is changed according to the image tone, and the coarse density of the "screen" applied to the multivalued image signal 43 is changed.

<Image tone recognition> The output signal from the buffer memory 11 enters the next stage identification circuit 13 shown in FIG. 1(a). The function of this identification circuit 13 is shown in FIG. 3(a), and is image tone recognition for detecting edges of an image by an aplactan filter operation. This L
The hardware circuit of the APLACian filter is shown in FIGS. 3(b) and 3(c). That is, the image signals 16a, 16b, 16c of each line arranged in order in the sub-scanning direction are transmitted through delay circuits 20a to 20d corresponding to one pixel clock to five taps 1.
It is output from 7a to 17e. The non-on matrix elements of the filter shown in FIG. 3(a) correspond to each tap. The output of each tap, that is, the part (17a) corresponding to the coefficient "-1" in FIG. , 17b, 17d
, 17e) are all added by the adder 52. Further, the coefficient "4" portion (17c) is multiplied by 4 by the multiplier 50. Both are then subtracted by an adder 18''C to obtain the desired Laplacian output 18a.
The cian output 18a is the amount of edges in the image, that is, the amount of edges in the image.
This edge amount is compared with the reference data 22 by the comparator 21, and the 5E
LEGT signal 19 is obtained. At this time, the 5ELECT signal 19, which is the output of the identification circuit 13, becomes a binarized output that is: When the edge amount of the image>k, the output is "1", and when the edge amount of the image ≤k, the output is "0". However, the parameter "k" at this time can be determined as appropriate using the reference data 22. In this way, the identification circuit 13 recognizes the image tone of the area constituted by the eight image data around the image data of the tap 17c, and converts the recognition result into 5ELEfl.
: This is output as the T signal 19. Of course, if there is a stage of image tone recognition, if it is detailed, for example, "parameters"
If k ” is taken as multiple values, the output is 5ELEC
By making the T signal 19 also several bits long, more detailed image tone recognition can be achieved.

<Pattern pulse selection timing generation> 5ELECT
The signal 19 is input to a synchronous circuit 70, from which a synchronous 5ELECT signal 71 is obtained. Here, the synchronous circuit 70
I will explain about it. FIG. 1(b) is an example of the synchronous circuit 70. For example, it is composed of a D type flip-flop 75, whose D input is a 5ELECT signal 19, its clock input is a screen clock signal 12, and its Q output is a synchronous 5EL signal.
This is the ECT signal 71. Therefore, 5
The change in the ELECT signal 19 is synchronized with the end of one cycle of the screen clock signal 12 currently being applied. As a result, the pattern pulse signal 42 is switched at the end of the period at which it is in use, so that
The delay time t2 as shown in the figure does not occur, and the resolution of the image edge portion is improved.

<Pulse for screen> Synchronous 5ELECT signal 71 is the timing signal generation circuit 7
An image clock 15 and a screen clock signal 12 are obtained from the timing signal generation circuit 7. The timing signal generation circuit 7 will now be described in detail. FIG. 2 is a block diagram of an example of the timing signal generation circuit 7. As shown in FIG. Inputs are a master clock 40, a synchronization 5 ELECT signal 71 and a horizontal synchronization signal 41, and outputs are a pixel clock 15 and a screen clock signal 12. Note that the horizontal synchronization signal 41 may be generated internally or may be provided externally. Furthermore, since this embodiment is applied to a laser beam printer, the horizontal synchronization signal 41
corresponds to the well-known beam detect (BD) signal. The timing signal generation circuit 7 divides the frequency of the master clock signal 40 using counters 91 and 92, respectively. Counter 91 forms pixel clock signal 15 and is also selected as screen clock signal 12. The degree of cycle reduction by the counter 91 is determined depending on the degree to which fluctuations occurring in each line of the screen clock signal 12 are to be suppressed, as will be described later, and is 1/4 in this embodiment. That is, one pixel clock signal 15 is generated for four master clock signals 40.
5 is used for image data transfer lock and D/A converter 2 latch timing. The counter 92 forms a clock signal 101 corresponding to the pixel clock signal 15 further divided by three. Selector 95 is synchronous 5ELEC
According to the T signal 71, the output of either the counter 91 or 92 is selected. When the synchronous 5 ELECT signal 71 recognizes an edge portion, the output of the counter 91 is selected, and when the non-edge portion is recognized, the output of the counter 92 is selected to form the screen clock signal 12. The screen clock signal 12 is also a clock signal for synchronizing the next cycle change. That is, the end of the currently applied screen clock signal 12 determines the next synchronization timing. Further, the counters 91 and 92 are both reset by the H5YNC signal 41 in order to synchronize each line. The counter 92 also indicates that the synchronous 5ELECT signal 71 is a logic "1".
It has been reset for a while. Therefore, since the counter 92 is reset until just before it is used, the next time it is used, it becomes possible to form the full pattern pulse signal 42 starting from the beginning at the same time as selection. This can be done in the same way even if a pattern pulse signal of another period is provided, by resetting it until just before. Furthermore, in the embodiment, the pixel clock signal 15 is obtained from the counter 91, but if, for example, a separate counter with the same frequency division ratio as the counter 91 is provided and the pixel clock signal 15 is obtained from there, the counter 91 can also be used. The full pattern pulse signal 42 can be reset to immediately before it is selected, and the next time it is used, a full pattern pulse signal 42 can be generated that starts from the beginning at the same time as the selection. Therefore, the screening control of switching the screening period at the end of one period of the pattern pulse signal that has been applied up to that point can be more thorough.

The synchronous 5ELECT signal 71 takes a logic "1" value for the image edge portion. Therefore screen clock signal 1
2 is selected as follows: edge portion of the image → pixel clock signal 15 non-edge portion of the image → clock signal 101. The screen clock signal 12 is converted by the pattern pulse generation circuit 3 into a pattern pulse 42 having a predetermined shape. In this embodiment, it is a triangular wave. This pattern pulse is input to a comparator 4 for binarizing image data by PWM (pulse width modulation).

<Second Embodiment> FIG. 5 is a block diagram of an image processing apparatus according to a second embodiment. Components that are equivalent to those in FIG. 1(a) are given the same reference numerals and their explanations will be omitted. The image processing apparatus shown in FIG.
3, and a pattern pulse generating means 90 that generates, for example, two systems of pattern pulse signals 42a and 42b with different periods.
and 3a.

3b, and a pattern pulse signal 42a of the specific period,
Screening processing means 4a and 4b perform screening processing on the multivalued image signal 43 for each 42b and output pulse width modulated binary image signals 45a and 45b, and screen processing means 4a and 4b output binary image signals 45a and 45b which are pulse width modulated by performing screening processing on the multivalued image signal 43, and binary image signals of different systems based on the recognized image tone. Image signals 45a, 45
a synchronization circuit 70 and a selector 72 that selectively apply b to switch the actual screening period and switch the screening period at the end of one period of the screen clock signal 61 that was applied at the time of the recognized image tone change; Equipped with.

<Timing Generation Circuit> FIG. 6 is a circuit diagram of the timing signal generation circuit, and FIG. 7 is an operation timing chart of the configuration shown in FIG. 5. In FIG. 6, a timing signal generation circuit 90 divides the master clock signal 40 by counters 91 and 92, respectively. Counter 91 forms a screen clock signal 12a, which corresponds to the pixel clock. The counter 92 forms a screen clock signal 12b corresponding to the pixel clock divided by three. The clock signal 12a.

12b is manually input to the pattern pulse generating circuits 3a, 3b and the selector 80, respectively. The selector 80 selects the screen clock signals 12a, 1 according to the T signal 71 at the synchronization 5ELE.
Select one of 2b. When the synchronization 5 ELECT signal 71 recognizes an edge portion, the screen clock signal 12a is selected, and when the non-edge portion is recognized, the screen clock signal 12b is selected to form the clock signal 61 for the next synchronization. do. That is, the currently applied screen clock signal determines the next synchronization timing.

Further, the counters 91 and 92 are both reset by the H5YNC signal 41 in order to synchronize each line.

Further, the counter 92 is reset while the synchronous 5ELECT signal 71 is at logic "1".Therefore, since the counter 92 is reset until just before it is used, the next time it is used, a full pattern pulse signal is sent at the same time as the selection. This can be done in the same way even if pattern pulse signals of other periods are provided.Such screening control is no longer a concept of switching between multiple systems of periodic pattern pulse signals, but rather - The concept is to select individual pattern pulse signals and connect them one, two or three if necessary.In this way, the selection of pattern pulse signals and their continuity can be easily achieved.

<Screen processing> In FIG. 7, pattern pulse signal 42a.

According to the synchronized 5ELECT signal 71, one of the signals 42b has the meaning of pulse width modulation, and the others have no meaning. Although the pattern pulse signal 42a of the embodiment is actually generated all the time, the diagram emphasizes whether it has the meaning of pulse width modulation or not. Therefore, the binarized image signal is formed with meaning only for the pattern pulse signal generated in the figure. Synchronous 5ELE[;T signal 71
selects and outputs the generated binary image signals 45a and 45b via the selector 72, and outputs a continuous screened image signal 45 as a whole. Therefore, in particular, since the screen clock period is switched from fine to coarse in synchronization with the end of one fine period, the resolution at the time of screen clock switching is improved.

Incidentally, in the screening processing of the above embodiment, the fine image was constructed using the pixel clock 15 (or 12a), and the coarse image was constructed using the clock signal 51 (or 12b) with a 3-pixel period, but this is just an example, and both If you choose a period with a difference between them, the original purpose will be met. Furthermore, it is obvious that it is within the scope of the present invention to have not only two types of screen cycles but several types that can be switched, and to switch the screen clock in synchronization with the screen cycle at the time of switching.

[Effects of the Invention] As explained above, according to the present invention, the 5ELECT signal 1
By simply synchronizing the change of 9 with the currently selectively applied screen clock signal, the shift in pattern clock signal switching at the edge portion of the image is reduced, and the resolution of the edge portion is improved.

Further, according to the present invention, one single pattern pulse signal,
If necessary, two or three can be selected and connected, making it easy and smooth to switch the screening cycle.

[Brief explanation of drawings]

1(a) and 1(b) are block diagrams of the image processing apparatus of the first embodiment, FIG. 2 is a block diagram of an example of the timing signal generation circuit 7, and FIG. 3(a) is the concept of a Laplacian filter. Figures 3(b) and 3(C) are block configuration diagrams of an example of realizing a Laplacian filter, Figure 4 is an operation timing chart of the configuration of Figures 1(a) and (b), and Figure 5 is a block diagram of an example of realizing a Laplacian filter. A block configuration diagram of the image processing device of the second embodiment, FIG. 6 is a circuit diagram 1 of the timing signal generation circuit, FIG. 7 is an operation timing chart of the configuration shown in FIG. 5, and FIG. 8 is a block configuration of the already proposed device. FIG. 9 is an operation timing chart of the configuration shown in FIG. In the figure, 1... Video data output unit, 2... D/A converter, 3, 3a, 3b... Pattern pulse signal generator, 4, 4a, 4b... Comparator, 5... horizontal synchronization signal generation circuit, 6... master clock oscillator, 7.
90... Timing signal generation circuit, 11... Buffer memory, 12... Screen clock signal, 13.
...Identification circuit, 19...-5ELECT signal, 14...
・Delay circuit, 15... Pixel clock signal, 40...
Master clock signal, 43...analog image data,
44...Digital image data, 45...PWM signal, 51...5ELECT signal synchronization clock, 70...
... Synchronous circuit, 71 ... Period 5 ELECT signal, 72
. . . PWM signal selector, 80 . . . synchronous clock selector. (Knee I:), -', -phase

Claims (2)

[Claims] (1) Image tone recognition that recognizes the tone of the multi-value image signal for each pixel in an image processing device that processes a multi-value image signal into a screen using a pattern pulse signal having multiple cycles and forms an image based on the screening process. and a period switching means for switching the screening period by selectively applying pattern pulse signals of different periods based on the recognized image tone, and screening at the end of one period of the pattern pulse signal that has been applied so far. An image processing device characterized by comprising a device that switches a cycle. (2) Image tone recognition that recognizes the tone of the multi-value image signal for each pixel in an image processing device that processes a multi-value image signal into a screen using a pattern pulse signal having multiple cycles and forms an image based on this screen. means, a plurality of pattern pulse generation means for generating pattern pulse signals of different periods in synchronization with the end of one period of the pattern pulse signal applied so far, a plurality of screening processing means for performing screening processing on a value image signal and outputting a pulse width modulated binary image signal, and one period of a pattern pulse signal that has been applied so far based on the recognized image tone. An image processing apparatus comprising: a signal selection means for selectively outputting one of the binary image signals in synchronization with the end of the image processing apparatus.