JPS6250978A - Image processing device - Google Patents

Abstract

PURPOSE:To obtain a high fidelity output regardless of an original image tone by binarizing an original picture signal with respect to an image on an edge part and the smoothed picture signal with respect to the image on the part except for the edge part. CONSTITUTION:A digital image 1a is inputted from a video data output part 1 to a smoothing circuit 8b, a selector 9 and an identifying circuit 13 through a buffer memory 11. The circuit 8b smoothes the picture signal and inputs the smoothed picture signal 50 to the selector 9. On the other hand, the memory 11 and the circuit 13, both of which compose an edge detecting part, judge the signal 1a to correspond to the edge part, and then the circuit 13 gives a SELECT signal to the selector 9. When the signal 1a is judged to correspond to the edge part, the selector 9 directly outputs the digital picture signal to a binarizing part which consists of a D/A converter 2, a comparator 4, etc When the signal 1a is judged to correspond to the edge part by the edge detecting part, a signal 50 is outputted to the binarizing part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that processes and binarizes input image signals.

[Prior Art] Conventionally, as a method of binarizing an image including halftones, for example, a dither method and a density pattern method using a threshold matrix are well known. However, especially when the halftone dot image is converted into 2-1 by these methods, moiré fringes are generated due to beats in the periodic structure of the halftone dots and the threshold value matrix, and the image quality is significantly deteriorated.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and its purpose is to obtain a high-quality reproduced image output, and a further purpose is to obtain, for example, a halftone image. An object of the present invention is to propose an image processing device that faithfully reproduces an image of a document containing one or more of nine character images, halftone images, etc.

[Means for Solving the Problems] In order to achieve the above-mentioned problems, the image processing apparatus shown in FIG. (buffer memory 11 and identification circuit 13), digital image signal 1a
A smoothing circuit 8b smoothes the image signal 50 and outputs a smoothed image signal 50, and when the identification circuit 13 determines that the image corresponds to an edge portion, binarizes the digital image signal (la or 8a), It has a binarization processing unit 51 that binarizes the smoothed image signal 50 when it is determined that the smoothed image signal 50 corresponds to a part other than an edge part.

[Operation] Under the above configuration, the original image signal is binarized as it is for edge portion images or halftone images, so its sharpness is not lost, and for images other than edge portions, the smoothed image signal is used. 2
By converting into values, the periodicity of halftone dots is removed, so moiré and the like will not occur.

[Examples] Examples of the present invention will be described in more detail below with reference to the accompanying drawings.

(Configuration of Embodiment) Figure 1 shows a schematic diagram of an image processing apparatus in this embodiment. It performs A/D conversion and outputs digital image data la of predetermined bits (6 bits in this example) having density information.This digital image data la may be stored in -H memory (not shown). The image data la from the digital data output unit 1, which may also be input from an external device through communication or the like, is 6-bit image data as shown in the figure, and is input to the buffer memory 11 at the first stage. As shown in FIG. 2, the buffer memory 11 is composed of four line memories lla to lid, one line of the input image data 1a is selected by a selector 15a, and is written to the selected line memory. on the other hand,
Image signals that have already been written are read out by the selector 15b from the line memory to which writing has not been performed and are output as one image signal 16a, 16b, 16c. or,
Writing to such line memory is lla, llb, ll
c, lid, and finally output image signals 16a to 16a.
16c outputs three consecutive lines of image data, and by preparing four line memories, writing and reading can be performed simultaneously.

Outputs from such line memories (16a, 16b, 16
c) is input to the subsequent smoothing circuit 8b, while a part of the original signal (image data 8a of the center pixel) in the line memory is also taken out and input to the selector 9. The other input of the selector 9 is the output of the smoothing circuit 8b, and the selection signal of the selector 9 is the 5ELEC obtained from the identification circuit 13.
This is the T signal 28. The operation of the identification circuit 13 will be described later.

The output signal 10 from the selector 9 is converted into an analog quantity by a digital-to-analog converter (CD/A converter) 2, and each picture element is sequentially input to one terminal of a comparison circuit (comparator) 4. Ru. On the other hand, the pattern signal generator 3 generates a triangular wave pattern signal 2 at a frequency of once for every predetermined number of picture elements (pixels) of the digital data, and inputs it to the other terminal of the comparator 4.

The master clock 52 from the oscillator (master clock generation circuit) 6 is generated by the timing signal generation circuit 7 in synchronization with the water motion synchronization signal 55 generated for each line from the horizontal synchronization signal (H5YNC) generation circuit 5. It is counted down to one cycle and becomes the pixel clock 11, which is used for locking the transfer of image data and latch timing of the D/A converter 2. Note that the horizontal synchronizing signal may be generated internally or may be given externally, and since this embodiment is applied to a laser beam printer, the horizontal synchronizing signal may be a well-known signal. beam dichik)
(BD) signal.

(Binarization processing by PWM) The comparator 4 compares the analog-converted image signal 53 and the level of the triangular wave pattern signal 12, and outputs a pulse width modulated PWM signal output 39. Then, this PWM signal output 39 is input to a modulation circuit (for example, the laser driver 32 in FIG. 7) for modulating the laser beam.The laser beam is then turned on/off according to the pulse width, and the recording medium (also the photosensitive drum 38) is inputted. A halftone image is formed thereon.

FIG. 5 is a diagram for explaining signal waveforms of each part of the apparatus shown in FIG. 1. Explaining with reference to FIG. 5, the master clock 52 is the output of the oscillator 6, and is the horizontal synchronization signal described above as the BD double signal.

Further, the pixel clock 11 is obtained by counting down the master clock 52 of the oscillator 6 by the timing signal generation circuit 7. That is, the pixel clock 11 is synchronized with the horizontal synchronization signal by the timing signal generation circuit 7, and is a signal obtained by counting down the master clock 52 to one-quarter period. The screen clock 54 is a signal that is synchronized with the BD double signal within the timing signal generation circuit 7, and the pixel clock 11 obtained by the timing signal generation circuit 7 is further processed in the timing signal generation circuit 7 so that it has one-third period. The screen clock 54 is obtained by counting down to , that is, has a period of once every three pixel clocks 11 , and is a synchronizing signal for generating the triangular wave pattern signal 12 . is input. Further, the digital data 10 is digital image data (code data), and the image signal output from the video data output section 1 can be an original image signal or Either the image signal after smoothing is selected.

The analog video signal 53 is converted into D by the D/A converter 2.
/A converted image data, and as shown in the figure, each pixel data at an analog level is output in synchronization with the pixel clock 11.

As shown in the figure, it is assumed that the higher the analog level is, the higher the concentration becomes.

On the other hand, the triangular wave 12 which is the output of the pattern signal generator 3 is generated in synchronization with the screen clock 54 and is input to the comparator 4, as shown by the solid line "input to comparator" in FIG. The broken line in the figure is the image data converted into analog by the D/A 2, which is compared with the triangular wave 12 from the pattern signal generator 3 by the comparator 4, and as shown in the PWM output signal 39, the image data is pulse width modulated. The result is binarized data.

In this way, the binarization process in this embodiment enables almost continuous pulse width modulation by converting digital image data into -H analog image data and then comparing it with the triangular wave pulse 12 of a predetermined period. It is possible to obtain a sharp image output.

Further, according to this embodiment, the screen clock is synchronized with the horizontal synchronizing signal 55 using the master clock 52 having a higher frequency (for example, 12 times the frequency of the triangular wave) than the frequency of the synchronizing signal for generating a pattern signal (for example, a triangular wave). 54, the pattern signal (triangular wave) 12 generated from the pattern signal generation circuit 3 has fluctuations (for example, l
In this embodiment, the deviation between the pattern signals on the first line and the second line is 1/12 of the pattern signal period. Therefore, since the gradation information is pulse-width modulated almost steplessly using a pattern signal with little fluctuation, a high-quality reproduced image can be obtained.

If the D/A converter 2 has a 6-bit input, the pulse width modulated video output generated in the above manner will be 6 bits.
Since 4 levels of analog output are obtained, 64 levels of pulse width modulation output are obtained.

<Picture tone identification> Next, details of the identification circuit 13 will be described. Figure 3(a)
, (b) shows a filter used in the identification circuit.As shown in the figure, a temporary differential filter is used.As is well known, the temporary differential filter has directionality, and is used to detect the first-order differential amount in the two-dimensional direction. In this case, it is necessary to combine the two filters shown in (a) and (b) of the figure. The physical nature of such identification circuit 13 is to detect edge portions of the image.

Figure m4 (a) is a partial block diagram for performing such a filter operation in hardware, and this block is an output signal 16a from the selector 15b.

16b, 16cI: 1 pixel clock delay circuit 20a-2
Using 0f, taps 17a to 17C218a to 18C119 corresponding to each element of the 3X3 matrix
FIGS. 4(b) to (d) with a configuration having aN19C
The circuit shown in FIG.
8. This shows the configuration for obtaining 8. Figure 4 (b
) performs a matrix operation corresponding to FIG. 3(a), and that of FIG. 4(C) performs a matrix operation corresponding to FIG. 3(b).
a and 22b are adders, which add the signals in consideration of the sign. 2
3a and 23b are the outputs of the respective matrix calculations and are absolute value circuits (ABS) 24a and 2 shown in FIG. 4(d).
4b and added by an adder 25. The resulting data is compared with reference data 27 as a digital signal in a comparator 26 to obtain an output of I when X>D and O when X≦D. However, X is the data of the calculation result, and D is the reference data. 5 select signal 28 is "1"
”, the sum of the differential values is large, so it is considered that the image is an edge portion image.

Smoothing process Next, the processing of the smoothing circuit 8b will be explained.

In the smoothing circuit 8b, the outputs of all the taps shown in FIG. 4(a) are added and averaged. That is, X = (1/9
) Find the average output X that is ΣXi. Here XI is the nine tap output. FIG. 6 shows the circuit diagram.

The adder 40 adds the taps 18a to 18c, and the adder 4
1, the sum of the output of the adder 40, the tap 29a (the output of the adder 21a in FIG. 4(b)), and the tap 29b (the output of the adder 21b in FIG. 4(b)) is calculated, and the sum is added to the division ROM 42.
In this case, an average value output of 50 is obtained.

Characteristics of Spatial Filter> The frequency characteristics of the above two spatial filters (-th order differential filter and smoothing filter) are as follows.

(2): The first-order differential filter is configured so that the frequency at its peak position is lower than the spatial frequency of the halftone dots, and is set so as not to spread the halftone dots, thereby detecting edge portions of characters and the like. This filter is used for image tone recognition.

■: Smoothing filter passes low frequencies (low-pass filter). Used for averaging image signals.

The characteristics of the above two filters are shown in FIG. As can be seen from the frequency characteristics in Figure 8, the bandpass filter (-
It is considered that the magnitude relationship between the total number of signals passing through the second-order differential filter and a predetermined number represents the image tone.

FIG. 9 shows the spatial frequency spectra of various originals. In general, halftone dot originals have periodic sharp peaks relative to the halftone dot pitch.

Image processing according to image tone recognition) To summarize what has been explained above, the image processing in this embodiment is as follows: ■ The peak frequency of the −th order differential filter (for image tone recognition) is set so as not to widen the halftone dots. The output of such a filter determines the tone of the image, or in other words, determines the edge portions of characters and the like.

■ Region where the output of the -order differential filter is small (select
If the signal 28 is "0" (ie, halftone or halftone area), it is passed through a smoothing filter.

■ Region where the output of the -order differential filter is small (select
When the signal 28 is "1" (ie, for a character image area, etc.), the original signal 8a is output.

It goes without saying that the image processing method described above is compatible with the image processing apparatus shown in FIG. 1, and the following results are obtained by processing zero or more.

■ The halftone image is smoothed. That is, the periodicity of the halftone dots is removed.

■ Text and line drawings are reproduced without smoothing the edges, that is, without losing sharpness.

■ Smoothing and enhancement are performed on photographic images depending on the presence or absence of edges. Therefore, the midtone portion of the photograph does not lose its naturalness.

The result of the above image tone determination and filter processing becomes the output 10 from the selector 9 in FIG. Even if the smoothed signal is pulse width modulated as described above, moiré fringes no longer occur.The reason is that the image signal of the document no longer has halftone dots due to the smoothing, and even if line screen output is performed, the screen pulse 5
This is because a beat with a period of 4 does not occur.

FIG. 7 shows an example in which the signal processing result of the present invention is applied to a laser beam printer. The aforementioned PWM output signal 39 modulates the laser driver 32, and pulse width modulates the semiconductor laser 33 to cause it to emit light. The emitted light beam of the semiconductor laser 33 is collimated by a collimator lens 34, optically deflected by a rotating polygon mirror 36, and scanned on a photosensitive drum 38 by an fθ lens 37. The light image formed on the photosensitive drum forms an electrostatic latent image, and the image is output using a normal copying machine process.

<Effects of the Embodiment> As described above, in this embodiment, high image quality can be output regardless of the quality of the original.

Furthermore, since a 64-level pulse width modulation output is performed, the effects of the discrimination and smoothing filters are fully reflected. Therefore, hardware can be implemented with a relatively small matrix size.

Although the above embodiment has been described using an example of an image processing apparatus that performs binarization processing using PWM modulation, it goes without saying that it is also applicable to binarization processing using conventional dithering methods or the like.

Furthermore, although the embodiment has been shown with a 3x3 matrix, this may be applied to larger matrix sizes, such as 5x5.7.
X7 can also be used, and the output pattern from the pattern signal generating circuit 3 is not limited to a triangular wave, but may be a sine wave, a sawtooth wave, or the like.

[Effects of the Invention] As explained above, according to the present invention, high-quality reproduced images can be obtained even when images with various tones are reproduced, such as halftone images, single character images, halftone images, etc. It is possible to faithfully reproduce a manuscript containing one or more of the following.

[Brief explanation of drawings]

Figure 1 is a diagram showing the basic configuration of the embodiment, Figure 2 is a diagram showing the configuration of the buffer memory, and Figure 3 (a).
, (b) are matrix configuration diagrams of the -dimensional differential filter, FIGS. 4(a) to (d) are block circuit diagrams configuring the identification circuit, and FIG. 5 is a timing chart explaining the operation of pulse width modulation. FIG. 6 is a block circuit diagram of a smoothing circuit, FIG. 7 is a diagram illustrating the output of a binary image using a laser beam printer as an example, and FIG. 8 is a frequency characteristic diagram of each spatial filter. Fig. 9 shows the section frequency characteristics of various images.
3... Pattern signal generator, 4, 26... Comparator, 5... Horizontal synchronization signal generation circuit, 6... Oscillator, 7... Timing signal generation circuit, 8b... Smoothing circuit , 9.15a, 15b・-Selector, 11・
... Buffer memory, lla to 1lcl... Line memory, 13... Identification circuit, 20a to 20f... One pixel delay circuit, 21a to 21d, 22a, 22b, 25
, 40 , 41 ... adder, 24 a , 24
b - Absolute value circuit, 42... Division ROM, 32.
...Laser driver, 33...Semiconductor laser, 34.
...Collimator. Lens, 36... Rotating polygon mirror, 37... fθ lens, 38... Photosensitive drum, 50... Smoothed image data, 51... Binarization processing section, 52... Master clock, 53...Analog image data, 54...Screen clock, 55...BD double signal. Figure 2 35F! (0) Figure 3 (b) Figure 4 (a) Figure 4 (b) Figure 5

Claims (3)

[Claims] (1) An image processing device that binarizes an input digital image signal, including an edge detection unit that detects whether the digital image signal input to the image processing device corresponds to an edge portion of an image; A smoothing processing unit smoothes the signal and outputs a smoothed image signal, and when the edge detection unit determines that the digital image signal corresponds to an edge portion, binarizes the digital image signal and outputs a smoothed image signal other than the edge portion. and a binarization processing unit that binarizes the smoothed image signal when it is determined that the smoothed image signal corresponds to the smoothed image signal. (2) The image processing apparatus according to claim 1, wherein the binarization process is performed by pulse width modulation based on a comparison between a pulse pattern of a predetermined period and an image signal. (3) The image processing device according to claim 2, wherein the pulse pattern is a triangular wave.