JPS62101177A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain reproduced pictures having high quality by comparing synthesized picture element data outputted from a synthesizing means with a selected pulse pattern to output a pulse width modulated picture element signal. CONSTITUTION:Three-picture element components of digital picture element data outputted from an output device 1 are synthesized by addition in an adding circuit 4, and the output is inputted to a comparing circuit 7 through a D/A converting circuit 5 and an amplifying circuit 6. A picture clock is obtained from the reference clock from a reference clock generator 15 by a counter 16, and this clock is inputted to a ternary counter 17 to generate a pulse pattern synchronizing clock, and one of terminals A, B, and C of a selector circuit 19 is selected to input this clock to one of pulse pattern generating circuits 8-10 through gate circuits 20-22. Three kinds of pulse pattern synchronized with three picture elements are generated selectively from generating circuits 8, 9, and 10 and are amplified by amplifying circuits 11, 12, and 13 and are inputted to the comparing circuit 7 through a mixing circuit 14 to subject three- picture element components of picture information to pulse width modulation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing device for obtaining high-quality reproduced images.

[Prior art]

Conventionally, it has been considered to reproduce halftone images using a dither method or a density pattern method. but.

In either case, sufficient gradation cannot be obtained with a small-sized threshold matrix, and a large-sized threshold matrix must be used.As a result, the resolution decreases and the texture structure due to the periodic structure of the matrix becomes noticeable. Unable to obtain high quality output.

In order to eliminate the above-mentioned drawbacks, in the dither method, a method of multi-valued dot information using a plurality of dither matrices is also considered. However, in such a method, a complicated circuit configuration is required to synchronize each dither matrix, and the system inevitably becomes large and complicated.

Therefore, there is a limit to multi-leveling using a plurality of dither matrices.

There is also a problem in that when a desired γ correction is applied to a digital input image signal, the number of gradations decreases. For this purpose, it is possible to increase the number of bits of the input image signal to widen the input image signal's dynamic range in advance, but as the amount of information in the input image signal increases, not only does the number of signal lines increase, but also the memory Or when processing
There is a problem that the device configuration becomes complicated and expensive.

〔the purpose〕

The present invention has been made in view of the above points, and an object of the present invention is to provide an image processing device that can obtain high-quality reproduced images.

Another object of the present invention is to provide an image processing device that can obtain excellent halftone images with a simple configuration.

A further object of the present invention is to provide an image processing device that can perform excellent gradation reproduction with a relatively small amount of information.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a circuit diagram of the image processing device in this embodiment. In the figure, 1 is a digital data output device that A/D converts image data from a COD sensor or video camera (not shown). , outputs predetermined bits of digital data with gradation information. This digital data may be temporarily stored in memory, or may be input from an external device via communication, etc. This digital data output device outputs one line of picture element data (pixel data) in a continuous form. The first pixel data is first latched by the first latch circuit 2, and then latched by the second latch circuit 3 at the next image clock. The data latched by the first latch circuit 2 and the second latch circuit 3 and the following picture elements (pixels), that is, three consecutive picture elements, are added and synthesized by the adder circuit 4.

In this embodiment, the digital image data outputted from the digital data output device 1 is a signal having 65 gradation levels, and is synthesized by adding 3 pixels in the adding circuit 4. The gradation number is 19393. The added and synthesized signals are converted into analog quantities by a digital-to-analog conversion circuit (D/A conversion circuit) 5, and after having their amplitude corrected by an amplifier circuit 6, they are input to one terminal of a comparison circuit 7. On the other hand, three types of pulse patterns synchronized with the three picture elements are selectively generated from the pulse pattern generation circuits 8, 9, and 10. The pulse patterns are each amplified by the amplifier circuits 11, 12, and 13, and then input to the other terminal of the comparator circuit 7 via the mixing circuit 14. The comparator circuit 7 compares the level of the repeatedly generated pulse pattern with the input image signal, pulse width modulates the image information for every three picture elements, and outputs it as binary data. This pulse width modulated image signal is then input to a modulation circuit for modulating a laser beam, for example. Then, the laser beam is turned on/off according to the pulse width to form a halftone image on a recording medium (not shown).

The pulse pattern generation circuit 8 generates a sinusoidal pulse pattern, the pulse pattern generation circuit 9 generates a triangular wave, and the pulse pattern generation circuit 10 generates an inverse sine wave pulse pattern.

On the other hand, in order to synchronize these operations, the reference clock from the reference clock generator 15 is counted down by a counter 16 to, for example, 1/8 cycle, and this pixel clock becomes an image clock (pixel clock) for transferring pixel data. is input to the ternary counter 17, and further 3
This is a pulse pattern synchronization clock for generating a pulse pattern that is counted down to 1/1 period. That is, the ternary counter 17 generates a synchronizing signal for every three picture elements in synchronization with the horizontal synchronizing signal generated for each line from the two horizontal synchronizing signal generating circuits 18.

Note that the horizontal synchronization signal may be generated internally or may be provided externally. Further, the horizontal synchronization signal corresponds to, for example, a well-known beam detect (BD) signal if the present apparatus is applied to a laser beam printer. In addition, terminals A, B, and C of the γ selector circuit 19
By selecting one of these, the pulse pattern synchronization clock from the ternary counter 17 is transmitted to the pulse pattern generation circuit 8°9.1 via the gate circuit 20°21.22.
0 will be input.

That is, if the terminal A of the γ-safe 2 circuit 19 is selected, the pulse pattern synchronization clock is input to the pulse pattern generation circuit 8 via the AND gate 20.

Similarly, if terminal B is selected, the pulse pattern synchronized clock is input to the pulse pattern generation circuit 9, and if terminal C is selected, the pulse pattern rfQM clock is input to the pulse pattern generation circuit 10. It is something that will be done.

Note that the terminals A, B, and C of the γ-safe 2 circuit 19 may be configured to be selected by an operator, or configured to be automatically selected by a control circuit such as a CPU according to the characteristics of the output device to be used. It's a good thing.

FIG. 2 is a diagram for explaining signal waveforms of each part of the apparatus shown in FIG. 1, and the operation of each part of the apparatus will be described below with reference to FIG. Figure 2 (a) shows the basic Glock generator 15.
FIG. 2(b) is the above-mentioned horizontal synchronization signal. Further, FIG. 2(C) shows a pixel clock generated from the counter 16 in synchronization with the horizontal synchronization signal. FIG. 2(d) shows a pulse pattern synchronization clock in which the pixel clock from the counter 16 is further divided into one-third periods by the ternary counter 17.

Further, FIG. 2(e) shows the analog level when the image signal from the digital data output device 1 is directly D/A converted, and as shown in the figure, the density increases as it goes downward.

In this embodiment, since addition and synthesis are performed every three picture elements, the analog image data output from the D/A conversion circuit 5 is shown in FIG.
It looks like the broken lines f) to (h). Figure 2(f)-(h
) The pulse patterns shown by solid lines are generated from the pulse pattern generating circuit 8.9.10, and in this embodiment, one of them is selected. Second
Figures (i) to (k) show output signals from the comparator circuit 7, and even if the same image signal is input to the comparator circuit 7, the binarized signal output by the selected pulse pattern generation circuit is This indicates that the characteristics of the data are different. That is, the pulse pattern generation circuit 8
When is selected, the characteristics of the output binarized data are as shown in Figure 2 (i)
Similarly, if the pulse pattern generating circuit 9 is selected, the result will be as shown in FIG. 2(j), and if the pulse pattern generating circuit 10 is selected, the result will be as shown in FIG. 2(k).

In this manner, in this embodiment, after adding and synthesizing digital image data for three pixels, this added data is converted into analog image data and compared with a selected pulse pattern of a predetermined period.

As a result, almost continuous pulse width modulation becomes possible, and a high-gradation image output can be obtained.

Further, according to this embodiment, since the pulse pattern synchronization clock synchronized with the horizontal synchronization signal is formed using a reference clock with a frequency higher than the frequency of the synchronization signal for pulse pattern generation, the pulse pattern generation circuit generates the pulse pattern synchronization clock. In this embodiment, the fluctuation of the pulse pattern (for example, the difference between the pulse patterns of the first line and the second line) is 1/24 of the pulse pattern period.

Therefore, since the gradation information is pulse width modulated almost steplessly using a pulse pattern with little fluctuation, a high-quality reproduced image can be obtained.

The relationship between the input image signal and the modulated pulse width, ie, the density, is shown in FIG. Figure 3(a) shows the characteristics when a sinusoidal pulse pattern is selected.
FIGS. 3(b) and 3(C) show the characteristics when triangular wave and inverse sine wave (FIG. 2(h)) pulse patterns are selected, respectively. Furthermore, if the amplifier circuits 11, 12, and 13 in FIG. 1 are made into adjustable nonlinear amplifier circuits, even finer selection of γ becomes possible.

In this way, this embodiment is configured so that the pulse pattern can be selected according to the characteristics of the output device used, so γ correction can be performed without reducing the number of gradations, achieving high-quality gradation reproduction. can do.

In this embodiment, the period of the pulse pattern is set to occur once every three picture element clocks, but the period may be greater or less than that.

Further, although the picture element data is additively synthesized every three picture elements, the number of picture elements to be additively synthesized may be determined as appropriate. This is determined by considering the response speed, resolution, etc. of the device.

Further, the pulse pattern generation period and the addition and synthesis period of picture element data may be configured to be different from each other.

Furthermore, in this embodiment, synchronization of pulse patterns is performed at the same timing on all lines, but it is also preferable to shift the synchronization signal for pulse pattern generation by, for example, one pixel for each line. . By doing this, the center position of the pulse width growth shifts for each line, and the output pattern seen from a macroscopic perspective becomes a diagonally arranged halftone dot-like pattern that looks natural to the eye. Furthermore, the growth center of the pulse width is equalized in the output screen, which is preferable from the viewpoint of resolution reproduction.Also, the pulse pattern can be selected partially or differently for each line instead of the entire screen. Also good.

〔effect〕

As described above, according to the present invention, it is possible to reproduce grayscale information with high gradation without deteriorating resolution.

Further, according to the present invention, high-quality reproduced images can be obtained with a simple configuration.

Incidentally, the present invention is applicable to all image processing apparatuses such as facsimile machines and laser beam printers.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram for explaining the image processing device in this embodiment, Fig. 2 is a diagram showing waveforms of various parts of the circuit shown in Fig. 1, and Fig. 3 is output binarized data in this embodiment. FIG. 2 is a diagram for explaining the conversion characteristics of . In the figure, 1 is a digital data output device, 2.3 is a latch circuit, 4 is an addition circuit, a D/A conversion circuit, 6, 11,
12.13 is an amplifier circuit, 8°9, 1O is a pulse pattern generation circuit, 14 is a mixing circuit, 15 is a basic clock generator, 16.17 is a counter, 19 is a selector circuit, 20.21.22 is an AND gate. . Patent applicant: Canon Co., Ltd.

Claims (1)

[Claims] pixel data output means for outputting pixel data; synthesis means for synthesizing a plurality of pixel data output from the pixel data output means; pulse pattern generation means for generating plural types of pulse patterns with predetermined periods; a selection means for selecting a pulse pattern to be used from among the types of pulse patterns, and a pixel signal pulse width modulated by comparing the synthesized pixel data output from the synthesis means and the selected pulse pattern. An image processing device characterized in that it is configured to output.