JPS62206965A - Image processing device - Google Patents

Abstract

PURPOSE:To obtain the output of a high picture quality even when a memory capacity and the data capacity at the time of communication are small by converting to the multi-value data of the prescribed number of the bit with a multi-value circuit after the input image data of the prescribed bit are binarized, stored into a memory and transferred through a communicating line. CONSTITUTION:The data of one picture element 8 bits outputted from a digital data output device 1 are half-tone-processed by using an organizational dither method or an average error minimum method at a binarization processing circuit 2, converted to the binary data of one picture element one bit, and thereafter, stored into a memory device 3. The binary data outputted from the memory device 3 are inputted to a multi-value circuit 4, converted to the multi-value data of the one picture element 8 bits again and transferred to a PWM circuit 5. At the PWM circuit 5, a pulse width modulating processing is executed to the inputted picture element data of 8 bits and the data are outputted as a pulse width modulating signal (PWM signal) to a terminal 39. The numeric value on respective lines displays the number of the bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing device that processes multivalued image data and converts it into a pulse width modulation signal.

[Prior art]

Conventionally, digital printers (binary printers) output only two values based on on/off dots, so for example, C
Input image data from an input system such as a CD (approximately 8 bits)
The gradation of the original image was expressed using a matrix of multiple pixels, which was then binarized using a dithering method. However, the dither method has the disadvantage that resolution deteriorates when trying to improve the gradation. For example, to express 17 Wi tones including white, a 4 x 4 pixel threshold matrix is required, and 65
An 8×8 pixel threshold matrix is required to express gradations, but since the output image is expressed in units of threshold matrices, the resolution of halftones deteriorates as the threshold matrix size increases. Furthermore, when systematic dithering is used, the threshold values are periodically repeated for each threshold matrix, so for example, when a halftone image is read and input, the difference between the original image data and the threshold value changes periodically, and the output image A low-frequency moiré pattern was generated, and the image quality tended to be poor. Furthermore, a minimum average error method has been proposed in which the error of an output pixel with respect to the original image data is compensated for by surrounding pixels to faithfully reproduce the gradation of the original image data. Although this method has a great effect in removing moiré, it has the disadvantage that the connections between pixels become unnatural and the distortion characteristic to this method occurs (an unpleasant texture structure), resulting in a reproduced image that is difficult to see. This average error minimum method was further improved to improve character reproducibility using the CAPIX method (1985).
5-212), etc., have been proposed, but they still have the drawback of producing micro texture structures. Furthermore, the systematic dithering method described above also has the drawback that diagonal thin lines in particular become jagged during image reproduction.

On the other hand, each of the above-mentioned binarization methods results in large compression in terms of data amount.For example, if the input image data is 8 bits per pixel, after the binarization process, the image data becomes 1 bit per pixel. It is compressed to 1/8. Therefore, it requires only a small amount of storage capacity in an image memory, electronic file, etc., and is also advantageous when transferring image data via communication, and will continue to be an essential technology in the future.

〔the purpose〕

The present invention has been made in view of the above points, and an object of the present invention is to provide an image processing device that can obtain high-quality reproduced images.

A further object of the present invention is to provide an image processing device that reproduces high-quality images using compressed pixel data.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a circuit diagram of the image processing device in this embodiment. In the figure, 1 is a digital data output device that A/D converts image data from a COD sensor or video camera (not shown). , outputs digital data of predetermined bits (8 bits in this example) having density information. 2 is a binarization processing circuit that performs halftone processing on the 8-bit pixel data output from the digital data output device using systematic dithering or the minimum average error method, and converts the 8-bit pixel data to 1 bit per pixel. information.

Reference numeral 3 denotes a memory device consisting of a RAM or an electronic file, which stores the binary data output from the binarization processing circuit 2 (
A predetermined amount of 1-bit data) is stored. 4 is a multi-value conversion circuit that converts the binary data output from the memory device 3 into multi-value data of 8 bits per pixel, and the 8-bit multi-value data output from the multi-value conversion circuit 4 has a pulse width. The signal is input to a modulation circuit (PWM circuit) 5. To explain the operation, data of 8 bits per pixel outputted from the digital data output device 1 is converted into binary data of 1 bit per pixel in the z-value processing circuit 2, and then stored in the memory device 3.

Then, the binary data output from the memory device 3 is input to the multi-value converting circuit 4, where it is again converted into multi-value data of 8 bits per pixel and transferred to the PWM circuit 5.

The PWM circuit 5 performs pulse width modulation processing on the input 8-bit pixel data and generates a Norms width modulation signal (P
WM signal) is output to terminal 39. The numbers on each line represent the number of bits, which are shown in Figure 3.
The same applies to FIGS. 4 and 6.

Next, the multi-value converting circuit 4 will be explained in detail. FIG. 3 shows a detailed block diagram of the multilevel conversion circuit 4. As shown in FIG. Convert to 8-bit data as follows.

Data 0 → Data 00 Data 1 → Data FF This converted 8-bit data is sequentially stored in two lines (when one is written, the other is read) or several lines of buffer memory 8, and sequentially read from buffer memory 8. Then, a smoothing circuit 9 performs spatial filter processing. As the spatial filter, a one-dimensional or two-dimensional spatial filter may be used, and weighted averaging filters, Gaussian filters, averaging and edge enhancement synthesis filters, etc. are suitable.

Further, this spatial filter may be selected from among a plurality of filters depending on the image data, or the binarized data input to this multi-value converting circuit 4 may be binarized by various algorithms. If so, optimal multivalued data can be obtained for any binarized data by appropriately selecting a spatial filter.

The multivalued data output from the smoothing circuit 9 is input to the PWM @ path 5 via the terminal 10.

Next, the PWM circuit 5 will be explained in detail. FIG. 4 shows a detailed block diagram of the PWM circuit 5. Multi-value data (8 bits) output from the multi-value converting circuit 4 is converted into an analog quantity by a digital-to-analog converter (CD/A converter) 11. The converted pixel data is sequentially input to one terminal of a comparison circuit (comparator) 12.

On the other hand, the pattern signal generator 13 generates, for example, a triangular wave signal 56 once every predetermined number of picture elements (pixels) of the digital data, and inputs it to the other terminal of the comparator 12 .

The oscillator (
Master clock 5 from master clock generation circuit) 15
2 is counted down to, for example, a quarter cycle by the timing signal generation circuit 14, and becomes the pixel clock 51, which is used for pixel data transfer lock and latch timing of the D/A converter 11. Incidentally, since the image processing apparatus of this embodiment is applied to a laser beam printer, the horizontal synchronizing signal 55 corresponds to the well-known Beam Detect (BD) No. 48 which indicates the scanning position of the beam.

In the comparator 12, the analog-converted image signal 53
and the level of the triangular wave signal 56 are compared, and a pulse width modulated PWM signal 39 is output. And this PWM
The signal 39 is input to a modulation circuit (eg, laser driver 40 in FIG. 2) for modulating a laser beam, for example. Then, the laser beam is turned on/off according to the pulse width, and a halftone image is formed on the recording medium (also the photosensitive drum 45).

FIG. 5 is a diagram for explaining signal waveforms of each part of the device shown in FIG. 4. Referring to FIG. 5, the master clock 52 is the output of the oscillator 15, and the BD signal 55 is the horizontal synchronization signal described above. Further, the pixel clock 51 is obtained by counting down the master clock 52 of the oscillator 15 by the timing signal generation circuit 14. That is,
The pixel clock 51 is synchronized with the horizontal synchronization signal by the timing signal generation circuit 14, and is a signal obtained by counting down the master clock 52 to one-quarter period. The screen clock 54 further converts the pixel clock 51 obtained by the timing signal generation circuit 14 into the timing signal generation circuit 1.
For example, the screen clock 54 is obtained by counting down to one-third of the period of the pixel clock 51, and is a signal synchronized with the BD double signal. The screen clock 54 is a synchronizing signal for generating a triangular wave signal 56, and is input to the pattern signal generator 13. Further, the digital data input to the terminal 10 is multi-value data (8 bits) obtained by the multi-value converting circuit 4, and the analog video signal 53 is D/A.
:] This shows image data that has been D/A converted by the comparator 11, and as can be seen from the figure, the pixel clock 51
Each pixel data at analog level is output in synchronization with . As shown in the figure, it is assumed that the higher the analog level is, the higher the concentration becomes.

On the other hand, a triangular wave signal 56, which is the output of the pattern signal generator 13, is generated in synchronization with the screen clock 54 and is input to the comparator 12, as shown by the solid line "input to comparator" in FIG. The dashed line in the same figure is D/A 1
1, and is compared with the triangular wave 56 from the pattern signal generator 13 by the comparator 12, and as shown in the PWM output 39, the image data becomes pulse width modulated binary data. .

In this way, the signal processing in this embodiment enables almost continuous pulse width modulation by converting the multivalued digital data 10 into -H analog image data and then comparing it with the triangular wave 56 of a predetermined period, resulting in high gradation. It is possible to obtain a good image output.

Further, according to this embodiment, the screen clock is synchronized with the horizontal synchronizing signal 55 using the master clock 52 having a higher frequency (for example, 12 times the frequency of the triangular wave) than the frequency of the synchronizing signal for generating a pattern signal (for example, a triangular wave). 54, the pattern signal (triangular wave) 56 generated from the pattern signal generation circuit 13 has fluctuations (for example,
In this embodiment, the deviation between the pattern signals on the first line and the second line is 1/12 of the pattern signal period. Therefore, since the gradation information is pulse-width modulated almost steplessly using a pattern signal with little fluctuation, a high-quality reproduced image can be obtained.

As described above, for example, 8-bit multi-value image data is binarized and stored in the memory 3, 8-bit multi-value data is generated again from the binary data read from the memory 3, and further pulse width modulated. , it is possible to obtain high-quality playback output even with a small memory capacity.

FIG. 2 is a schematic diagram of a laser printer to which the present invention can be applied. In the figure, the terminal 39 is for inputting the PWM signal of FIG.
The M signal is input to the laser driver 40. And laser dry/<40 is the semiconductor laser 4 according to the PWM signal.
1 to modulate the beam. The emitted light beam of the semiconductor laser 41 is collimated by the collimator lens 42, is optically deflected by the rotating polygon mirror 43, and is transmitted to the fθ lens 4.
4 to scan the photosensitive drum 45. The light image formed on the photosensitive drum forms a static M1 latent image, and the image is output using a normal copying machine process. Further, 57 is a beam differential, and a BD signal 55 is formed based on the output of this beam detector 57.

FIG. 6 is a block diagram of an image processing apparatus according to another embodiment. Components having the same functions as those in FIG. 1 are designated by the same reference numerals, and their explanation will be omitted.

FIG. 6 shows a case where image data is transferred through a communication line and output to a printer, like a facsimile machine. The data is input to the digital data output 17. The encoding circuit F compresses the input binary data and transfers it to the communication line 18. The transferred compressed data is converted back into binary data by the decoding circuit 19 on the receiving side, and further converted into multi-value data (8 bits) by the multi-value conversion circuit 4. Thereafter, this multivalued data is converted into a substantially continuous pulse width modulation signal by PWM times +i85 as described above and output to the printer. With this configuration, the data capacity during communication can be significantly reduced, and high-resolution image signals can also be transferred in a short time. Further, on the receiving side, the decoded binary data is converted into multi-value data and this multi-value data is output to the printer as a pulse width modulation signal, so that high-quality output can be obtained.

Furthermore, in this embodiment, binary data (1 bit) is configured to be converted to multi-value data (8 bits), but for example, ternary data (2 bits) is converted to multi-value data (8 bits). In this case, O (white),
The three values of 1/2 (gray) and 1 (black) are converted by the multi-level conversion circuit 4 into intermediate data O → data 00, output i data 1/2 → data 80, and intermediate data 1 and output data FF and 8. Converted to bit data. In this case, the memory capacity will increase somewhat, but
Higher image quality output is possible.

As described above, input image data of a predetermined number of bits is binarized, stored in memory or transferred via a communication line, and then converted to multi-value data of a predetermined number of bits using a multi-value conversion circuit, and the pulse width Since the image output is obtained by forming a modulation signal, the following effects can be obtained.

1. Even if the memory capacity and data capacity during communication are small, high-quality output can be obtained.

2. It can be applied to data that has been binarized using various algorithms, and higher quality output can be obtained.

〔effect〕

As explained above, according to the present invention, high-quality reproduction output can be obtained with a small amount of data.

2 is a schematic configuration diagram of a laser printer to which the present invention can be applied, FIG. 3 is a detailed block diagram of the multi-level conversion circuit 4, FIG. 4 is a detailed block diagram of the PWM circuit 5, and FIG.
This figure is a diagram explaining signal waveforms of each part of the PWM circuit shown in FIG. 4, and FIG. 6 is a diagram showing another embodiment.

here 1 is a digital data output device, 2 is a binarization processing circuit; 3 is memory, 4 is a multivalue circuit; 5 is a PWM circuit, 7 is an 8-bit conversion circuit, 8 is back memory.

9 is a smoothing circuit, 11 is a D/A converter; 12 is a comparator; 14 is a timing signal generation circuit.

Claims (1)

[Scope of Claims] Means for converting input image data into binary data or ternary data, means for storing the binary data or ternary data output from the converting means, and means for storing the binary data or ternary data output from the storing means. a first converting means for converting binary data or ternary data into multi-value data having a larger amount of data than the binary or ternary data; and pulse width modulation of the multi-value data output from the first converting means. An image processing device comprising: second conversion means for converting into a signal.