JPS62188558A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain a reproduced picture with high quality by selecting a substatilly binarized picture signal alternately by a selecting means in synchronism with a horizontal synchronizing signal as to multi-value picture signal. CONSTITUTION:Pattern signal SW1, SAW2 of different period and an analog picture signal VA are compared respectively by comparators 4a, 4b to obtain binarized picture signals PW1, PW2 subjected to pulse width modulation. Further, a horizontal synchronizing signal HSYNC is used as the timing for selecting changeover to invert a filp-flop 24, and a selector 23 outputs switchingly the signals PW1, PW2 alternately at each line. Since the selecting means selects alternately the binarized picture signal in synchronism with, e.g., the horizontal synchronizing signal as to a multi-value picture signal, even if a dot picture, a character picture and a halftone picture exist mixingly in one picture, the occurrence of moire due to asynchronization of the pattern signal is prevented or reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and in particular to an image processing device that compares the levels of a multivalued image signal and a pattern signal to form a pulse-width modulated binary image signal. The present invention relates to an image processing device that forms an image based on the image.

[Prior Art] The applicant has already proposed this type of device. FIG. 4 is a circuit diagram of the previously proposed device. In the figure, 8-bit human-powered digital video signals VDO to VDT are latched by a latch circuit 1 using a video clock signal 172CL and synchronized. Video clock signal 172 CLK connects master clock signal CL to J- to flip-flop 5
This is a clock signal whose frequency is divided by two. The latched video signal is converted into an analog video signal V by the D/A converter 2.
The analog video signal VA is converted into a voltage level by a resistor 3 and then inputted to one input terminal of a comparator (CMP) 4.

On the other hand, the master clock signal CLK is frequency-divided by n by the frequency divider 6 and becomes a clock signal 1/nat.
Furthermore, the J- signal is frequency-divided by 2 by a flip-flop 8 to become a pattern clock signal PCLK with a duty ratio of 50%. Therefore, pattern clock signal PC:LK has a period n times that of video clock signal 172CLH. Further, the pattern clock signals Pct, K are inputted through a buffer 9 to an integrating circuit composed of a variable resistor 10 and a capacitor 11, and become a triangular wave signal (analog pattern signal) SAW having the same period as the pattern clock signal PCLK.

The triangular wave signal SAW is further connected to a capacitor 12 and a variable resistor 1.
The bias amount is adjusted by 3 and 3, and is further inputted to the other input terminal of the comparator 4 through the protection resistor 14 and the buffer amplifier 15. A comparator 4 compares the triangular wave signal SAW to the analog video signal V, and the analog video signal VA is pulse width modulated according to its density.

Here, in order to obtain high gradation, it is desirable that the maximum amplitude of the video signal VA and the maximum amplitude of the triangular wave signal SAW have the relationship shown in FIG. That is, the highest level V/max (for example, black level) of the video signal VA and the triangular wave signal SA
The relationship is such that the peak levels of W match, and the lowest level VAmin (eg, white level) of the video signal VA matches the bottom level of the triangular wave signal SAW. This is because maximum concentration resolution and linearity over the full scale are maintained.

Incidentally, images reproduced by such devices have various tones (characteristics or properties of images). For example, in character images, faithful reproduction of pixels that change from white to black or from black to white is emphasized rather than halftone reproduction, and in photographic images, emphasis is placed on reproduction of halftones whose density changes smoothly.

Therefore, in the apparatus shown in FIG. 4, the cycle of the pattern clock signal PCLK can be switched depending on which image tone reproducibility is prioritized. That is, the frequency divider 6 can change its frequency division ratio from 1 to n, for example, by the period switching signal SEL. In this way, when reproducing a character image, the frequency division ratio is set to, for example, 1, and one pixel of the human video signal is pulse width modulated by one triangular wave signal SAW, and pixels that change from white to black or from black to white are faithfully reproduced. There is. In the reproduction of a photographic image, the frequency division ratio is set to n, for example, and 0 pixels of the input video signal are pulse width modulated by one triangular wave signal SAW to reproduce a smooth gradation image.

However, in the above-mentioned device, the period, amplitude, and bias of the triangular wave signal SAW change by switching the frequency division ratio, so the relationship shown in FIG. 5 can no longer be satisfied as is. Also, variable resistor 10.
Even if 13 adjustments are made, if a single image contains both text and photographs, the quality of one of the images must be sacrificed. In this case, for example, if a pattern clock signal PCLK with a long period is applied to a character image, it tends to become a halftone image and moiré is likely to occur. On the other hand, even if a pattern clock signal PCL with a short period is applied to a halftone dot image, it is difficult to obtain a state in which the period perfectly matches, and moiré occurs.

[Object of the Invention] The present invention has been made in view of the above-mentioned drawbacks of the previously proposed techniques, and its purpose is to obtain a high-quality reproduced image. images, text images,
An object of the present invention is to provide an image processing device that can faithfully create an original image including one or more of halftone images and the like with a simple configuration and control.

[Means for solving the problem] As a means for solving this problem, for example, the image processing apparatus of the embodiment shown in FIG. An image processing device that forms a binary image signal and forms an image based on the binary image signal, the binary image signal PWI being pulse width modulated by comparing with pattern signals SAW 1 and SAW 2 of different cycles,
The screening means 4a, 4b forming PW2 and the horizontal synchronizing signal H5YN[
: Selection means 23 and 24 are provided for alternately selecting the substantially binary image signals pwt and PW2 in synchronization with .

Here, in practice, alternately selecting the binary image signals PWI and PW2 means that, instead of directly selecting the pulse width modulated binary image signals PWI and PW2 as in the embodiment, selecting the binary image signals PWI and PW2 with different cycles in the previous step Pattern signal SAW 1, 5AW2
This means that you may choose.

[Operation] In the configuration shown in FIG. 1, the pattern signals SAW 1 and SAW 2 with different periods and the analog image signal VA
are compared by comparators 4a and 4b, respectively, to obtain pulse width modulated binary image signals PW1 and PW2. Further, the flip-flop 24 is inverted using the horizontal synchronizing signal HSYNC as a selection switching timing, and the selector 23 alternately switches and outputs PWI and PW2 for each line.

[Examples] Examples of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of an image processing apparatus according to an embodiment. In the figure, the duty ratio is 5 from flip-flop 5 to J-.
0% 1/2 CLK pattern clock signal PCLK
1 is output, and the frequency divider 6 outputs a clock signal 1/n CL with an n times period.

Further, from the clock signal 1/n CLK, a pattern clock signal PCL with a duty ratio of 50% of 2 is formed by a flip-flop 8 at J-. The pattern clock signal PCLK 1 forms a triangular wave signal 5AW1 by the integral action of a time constant made up of a resistor 10a and a capacitor 11a, and the pattern clock signal PCLK 2 forms a triangular wave signal 5AW1 by the integral action of another time constant made of a resistor 10b and a capacitor llb. A signal SAW 2 is formed. In this case, according to the period of each pattern clock signal, FIGS. 2(a) and (b)
) The resistance values 10a, 10b and the capacitance values IIa, llb are determined so as to satisfy the amplitude condition.

The integral signal output from each integrating circuit is capacitor 1
2a and 12b, the DC component is once removed, and the subsequent voltage dividing circuits 13-1a, 13-2a and 13-1b, 13-2
The bias amount is determined by b. Each voltage dividing circuit 13-1
The resistance values of a, 13-2a and 13-1b, 13-2b are determined to satisfy the bias conditions shown in FIGS. 2(a) and 2(b), respectively. The pattern signals SAW 1 and SAW 2 with different periods thus obtained and the analog image signal VA are compared by comparators 4a and 4b, respectively, to obtain pulse width modulated binary image signals PWI and PW2. : is used as the selection switching timing to invert the flip-flop 24, and the selector 23 alternately switches and outputs PWI and PW2 for each line.

FIG. 3 is a timing chart showing the selection switching operation. Horizontal synchronization signal) 1sYNc 100 is a horizontal synchronization signal that comes from a configuration not shown, and for example, in a laser beam printer, it is a beam detection signal (BD) that gives the start of one main scanning line. The flip-flop 24 in J- is inverted every time the horizontal synchronizing signal H5YNC is generated, and the select signal 200 of its output Q is High"+"Low".
Repeat the level reversal. The selector 23 selects binary image signals PWI, PW according to the level of the select signal 200.
Select 2 alternately. Select signal 200 is “Low”
On the level line, the pattern signal SAW 1 and the analog image signal VA are compared by the comparator 4a to select the pulse width modulated binary image signal PWI, and on the line where the select signal 200 is at the "High" level, the pattern signal SAW 2 and the analog image signal VA are compared by the comparator 4b to obtain a pulse width modulated binary image signal P.
W2 is selected.

FIGS. 2(a) and 2(b) are diagrams showing the relationship between the triangular wave signals SAW 1 and SAW 2 and the analog image signal levels VAmax and VAmin when the designated periods are different, respectively. In this case, the conditions shown in FIG. 5 are satisfied for the amplitudes and biases of W 1 and SAW 2 to the triangular wave signal S.

[Effects of the Invention] As described above, according to the present invention, the selection means alternately selects the binary image signals in synchronization with, for example, the horizontal synchronization signal of the multivalued image signal, so that there are halftone dots within one image. Even if images, character images, halftone images, etc. are mixed, it is possible to prevent or reduce the occurrence of moiré due to pattern signal cycle mismatch. Therefore, such original images can be faithfully reproduced.
High-quality reproduced images can be obtained.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of the image processing device of the embodiment, Fig. 2(a)
, (b) is a diagram showing the relationship between each triangular wave signal SAW and the analog image signal level VA in the configuration shown in Figure 1, Figure 3 is a timing chart of the synchronization signal (ISYNC) and select signal, and Figure 4 is the previously proposed device. FIG. 5 is a diagram showing the ideal relationship between the triangular wave signal SAW and the analog image signal VA. In the figure, 1... Latch circuit, 2... D/A comparator, 4a, 4b... Analog comparator, 5°8, 2
4...Flip-flop to J-, 6...Frequency divider, 2
3...Selector.

Claims (2)

[Claims] (1) In an image processing device that compares the levels of a multivalued image signal and a pattern signal to form a pulse-width modulated binary image signal and forms an image based on this, a comparison is made with pattern signals of different cycles. a screening means for forming a binary image signal pulse-width-modulated; and a selection means for selecting substantially one of the binary image signals in synchronization with a predetermined synchronization signal for the multi-value image signal. An image processing device characterized by: (2) The image processing apparatus according to claim 1, wherein the selection means alternately selects the substantially binary image signal in synchronization with a horizontal synchronization signal for the multivalued image signal.