JPS62188559A - Picture processor - Google Patents

Abstract

PURPOSE:To obtain a reproduced picture with high quality without losing the density of a character picture and its steepness by selecting any of substantially binarized picture signals according to the picture element density of a multi- value picture signal. CONSTITUTION:Pattern signals SAW1, SAW2 of difference period and an analog picture signal VA are compared respectively by comparators 4a, 4b to obtain binarized picture signals PW1, PW2 subjected to pulse width modulation. Further, a high-order bit of muti-value picture signals VD0-VD7 is extracted at each picture element to detect a dark density and a selector 23 selects any of the substantially binarized picture signals PW1, PW2 according to the picture element density. Since any of the substantially binarized picture signals is selected according to the picture element density of a multi-value picture signal in this way, the density and steepness of a character picture even in an original including the character picture in a photographic picture are not lost and one picture is reproduced with fidelity by using simple constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image processing device, and particularly to an image processing device that compares the levels of a multivalued image signal and a pattern signal to form a pulse width modulated binary image signal, and The present invention relates to an image processing device that forms an image based on the image.

[Prior Art] The applicant has already proposed this type of device. FIG. 2 is a circuit diagram of the previously proposed device. In the figure, 8-bit input digital video signals VDo to VDT are latched by a latch circuit 1 using a video clock signal 1/2 CLK and synchronized. Video clock signal 1/2 CLK connects master clock signal CLK to J- through flip-flop 5
This is a clock signal whose frequency is divided by two. The latched video signal is converted into an analog video signal V by the D/A converter 2.
The analog video signal VA is converted into a voltage level by a resistor 3 and then input to one input terminal of a comparator (CMP) 4.

On the other hand, the master clock signal CLK is frequency-divided by n by the frequency divider 6 to become a clock signal 1/n CLK,
Furthermore, the J- signal is frequency-divided by 2 by a flip-flop 8 to become a pattern clock signal PCLK with a duty ratio of 50%. Therefore, pattern clock signal PCLK has a period n times that of video clock signal 1/2 CL. Further, the pattern clock signal PCLK is inputted through a buffer 9 to an integrating circuit composed of a variable resistor 10 and a capacitor 11, and becomes a triangular wave signal (analog pattern signal) SAW having the same period as the pattern clock signal PCL. The triangular wave signal SAW is further adjusted for its bias by a capacitor 12 and a variable resistor 13, and is further input to the other input terminal of the comparator 4 through a protection resistor 14 and a buffer amplifier 15. A comparator 4 compares the levels of the analog video signal VA and the triangular wave signal SAW, and the analog video signal VA is pulse width modulated according to its density.

Here, in order to obtain high gradation, it is desirable that the maximum amplitude of the video signal H and the maximum amplitude of the triangular wave signal SAW have the relationship shown in FIG. 3. That is, the highest level VAa+ax (for example, black level) of the video signal VA and the triangular wave signal SA
The relationship is such that the peak levels of W match, and the lowest level VAmin (eg, white level) of the video signal VA matches the bottom level of the triangular wave signal SAW. This is because maximum concentration resolution and linearity over the full scale are maintained.

Incidentally, images reproduced by such devices have various tones (characteristics or properties of images). For example, in character images, faithful reproduction of pixels that change from white to black or from black to white is emphasized rather than halftone reproduction, and in photographic images, emphasis is placed on reproduction of halftones whose density changes smoothly.

Therefore, in the apparatus shown in FIG. 2, the cycle of the pattern clock signal PCL can be switched depending on which image tone reproducibility is prioritized. That is, the frequency divider 6 can change its frequency division ratio from 1 to n, for example, by the period switching signal SEL. In this way, when reproducing a character image, the frequency division ratio is set to, for example, 1, and one pixel of the input video signal is pulse width modulated by one triangular wave signal SAW, and pixels that change from white to black or from black to white are faithfully reproduced. There is. In the reproduction of a photographic image, the frequency division ratio is set to n, for example, and 0 pixels of the input video signal are pulse width modulated by one triangular wave signal SAW to reproduce a smooth gradation image.

However, in the above-mentioned device, the period, amplitude, and bias of the triangular wave signal SAW change by switching the frequency division ratio, so the relationship shown in FIG. 3 can no longer be satisfied as is. Also, variable resistor 10.
Even if adjustment 13 is carried out, if a character image, a halftone image, and a photographic image are mixed in one image, it is no longer possible to make adjustments, so the image quality of one of them must be sacrificed.

[Object of the Invention] The present invention has been made in view of the above-mentioned drawbacks of the existing technology, and its object is to reproduce high-quality reproduced images without impairing the density and sharpness of character images. A further object is to provide an image processing device that can faithfully create an original image including one or more of halftone images, character images, halftone images, etc. with a simple configuration and control. It's about doing.

[Means for Solving the Problem] As a means for solving this problem, for example, the image processing apparatus of the embodiment shown in FIG. An image processing device that forms a modulated binary image signal pw and forms an image based on the modulated binary image signal pw, which includes pattern signals SAW 1 of different periods,
Screening means 4a for forming binarized image signals PWI, PI3 which are pulse width modulated in comparison with SAW2.
, 4b, and substantially 2 according to the pixel density of the multivalued image signal VA.
Selecting means 24 and 23 are provided for selecting either of the digitized image signals PWI and PI3.

Here, selecting one of the actual binary image signals pwt and PI3 means that instead of directly selecting the pulse width modulated binary image signals pwt and PI3 as in the embodiment,
In the previous stage, pattern signals 5AW1 and S with different cycles are generated.
This means that AW 2 may be selected.

[Operation] In the configuration shown in FIG. 1, the pattern signals SAW 1 and SAW 2 with different periods and the analog image signal VA
are compared by comparators 4a and 4b, respectively, to obtain pulse width modulated binary image signals pwt and PI3. At the same time, the upper bits of the multivalued image signals VDo to VDT are extracted for each pixel to detect a high density, and the selector 23 generates substantially binary image signals pwi, P according to the pixel density.
Select one of I3.

[Examples] Examples of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of an image processing apparatus according to an embodiment. In the figure, the duty ratio is 5 from flip-flop 5 to J-.
Pattern clock signal PCLK to 1/2 CL of 0%
1 is output, and the frequency divider 6 outputs a clock signal 1/n CLK with n times the period.

Further, from the clock signal 1/nCLK, a pattern clock signal PCL with a duty ratio of 50% is formed into a pattern clock signal PCL of 2 by a flip-flop 8 at J-. pattern clock signal P
In CL, 1 forms a triangular wave signal 5AW1 by the integral action of a time constant made up of a resistor 10a and a capacitor lla, and a pattern clock signal PCLK2 forms a triangular wave signal 5AW1 by an integral action of a time constant made up of a resistor 10a and a capacitor lla. A triangular wave signal SAW 2 is formed by the integral action. In this case, each pattern clock signal has a third clock signal according to its cycle.
Resistance values 10a, 10b and capacitance values 11a, 11b are determined so as to satisfy the amplitude conditions shown in the figure. The integral signal output from each integrating circuit is connected to a capacitor 12a.

12b, the DC component is once removed, and each subsequent voltage divider circuit 1
The bias amount is determined by 3-1a, 13-2a, 13-1b, and 13-2b. Each voltage dividing circuit 13-1a, 1
The resistance values of 3-2a'EL, 13-1b and 13-2b are determined so that each satisfies the bias conditions shown in FIG. Pattern signals S of different periods obtained in this way
AW 1 , SAW 2 and analog image signal VA are compared by comparators 4a and 4b, respectively, to obtain a pulse width modulated binary image signal PW1. PI3 is obtained, and at the same time, the selector 23 selects either the substantially binary image signal pwt or PI3 according to the density of the multivalued image signals VDo to VDT.

The digital image signals VDO to VDT represent the density of the pixel, for example, from "00" H at the white level to "F" at the black level.
It is possible to express 256 gradations up to F''H (H represents hexadecimal notation). In the embodiment, the upper 3 bits are
The AND output is connected to the select terminal S of the selector 23 as the select signal 100. That is, the select signal 100 becomes a "High" level when the 8-bit digital image signal is "EO" 8 or more, and becomes a "Low" level when "DF" is less than H. now,
In the pixel where the select signal 100 is "High" level, the pattern signal SAW 1 (the one with the shorter period) created by the pattern clock signal PCL 1 is compared with the analog image signal VA by the comparator 4a, and the pulse width modulated 2 is generated. The digitized image signal PWI is selected. Furthermore, in pixels where the select signal 100 is at the "Low" level, the pattern signal SAW 2 (longer cycle) generated by the pattern clock PCLK 2 and the analog image signal V
A is compared with the comparator 4b to obtain pulse width modulated 2
(l! converted image signal PW2 is selected. By doing this, for example, in a dark area where the 8-bit digital image signal is 'EO' 8 or more, one pixel of the digital image signal is pulsed by one triangular wave signal SAW1. Width modulation is performed to emphasize dark pixels with high density.In other words, for example, character pixels in a photographic image generally appear as dark, so the character pixels always maintain their density and steepness by the action of the select signal 100. On the other hand, in white or thin areas, one pixel is pulse width modulated using one triangular wave signal SAW 2,
Reproduce smooth density changes.

[Effects of the Invention] As described above, according to the present invention, one of the binary image signals is selected according to the pixel density of the multivalued image signal, so that even if a document includes a text image within a photographic image, the text To faithfully reproduce one image with a simple configuration without impairing the density and steepness of the image.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an image processing device according to an embodiment, FIG. 2 is a circuit diagram of an already proposed device, and FIG. 3 is a diagram showing an ideal relationship between a triangular wave signal SAW and an analog image signal VA. In the figure, 1... Latch circuit, 2... D/A converter, 4a, 4b... Analog comparator, 5°8...
・Flip-flop to J-, 6... Frequency divider, 23...
- Selector, 24...AND gate.

Claims (1)

[Claims] In an image processing device that compares the levels of a multivalued image signal and a pattern signal to form a pulse width modulated binary image signal and forms an image based on this, the pulse width is determined by comparing the levels of a pattern signal with a different period. Image processing characterized by comprising a screening means for forming a modulated binary image signal, and a selection means for selecting substantially one of the binary image signals according to the pixel density of the multivalued image signal. Device.