JPH0846787A - Image processing unit - Google Patents

Abstract

PURPOSE:To obtain a reproduced image with high image quality by providing a digital video signal generating means, a characteristic conversion means, a D/A converter means, a pattern signal generating means and a pulse width modulation signal generating means to the processing unit. CONSTITUTION:A signal from a digital data output device 1 is used for an address of a digital lookup table 9 for gamma correction. An output from the table 9 is converted into an analog signal for each picture element by a D/A converter 2 and given sequentially to a comparator circuit 4. Simultaneously an analog reference pattern signal is generated by a pattern signal generating section 3 and given to the circuit 4. The circuit 4 compares the video signal with the pattern signal to provide an output of a pulse modulation signal. The pulse modulation signal is given to a laser modulation circuit of a raster scanning print section 8 and a laser beam is stimulated/released depending on the pulse width and an intermediate tone image is formed on a recording medium of the print section 8.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an image processing apparatus for obtaining a reproduced image of high quality.

[0002]

2. Description of the Related Art Conventionally, it has been considered to reproduce a halftone image by using a dither method or a density pattern method. However, in any case, a small threshold matrix cannot obtain sufficient gradation depending on the dot size, and a large threshold matrix must be used. As a result, it is not possible to obtain a high-quality output because the texture structure is conspicuous due to the deterioration of resolution and the periodic structure of the matrix.

In order to eliminate the above-mentioned drawbacks, in the dither method, a method of further improving (multi-valued) the dot size by using a plurality of dither matrices can be considered. However, in such a method, a complicated circuit configuration is required to synchronize the dither matrices, and the system must be large, complicated and slow. Therefore, there is a limit to the multi-value conversion using a plurality of dither matrices. Further, JP-A-50-25112 discloses a method in which the conventional screening process is improved.

However, even if the method disclosed in the above publication is used in an apparatus for reproducing an image, the accuracy of gradation reproduction may decrease due to the delay in the response of the apparatus. Further, the prior art of the above publication (page 67, lower left column, line 19 to same page, lower right column, line 13) discloses that an analog video signal is linearly converted into a pulse width modulated signal.

However, as is known in the field of printing devices, since non-linear distortions are used in the halftone printing process, even if the above linear conversion is used (particularly the above linear conversion). Cannot be used with laser beam print engines). Therefore, in order to obtain a high quality halftone print, it is necessary to search for a non-linear conversion method, but in the method disclosed in the above publication,
Different triangular waves have to be used in successive scans to make non-linear changes, which complicates the configuration.

[0006]

The object of the present invention is to eliminate the above-mentioned drawbacks. Another object of the present invention is to provide an image processing apparatus capable of obtaining a reproduced image of high quality. A further object of the present invention is to provide an image processing apparatus capable of obtaining an excellent halftone image with a simple apparatus configuration. Another object of the present invention is to provide an image processing apparatus capable of obtaining a reproduced image of high quality at high speed.

A further object of the present invention is to provide an image processing apparatus capable of reproducing grayscale information in high gradation without impairing resolution. It is a further object of the present invention to provide an image processing device capable of correcting the gradation of a video image by performing non-linear conversion of the video signal into a pulse width modulation signal with a flexible structure. It is in.

A further object of the invention is a digital video signal generating means for generating a digital video signal,
Characteristic conversion means for converting the characteristics of the digital video signal generated by the digital video signal generation means to generate a characteristic conversion digital video signal, and a characteristic conversion digital video signal generated by the characteristic conversion means for analog video Digital-to-analog converting means for converting into a signal, pattern signal generating means for generating a pattern signal of a predetermined cycle, and generating a pulse width modulation signal according to the analog video signal and the pattern signal Another object of the present invention is to provide an image processing device comprising the pulse width modulation signal generating means of.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram of an image processing apparatus according to the present embodiment. In FIG. 1, reference numeral 1 is a digital data output device, which converts analog image data from a CCD sensor or a video camera (not shown) into an A / D ( analog/
Digital) conversion, and outputs a predetermined bit digital video signal having density information. This digital video signal may be temporarily stored in the memory or may be input from an external device by communication or the like. The signal from the digital data output device 1 is used as an address of the digital lookup table 9 for γ correction. Output from the look-up table 9 (in this example, as will be described later, OOH to F representing levels of 256 gradations)
Eight bits, which is the range of FH, are used. ) Is converted into an analog signal for each pixel by a digital-analog converter (D / A converter) 2 and one picture element is sequentially input to one terminal of the comparison circuit 4. At the same time, a triangular wave analog reference pattern signal is generated from the pattern signal generator 3 at a cycle corresponding to the desired pitch of the halftone screen and is input to the other terminal of the comparison circuit 4. The oscillator (reference clock generation circuit) is synchronized with the horizontal synchronization signal generated from the horizontal synchronization signal generation circuit 5 for each line.
A reference clock (master clock) from 6 is counted down to, for example, a quarter cycle by a timing signal generating circuit 7, and a transfer clock of the digital video signal and D
Used for the latch timing of the / A converter 2. In this embodiment, the horizontal synchronizing signal corresponds to a well-known beam detect (BD) signal because the present apparatus is applied to a laser beam printer. In the comparison circuit 4, the level of the analog-converted analog video signal and the level of the triangular wave pattern signal are compared, and a pulse width modulation signal is output. Then, this pulse width modulation signal is input to the laser modulation circuit of the raster scan printing unit 8 for modulating the laser beam, for example. As a result, the laser beam is turned on / off according to the pulse width, and a halftone image is formed on the recording medium of the raster scanning printing unit 8.

FIG. 2 is a diagram for explaining a signal waveform of each part of the apparatus shown in FIG. 2A shows the reference clock of the oscillator 6, and FIG. 2B shows the horizontal synchronizing signal described above. Further, FIG. 2C shows a pixel clock (PIXEL-CLK) obtained by counting down the reference clock of the oscillator 6 by the timing signal generation circuit 7. That is, FIG.
The pixel clock shown in (c) is a signal which is synchronized with the horizontal synchronizing signal and is counted down by the timing signal generating circuit 7 to a quarter cycle of the reference clock. Used. In FIG. 2D, the reference signal is synchronized with the horizontal synchronizing signal by the timing signal generating circuit 12
The pattern signal synchronization clock (screen clock (SCREEN-CLK)) of one cycle is shown in the three image clocks obtained by counting down to one-half cycle. That is, FIG.
The screen clock (d) is used as a synchronizing signal for generating a pattern signal and is input to the pattern signal generator 3. 2E shows a digital video signal (code data), which is output from the digital data output device 1. FIG. 2F shows an analog video signal D / A converted by the D / A converter 2, and as can be seen from the figure, each pixel data of analog level is output in synchronization with the pixel clock. As shown in the figure, the higher the level of the analog video signal, the higher the density (black).

On the other hand, the output of the pattern signal generator 3 (input of the comparison circuit) is as shown by the solid line in FIG.
It is generated in synchronization with the clock (d) and is input to the comparison circuit 4. The broken line in FIG. 2 (g) is the analogized image data (analog video signal) in FIG. 2 (f), and this analog video signal is the triangular wave (pattern signal) from the pattern signal generator in the comparison circuit 4. It is compared and converted into a pulse width modulation signal as shown in FIG.

As described above, in this embodiment, after the digital image signal is once converted into the analog image signal and then compared with the triangular wave signal of the predetermined period, almost continuous or linear pulse width modulation becomes possible and high gradation is obtained. The image output of is obtained.

Further, according to the present embodiment, the pattern signal synchronizing clock (screen clock) synchronized with the horizontal synchronizing signal by using the reference clock having a frequency higher than the frequency of the pattern signal synchronizing clock for generating the pattern signal (for example, triangular wave). Therefore, the fluctuation (jitter) of the pattern signal generated from the pattern signal generation circuit 3, for example, 1
In the present embodiment, the offset (offset) between the pattern signals of the second line and the second line is 1/12 or less of the cycle of the pattern signal. This precision is required to ensure high-quality halftone reproduction in which the line screen is formed evenly and smoothly for each line. Therefore, since the grayscale information is accurately pulse-width modulated using the pattern signal with less fluctuation, a high-quality reproduced image can be obtained.

FIG. 4 is a schematic perspective view of a scanning optical system of a laser beam printer (raster scanning printing unit) to which the present invention can be applied. In the figure, the scanning system has a semiconductor laser that emits a laser beam modulated according to the pulse width modulation signal described above. The light beam modulated by the semiconductor laser 21 is collimated by the collimator lens 20 and has a rotary polygon mirror (applying means) 22 having a plurality of reflecting surfaces.
Receive light polarization by. An image forming lens 23 called a polarized light beam fθ lens forms an image on the photosensitive drum 12a to form a beam. In this beam scanning, the tip of one line scanning of the light beam is reflected by the mirror 24 and the light is guided to the beam detector (detector) 25. The beam detection (BD) signal from the beam detector 25 is used as a well-known horizontal synchronizing signal in the scanning direction H (horizontal direction). In this example, the horizontal synchronizing signal is composed of this BD signal. Therefore this B
The D signal is detected for each line scanning of the laser beam and serves as a timing signal for sending the pulse width modulation signal to the semiconductor laser.

The "line segment" used in this specification means a dot formed on a recording medium, and the dot length (size) is the pulse width of the pulse width modulation signal. It changes according to.

Next, each part of the image processing apparatus of this embodiment will be described in more detail with reference to FIGS. 3A and 3B. FIG.
3A and 3B describe the device of FIG. 1 in more detail. As described above, in this embodiment, the BD signal is used as the horizontal synchronizing signal. However, since this BD signal is essentially a signal that is asynchronous with the pixel clock,
It causes horizontal jitter. Therefore, in this embodiment, the reference clock (72
The jitter is suppressed to 1/4 or less of the width of one pixel by using the oscillator 100 that generates M-CLK, 72 MHz clock.

The BD synchronizing circuit 200 is a circuit for this purpose. Reference clock from the original oscillator 100 (72M-CL
K) is the D-latch 201/202 via the buffer 101.
-Supplied to 203. On the other hand, the BD signal is input to the data terminal D of the D latch 201 via the terminal 200a and synchronized with the reference clock. Further, the BD signal is delayed by two reference clock pulses by the D latches 202 and 203. The delayed BD signal is input to one input terminal of the NOR gate 103, and the inverted output of the D latch 201 is input to the other input terminal of the NOR gate 103. The output of the NOR gate 103 is the NOR gate 10
4 is input to one input terminal, and the output of the flip-flop circuit 102 is input to the other input terminal of the NOR gate 104.

With the above configuration, the flip-flop circuit 1
From 02, a clock (36 M-CLK, 36 MHz) obtained by dividing the reference clock by 1/2 is output. Therefore, the output from the flip-flop circuit 102 (36M-
CLK) is a clock synchronized with the BD signal within one cycle of the clock 72M-CLK.

The output of the D latch 203 is the D latch 20.
Flip-flop circuit 1 by 4, 205, 206
The output of 02 is delayed by 36M-CLK3 clock pulses. Now, the inverted output of D-latch 201 and D-latch 2
The output of 06 is input to the NOR gate 207, and the internal horizontal synchronizing signal B synchronized with the reference clock (within one cycle)
A D-Pulse is formed. FIG. 5 shows the BD synchronization circuit 20.
It shows the timing of the signal of each part of 0. In the figure, A-1 is a BD signal, and A-2 is a reference clock (72M-CLK) generated from the original oscillator 100. A-
Reference numeral 3 denotes an inverted output from the D latch 201, which is a signal obtained by synchronizing the BD signal with a reference clock (72M-CLK). A-4 represents the output from the D latch 203,
This is a signal obtained by delaying A-3 by two reference clock pulses.
A-5 is a clock (36M-CLK) output from the flip-flop 102. A-6 is a signal obtained by further delaying A-4 by 3M-CLK3 clocks, and is output from the D latch 206. A-7 is an internal horizontal synchronizing signal BD-Pulse. As shown in A-7, the internal horizontal synchronizing signal BD-Pulse rises in synchronization with the rising of the first reference clock (72M-CLK) after the rising of the BD signal, and 8 reference clocks, that is, 2 This is a signal that is in the state of "1" for the pixel. This internal horizontal synchronizing signal (BD-Pulse) is a signal that serves as a horizontal reference of this circuit.

The video signal will be described with reference to FIG. 3 again. Pixel clock (PIXEL-CLK) is JK
The clock 36M- by the flip-flop circuit 105
It is formed by dividing CLK in half. The 6-bit digital video signal is the pixel clock (PIXEL-CL
K) is latched by the D-latch 10,
Is output to the ROM 12 for γ conversion. ROM
The 8-bit video signal gamma converted by 12 is D /
It is further converted into an analog signal by the A converter 13, and the comparator 1 is used for comparison with a triangular wave as described later.
5 is input to one of the input terminals. The pulse width modulation signal output as a result of the comparison is input to the laser driver of the raster scanning print unit.

Reference numeral 300 is a screen clock generation circuit. The screen clock (analog reference pattern signal synchronization clock) generated from the screen clock generation circuit 300 serves as a reference clock for forming a triangular wave.

The counter 301 is a flip-flop circuit 1
It is used as a divider that divides 36M-CLK generated from 02. The counter 301 has input terminals A, B,
The counter 303 has C and D, and the switch 303 presets predetermined data to the terminals A to D of the counter 301. The division ratio is determined by the values set in these input terminals A to D. For example, A: 1, B: 0, C:
When set to 1, D: 1, 36M-CLK is 1/3
Is divided into. Also, the NOR gate 302 and the BD-Pu
Horizontal synchronization is established by the lse signal. The signal divided by the counter 301 is further divided by 1/2 by the JK flip-flop circuit 304 to form a screen clock having a duty ratio of 50%. A triangular wave is generated by the triangular wave generation circuit 500 based on this screen clock (SCREEN-CLK). FIG. 6 shows the waveform of each part of the screen clock generation circuit 300. B-1 is an internal horizontal synchronizing signal BD-Pulse, B
-2 is a clock 36M-CLK, B-3 is a counter 30
"1", "1", "1", at terminals D, C, B, A of 1
Screen clock (SC when “0” is set)
REEN-CLK), B-4 is the screen clock B-
Triangle wave based on 3, B-5 is counter 301
Input terminals D, C, B and A of "1", "1", "0",
Screen clock (SC) when "1" is set
REEN-CLK), B-6 is the screen clock B-
It is a triangular wave when 5 is used as a reference. That is, one cycle of the triangular wave shown by B-4 corresponds to two pixels, and one cycle of the triangle shown by B-6 corresponds to four pixels. In this way, the cycle of the triangular wave can be arbitrarily changed by switching the switch 303, and in this embodiment, from 1 pixel to 1
A triangular wave with a period corresponding to 6 pixels can be generated.

Next, the triangular wave generating circuit 500 will be described with reference to FIG. Screen clock (SCREE
(N-CLK) is once received by the buffer 501, and a triangular wave is generated by the integrator composed of the variable resistor 502 and the capacitor 503. Further, the triangular wave has a capacitor 504, a protection resistor 506, and a buffer amplifier 507.
Is input to one input terminal of the comparator 15.

The triangular wave generating circuit 500 has two variable resistors. That is, the variable resistor 502 is for adjusting the amplitude of the triangular wave, and the variable resistor 505 is for adjusting the bias or offset of the triangular wave. Adjustment of the amplitude and offset of the triangular wave by the variable resistors 502 and 505 described above will be described with reference to FIG. 7. The triangular wave Tri-1 shown by the solid line in FIG.
Is an unadjusted triangular wave. By adjusting the variable resistor 502, the triangular wave Tri-1 can be changed to the amplified triangular wave Tri-2 shown by the dotted line. Further, the variable resistor 505 can be adjusted to shift the triangular wave, or the offset can be adjusted to obtain the triangular wave Tri-3 shown by the alternate long and short dash line. In this way, the triangular wave generating circuit 500 can obtain a triangular wave having an arbitrary amplitude and offset. In addition, as shown in FIG.
The relationship between the triangular wave signal and the output (analog video signal) from the D / A converter 13 is that the digital input value of the D / A converter 13 is at the maximum level (FFH, H).
Is the hexadecimal system), the output level of the D / A converter 13 and the maximum value of the triangular wave become the same level, and the D / A
The digital input value of the converter 13 is at the minimum level (OO
It is desirable that the output level of the D / A converter 13 at the time of H) and the minimum value of the triangular wave be the same. This state can be easily realized by arbitrarily adjusting the amplitude and offset of the triangular wave in the circuit of FIG.

However, in the present embodiment, the amplitude and offset of the triangular wave are adjusted as follows in order to obtain a high gradation output. A laser driver (not shown) for emitting a laser beam generally has a delay time. Also, the delay time until the laser emits light tends to become longer due to the laser emission characteristic curve. For this reason, the laser does not start emitting the laser beam unless the width of the pulse signal (binarized data) input to the driver exceeds a certain level. When the input signal is a periodic pulse signal as in the present embodiment, the laser does not emit light unless the duty ratio of the input pulse signal is above a certain value (predetermined value). On the contrary, when the duty ratio of the pulse is increased to some extent (a predetermined value) or more, that is, when the light emission pause time is shortened, the laser is always in the light emitting state as in the case of full lighting. Therefore, if the triangular wave is adjusted as shown in FIG. 7B, the part near the OOH (minimum value) and the part near FFH (maximum value) of the 256 gradations of the input data of the D / A converter 13 are lost. This deteriorates the gradation. Therefore, the variable resistors 502 and 505 are adjusted so that the pulse width immediately before the laser starts emitting light is adjusted at the level of the input data OOH of the D / A converter 13, and similarly D / A
The variable resistors 502 and 505 are adjusted so that the pulse width is such that the laser is fully lit at the level of the input data FFH of the A converter 13. This is shown in FIG.
It is shown in (c).

As can be seen from FIG. 7C, in the present embodiment, the minimum input data OOH is input to the D / A converter 13.
Is input, a pulse having a certain width (pulse width immediately before the laser is turned on) is output from the comparator 15. In addition, the D / A converter 13
When the maximum input data FFH is input to, the duty ratio of the pulse output from the comparator 15 is 100.
The pulse width is not set to%, but the pulse width is set to the duty ratio at which the laser is fully turned on. As a result, 2
The input data of 56 gradations can vary the lighting time of the laser over almost the entire area, and a reproduced image with excellent gradation can be obtained. The method described above is not limited to the radar printer, but can be used for an inkjet printer, a thermal printer, or other raster scanning devices.

The ROM 12 for γ conversion is shown in FIG.
Will be used to explain in more detail. The γ conversion ROM 12 is used to obtain a reproduced image with high gradation. In this embodiment, a ROM having a capacity of 256 bytes is used, but since the input digital video signal is 6 bits, essentially a capacity of 64 bytes is sufficient. Figure 8 shows the γ conversion ROM
12 is a memory map of 12. As described above, since the ROM 12 has a capacity of 256 bytes in this embodiment, four types of conversion tables can be written. That is, address OOH ~
TABLE-1 up to 3FH, addresses 40H to 7FH
Up to TABLE-2, addresses 80H to BFH up to TABLE-3, addresses COH to FFH up to TAB.
This is LE-4.

FIG. 9 shows a concrete example of input / output characteristics of the input video signal-converted video signal obtained by each conversion table.
4 levels from 0 to 255 according to each conversion table
(00 is converted to FFH). The conversion table can be switched by changing the upper addresses A6 and A
It can be realized by changing 7. In this embodiment, this switching can be performed for each line.
In FIG. 3, 400 is a circuit for switching the table for each line. Internal horizontal sync signal BD-Pulse
Is input to the counter 401, and the count value of the counter 401 is output from the terminals QA and QB to the terminal A of the ROM 12 respectively.
6, input to A7. The counter 401 constitutes a ring counter by the RCO inverter 402 and the switch 403, and the switching cycle of the conversion table can be changed depending on the state of the switch 403. For example, the switch 403 is “1” (terminal B),
When "1" (terminal A), always select TABLE-4,
Switch 403 is "1" (terminal B), "0" (terminal A)
When the switch 403 is "0" (terminal B) or "0" (terminal A), TABLE-4 to TABLE-3 are selected as shown in FIG. 10A.
TABLE-4 can be selected for each line. By changing the conversion table for each line in this way, the gradation can be improved.

In general, when an image is reproduced by using an electrophotographic method, it is difficult to obtain gradation in a bright portion than in a dark portion. In the example shown in FIG. 9, only the bright part is changed and the common conversion table is used for the dark part in order to obtain the optimum gradation. Further, in this embodiment, the tables can be switched in the main scanning direction by the laser beam. The screen clock is divided into 1/2 by the JK flip-flop circuit 404, the divided signal is input to one terminal of the exclusive OR circuit 406, and the terminal QB of the counter 401 is connected to the other terminal. .

With this structure, the conversion tables can be switched in a staggered manner as shown in FIG. 10B, and the gradation can be further improved. The switch 405 is a switch for selecting whether or not to switch the conversion table in a staggered manner, and is “0” for “not selected”,
"1" means "selection". The numerical values in each frame in FIG. 10 (b) are the numbers of the selected conversion table. (Table 1
Table 4), one cycle of the screen clock in this example corresponds to three cycles of the pixel clock.

As is clear from the above description, the ROM 1
Each scan line formed by the laser according to the data output from the second conversion table is composed of continuous line segments. Each line segment of continuous scan lines is aggregated to form a plurality of columns,
A line screen is formed by the plurality of columns.

When the image signal is processed by the circuit shown in FIG. 3 and outputted to the reproducing means such as a laser beam printer, the reproduced image has a vertical stripe structure. (In this example, the line screen is formed by the vertical stripes, and the vertical stripes are formed by each line segment of continuous scanning lines.) The phase of the triangular wave is BD.
This is because each line is the same for the Pulse signal (internal horizontal synchronizing signal).

The circuit of this embodiment forms a triangular wave after counting (delaying) 12 reference clocks from the rise of the BD-Pulse signal. The generation timing of this triangular wave is the same for all lines, and as a result, the phases of the triangular waves on each line match.

The image data is output from the digital data output device 1 as described above. The digital data output device 1 outputs image data at a predetermined timing in synchronization with a signal equivalent to the BD-Pulse signal. Specifically, the data output device 1 starts counting the reference clock after inputting the BD signal, and outputs the image data after counting a predetermined number of the reference clocks. As a result, the transmission timing of the image data necessary for image reproduction is the same in all lines, and an excellent reproduced image without image blur can be obtained.

Further, since the generation timing of the triangular wave and the transmission timing of the image data necessary for image reproduction have the same relationship in all the lines, the reproduced image has a vertical stripe structure without image blur. The structure serves, for example, to reduce certain moire fringes. As described above, this vertical stripe structure forms a line screen, which consists of vertical lines that extend at an angle in a direction perpendicular to the raster scan lines.

Further, by slightly shifting the phase of the triangular wave line by line, it is possible to obtain a reproduced image having a diagonal screen structure. This is effective in reducing moire fringes that occur when a halftone original is read and processed, for example. The angle of the oblique line structure can be arbitrarily set by shifting the phase of the screen clock for each line as appropriate. For example, when a triangular wave of one cycle is generated for three pixels, if the triangular wave is shifted by one pixel for each line (that is, the screen clock is shifted by 120 ° for each line), a diagonal structure of 45 ° is formed. A reproduced image with is obtained. FIG. 11 shows a circuit for realizing the reproduction image having the above-mentioned diagonal line structure. If this circuit is used instead of the screen clock generation circuit 300 of FIG. 3, a reproduced image having a hatched structure can be obtained. In FIG. 11, the internal horizontal synchronizing signal (BD-Pulse) is supplied to the D latch 3
Pixel clock (PIXEL-CL
The internal horizontal synchronizing signal BD-Pulse having three kinds of phases is generated by latching with K). Counter 35
8, inverters 359, 360 and gate circuits 361 to 361
Using 367, one of three types of BD-Pulse is selected for each line and is input as the LOAD signal of the counter 351, and the phase of the screen clock is changed for each line. The counter 351 divides 36M-CLK by 1/3, and the JK flip-flop circuit 354 further divides the output of the counter 351 by 1/2. As a result, the screen clock is generated once every three pixels. FIG. 12 shows the generation timing of each line of the screen clock and the triangular wave generated by the circuit of FIG. The three types of triangular waves shown in FIG. 12 are sequentially generated every three lines.

When the reference pattern signal is generated in a cycle synchronized with a plurality of picture elements as described in the present embodiment, synchronization for generating the pattern signal is performed for each of a plurality of scanning lines equivalent to the width of the pattern signal. It is also possible to shift the signal by half a cycle of the reference pattern signal. By doing so, the growth center position of the pulse width shifts for each of the plurality of scanning lines, and the output image becomes an image like halftone dots arranged obliquely and looks natural to the eye.

In the circuit of FIG. 3, a ROM is used for γ conversion.
Although 12 is used, the γ conversion table can be arbitrarily rewritten by software by using it as an S-RAM and connecting it to the bus line of the microcomputer. This makes it possible to change the γ-conversion curve depending on the type of the original, and to improve the flexibility of the system.

FIG. 13 shows an example of this, and this circuit may be inserted instead of the ROM 12 of FIG.
In the figure, 12a is a γ conversion-like S-RAM, 30 is a decoder, 31 is a microcomputer for rewriting the γ conversion table, 32 and 33 are tristate buffers, and 34 is a bidirectional tristate buffer.

Further, although the switches 303, 403 and 405 are used for mode switching in FIG. 3, the expandability of the system can be increased by making these switches controllable by the microcomputer 31. .

[0042]

As described above in detail, according to the present invention, a reproduced image of high quality can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic diagram of an image processing apparatus in this embodiment.

FIG. 2 is a diagram showing a waveform of each part of the device shown in FIG.

FIG. 3 is a diagram showing a connection state between FIGS. 3A and 3B.

3A is a detailed diagram of the image processing apparatus shown in FIG. 1. FIG.

3B is a detailed diagram of the image processing apparatus shown in FIG. 1. FIG.

FIG. 4 is a schematic diagram of a scanning optical system of a laser beam printer to which the present invention can be applied.

5 is a diagram showing waveforms at various points in the circuit shown in FIG.

6 is a diagram for explaining a triangular wave formed in the circuit of FIG.

7 (a), (b) and (c) are diagrams for explaining a method of adjusting a triangular wave.

FIG. 8 is a diagram illustrating a look-up table of a γ conversion ROM 12;

FIG. 9 is a characteristic diagram of an input video signal-converted video signal.

10 (a) and (b) are used for each scan line and γ.
It is a figure which shows the relationship of a conversion table.

FIG. 11 is a circuit diagram for shifting the phase of a triangular wave for each line.

FIG. 12 is a diagram for explaining a triangular wave having a phase shift for each line.

FIG. 13 is a diagram for explaining another embodiment.

[Explanation of symbols]

 1 Digital Data Output Device 2, 13 D / A Converter 4, 15 Comparator 5 Horizontal Sync Signal Generation Circuit 3, 500 Triangular Wave Generation Circuit 7 Timing Signal Generation Circuit 8 Raster Scan Print Section 12 ROM 21 Semiconductor Laser 300 Screen Clock Generation Circuit

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] August 14, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

A further object of the present invention is to input a digital image signal represented by a plurality of bits for each pixel by a clock signal at a predetermined cycle, and a pattern signal having a plurality of cycles according to the clock signal. A pattern signal generating means, a selecting means for selecting a cycle of the pattern signal, a digital image signal synchronized with the clock signal, and the pattern signal selected by the selecting means and synchronized with the clock signal. An image processing apparatus having pulse width modulation means for pulse width modulation according to the above.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction content]

[0042]

[Effect] Since the cycle of the pattern signal can be selected, optimum pulse width modulation can be performed according to the image tone of the image data, and deterioration of image quality in high-definition image recording can be reduced. Further, since the pattern signal is generated in synchronization with the input digital image signal, the pulse width modulation processing is performed with the pattern signal and the digital image signal always keeping a constant relationship in the pattern signal of any cycle. Therefore, a stable reproduced image can always be obtained.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H04N 5/202 5/91 H04N 1/40 101 E C3-5 5/91 H (72) Inventor Alice Marie Dentermont USA. 02109 Massachusetts, Boston, Fulton Street 120 (72) Inventor Craig Edward Goldman United States. 01760 Massachusetts, Natick, Post Oak Lane Number 10 7

Claims (8)

[Claims] 1. A digital video signal generating means for generating a digital video signal, and a characteristic conversion for converting a characteristic of the digital video signal generated by the digital video signal generating means to generate a characteristic conversion digital video signal. Means, digital-analog conversion means for converting the characteristic-converted digital video signal generated by the characteristic conversion means into an analog video signal, pattern signal generation means for generating a pattern signal of a predetermined period, An image processing apparatus comprising a pulse width modulation signal generating means for generating a pulse width modulation signal according to an analog video signal and the pattern signal. 2. The image processing apparatus according to claim 1, wherein the pattern signal generating means generates a triangular wave having a predetermined cycle as the pattern signal. 3. The image processing apparatus according to claim 1, wherein the apparatus further continuously lines the recording medium with a beam in accordance with the pulse width modulation signal generated by the pulse width modulation signal generating means. An image forming unit for scanning and forming an image on the recording medium is provided, and the characteristic converting unit converts the characteristic of the digital video signal for each of the continuous lines scanned by the image forming unit. An image processing apparatus comprising means for changing a coefficient. 4. The image processing apparatus according to claim 1, wherein the characteristic conversion means has a storage means containing digital information for applying at least one nonlinear transformation to the digital video signal. Image processing device. 5. The image processing apparatus according to claim 4, wherein the storage unit has a read-only memory for storing a digital lookup table for gamma conversion. 6. The image processing apparatus according to claim 1, wherein the digital video signal fluctuates between a maximum value and a minimum value, and the pulse width modulation signal generating means determines that the digital video signal has the minimum value. An image processing apparatus, wherein a pulse width modulation signal having a predetermined pulse width is generated. 7. The image processing apparatus according to claim 1, wherein the digital video signal fluctuates between a maximum value and a minimum value, and the pulse width modulation signal generating means determines that the digital video signal has the maximum value. An image processing apparatus, wherein a pulse width modulation signal having a predetermined pulse width is generated. 8. The image processing apparatus according to claim 1, wherein the pattern signal generating means includes an adjusting means for adjusting at least one of an amplitude and an offset of the pattern signal. Processing equipment.