JPS62185465A - Picture processor - Google Patents

Abstract

PURPOSE:To prevent moire stripe by modulating the picture of edge part at the 1st period and modulating the picture at non-edge part at a period longer than the preceding period, and outputting the result to as to obtain an output picture with high quality to a color original for both a character/line drawing and halftone originals. CONSTITUTION:Digital picture data 67a-67d are converted into analog picture signals 66a-66d by D/A conversion circuits 4a-4d and become picture data in synchronism with a picture element clock 63. Further, pattern signals 98a-98d from pattern signal generators 6a-6d are generated in synchronism with screen clocks 62a-62d and inputted to comparator circuits 5a-5d. The analog picture signals 66a-66d are comparated with the pattern signals 98a-98d by the comparator circuits 5a-5d to form binary PWM signals 65a-65d. Further, screen clocks 62a-62d are formed by using a reference clock 69 having a higher frequency. Thus, contrast information is subjected to pulse width modulation nearly steplessly by using the pattern signals 98a-98d with less variation to obtain a reproduced picture with high quality.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that converts and outputs manually generated image data.

[Prior Art] Conventionally, the dither method and the density pattern method, for example, are well known as methods for binarizing images with halftones. This method can output halftones with high image quality, but on the other hand, it has the disadvantage that characters and line drawings are cut off and the image quality deteriorates.

Furthermore, when outputting a halftone original with dither, the halftone and dither
Another drawback is that moiré fringes occur due to beats in the periodic structure of the pattern, resulting in a significant deterioration of image quality.

[Problems to be Solved by the Invention] The present invention provides an image processing device that eliminates the drawbacks of the prior art and outputs image data of an original or halftone original including halftones, characters, and line drawings without degrading the image quality. It provides:

[Means for Solving the Problem] As a means for solving this problem, for example, the image processing apparatus of the embodiment shown in FIG. 1 includes an image data input circuit 1,
Black component extraction circuit 2, page memories 3a, 3b, 3c,
3d, D/A conversion circuits 4a, 4b, 4c, 4d, and comparison circuit 5a.

5b, 5c, 5d, and a pattern signal generator 6a.

6b, 6c, and 6d, a timing signal generation circuit 8, and an edge identification circuit 7.

[Operation] In the configuration shown in FIG. 1, yellow (Y), magenta (M), and cyan (
The three-element image data C) is divided by the black component extraction circuit 2 into four elements: yellow (Y), magenta (M), cyan (C), and sensuality (K). Each element is connected to the page memory 3a together with an edge identification signal from the edge identification circuit 7.
~3d. Here, the edge identification signal is 1 in the edge portion and O in the non-edge portion. When outputting images,
Image data is read from the page memories 3a to 3d, and the edge identification signal read out at the same time is input to the timing signal generation circuit 8. The image data is converted into analog quantities by D/A conversion circuits 4a to 4d, and then converted to analog quantities by D/A conversion circuits 4a to 4d.
At step 5d, the signal is compared with the triangular wave from the pattern signal generators 6a to 6d and modulated into a pulse width. At this time, the comparison circuit 58
The triangular wave input to ~5d is generated by the clock from the timing signal generation circuit 8, and when the edge identification signal is 1, it is switched to a triangular wave synchronized with 1 pixel, and when it is 0, it is switched to a triangular wave synchronized with 3 pixels. The edge portion is an output for each pixel, and the non-edge portion is an output with a rough screen applied to every three pixels.

[Embodiment] FIG. 1 is a block diagram of an image processing apparatus in this embodiment.

In the figure, the image data input circuit 1 receives image data from a CCD centimeter or video camera (not shown).
g conversion, A/D conversion, yellow (Y), magenta (
Digital image data of predetermined bits having density information of three colors: M) and cyan (C) is input. This digital image data may be temporarily stored in a memory, or may be input from an external device through communication or the like. This digital image data is processed by the black component extraction circuit 2 using the formula (1).
The amount of thought (K) is calculated according to the following.

K=min (Y, M, C) (1) The output from the black component extraction circuit 2 and the edge identification signal 64a from the edge identification circuit 7 are a total of 7 bits as shown in FIG. It is recorded in page memories 3a to 3d as image data.

At the time of image output, image data is read from the page memories 3a to 3d for each color, and the edge identification signal 64b, which is the most significant bit of the read data, is input to the timing signal generation circuit 8.

The remaining 6-bit digital image data 67a to 67d are converted into analog image signals 66a to 66d by D/A conversion circuits 4a to 4d, and each pixel is sequentially input manually to one terminal of comparison circuits 5a to 5d. be done. On the other hand, from the pattern signal generators 6a to 6d, triangular wave pattern signals 98a to 98a are generated at a frequency of once for each predetermined pixel of the image data.
98d is generated and inputted to the other terminals of the comparison circuits 58 to 5d. In synchronization with the horizontal synchronization signal 68, the reference clock 69 from the oscillator becomes the pixel clock 63, which is counted down to, for example, a quarter cycle by the timing signal generation circuit 8, and locks the image data transfer and D/
It is used for latch timing of A conversion circuits 48 to 4d. Note that the horizontal synchronization signal 68 may be generated internally, or
It may be given from outside. In this embodiment, the horizontal synchronization signal 68 corresponds to the well-known beam detect (BD) signal 99 since this apparatus is applied to a laser beam printer. Comparison circuit 5a~
5d, the analog image signals 66a~
66d and triangular wave pattern signals 98a to 98d are compared, and pulse width modulated binary image data PWM signals 65a to 65d are output. The pulse width modulated PWM signals 65a to 65d are then input to, for example, a modulation circuit for modulating a laser beam, and the laser beam is turned on/off according to the pulse width to produce a halftone image on a recording medium, which will be described later. It is formed.

FIG. 9 is a diagram for explaining signal waveforms of each part of the apparatus shown in FIG. 1. The top waveform in FIG. 9 is the oscillator reference clock 69, and the second waveform in FIG. 9 is the horizontal synchronization signal 68 described above. Further, the third waveform in FIG. 9 shows the pixel clock 63 obtained by counting down the reference clock 69 of the oscillator by the timing signal generation circuit 8. That is, the pixel clock 63 is generated by the timing signal generation circuit 8.
This is a signal that is synchronized with the horizontal synchronization signal 68 and counts down the reference clock 69 to a quarter period,
The signal is input to the D/Ai conversion circuits 48 to 4d and is used as a transfer lock for image data. The fourth waveform in FIG. 9 takes the pixel clock 63 obtained by the timing signal generation circuit 8 as an example, and further converts it to three pixel clocks obtained by counting down to one-third period in the timing signal generation circuit 8. Screen clocks 62a to 62 with one cycle
d is shown. That is, the screen clocks 62a to 62d
is a synchronizing signal for generating pattern signals 98a to 98d, and is input to pattern signal generators 6a to 6d.

Also, the fifth waveform in FIG. 9 is digital image data 67.
a to 67d, and are output from page memories 3a to 3d. The sixth waveform in FIG. 9 is the D/A conversion circuit 4a to 4.
Analog image signals 66a to 6 D/A converted by d
6d, and analog level image data is output in synchronization with the pixel clock 63. As shown in the figure, it is assumed that the higher the concentration, the higher the concentration.

On the other hand, pattern signals 98a-98d from pattern signal generators 6a-6d are generated in synchronization with screen clocks 62a-62d, as shown by the solid line of the seventh waveform in FIG. Man-powered. Incidentally, the broken line of the seventh waveform in FIG. 9 is the sixth analog image signal 66a to 66d in FIG.
98d, and as shown in the bottom waveform of FIG. 9, analog image signals 66a to 66d are pulse width modulated binary data pW
~85 d.

In this way, in this embodiment, the digital image data 67a
~67d are once converted into analog image signals 66a~66d, and then compared with pattern signals 988~98d of a predetermined period, it is possible to perform almost continuous pulse width modulation, and a high gradation image output can be obtained. It is.

Further, according to this embodiment, the pattern signal (for example, triangular wave) 9
Since the screen clocks 62a to 62d synchronized with the horizontal synchronization signal 68 are formed using the reference clock 69 with a frequency higher than the frequency of the synchronization signal for generating 88 to 98d, the screen clocks 62a to 62d are generated from the pattern signal generation circuits 6a to 6d. In this embodiment, the fluctuation of the pattern signals 98a to 98d (the deviation between the pattern signals of the first line and the second line in the A column) is 1/12 of the pattern signal period.

Therefore, since the gradation information is pulse width modulated almost steplessly using the pattern signals 98a to 98d with little fluctuation, a high quality reproduced image can be obtained.

The pulse width modulated output generated in the above manner is D/
6 if the A conversion circuits 4a to 4d have 6-bit input.
Since a 4-level analog output is obtained, a 64-level pulse width modulation output is obtained.

Here, switching of the timing signal will be explained in detail.

FIG. 6 is an explanatory diagram of timing signal switching, and the pixel clock 63 shown in FIG. 9 enters the selector 60 directly or via the ⅓ frequency dividing circuit 61. The selector 60 uses the edge identification signal 64b as the select signal 64c to switch the input signal of the selector, and the screen clocks 62a to 62
For d, the edge part of the image - the non-edge part of the pixel clock image - the pixel clock whose frequency is divided by 1/3 is selected and output from the above-mentioned result.

In the above explanation, the signal conversion at the time of 1/3 frequency division was shown in FIG. 9, but when the pixel clock is selected, the waveforms of the pattern signals 98a to 98d in FIG. 9 correspond to one pixel clock. It is a triangular wave with one period, and all comparisons in the latter stages are the same.

Therefore, the following waveforms are obtained as output waveforms of the final PWM signals 65a to 65d depending on the image quality of the read image.

Edges of the image → Output of pulse width modulation using a triangular wave synchronized with a 1-pixel clock Non-edge parts of the image - Output of pulse width modulation using a triangular wave synchronized with a 3-pixel clock. For edge portions, output is obtained by applying a screen with a coarse number of lines.

Next, several examples of the edge identification circuit 7 that outputs the edge identification signal 64a will be described.

FIG. 2 shows a block diagram of the edge identification circuit 7.

The Y, M, and C signals are converted to Y by the average value circuit 20.

The average value of M and C is taken, and an average value signal 23 corresponding to monochrome is generated.

Output=1/3 (Y+M+C). This average value signal 23 is then input to the line memory 21.

The line memory 21 is composed of four line memories 31a to 31d as shown in FIG. 3(a), one line of input image data is selected by a selector circuit 35a, and the line memory performs writing. On the other hand, line memories to which writing has not been performed are read out by the selector circuit 35b to obtain image signals 36a, 36b, and 36c.

Writing to such line memory is performed by steps 31a and 31b.

31c and 31d are performed sequentially, resulting in an output image signal 368.
36c outputs three consecutive lines of image data.

The output signal from such line memory enters the arithmetic circuit 22. The function of this arithmetic circuit 22 is to perform the smoothing operation shown in FIG. 3(e). Such hardware circuits are shown in FIGS. 3(b)-(d). That is, the image signals 36a, 36b, and 36c of each line pass through delay circuits 30a to 30f corresponding to one pixel clock, and then to each tap 37.
It is output from a to 37j. The outputs of each tap are all added together as shown in FIG. 3(C). Next, multiplier 38
x 1/9 to obtain the desired smoothing output. An output 38a, which is the difference between the smoothing output and the center pixel data 37e, is compared with a threshold value 33 by a comparator 32 shown in FIG. 3(d) to obtain an output 39.

By the above calculation, the output of the edge identification circuit 7 is a binary output of O when the difference between the center pixel and the smoothing value>kl, and 1 when the difference between the center pixel and the smoothing value≦1. However, 1 can be set as appropriate for the parameter at this time using the threshold value 33 in FIG. 3(d).

Therefore, when we investigated the value of the output 38a depending on the type of original, we found that images with small local density differences such as photographs and high line counts (150 lines/in) of halftone originals
(ch or higher), the output becomes O. Especially the latter,
Although it is originally a dot image made of halftone dots, the pitch of the halftone dots is fine, and due to the MTF characteristics of the input sensor, the halftone dots are not resolved and the image appears blurry, which is also a factor in the output being 0. It has become.

On the other hand, the number of lines for text, line drawings, and halftone originals is low (50 lines/i
(about n ch h), the output becomes 1.

As the next example of an edge identification circuit, a circuit that calculates and identifies the primary image amount of an image will be described with reference to FIGS. 4(a) to 4(d).

The line memory 21 is composed of six line memories 42a to 42f as shown in FIG. 4(a), one line of the average value signal 23 is selected by the selector circuit 41a, and the line memory performs writing. On the other hand, the line memory to which writing has not been performed is read out by the selector circuit 41b and receives image signals 44a, 44b, 44c, 44d.
.

Get 44e. Writing to such line memory is 42a
, 42b, 42c, 42d, 42e.

42f and finally output image signals 44a to 44e.
outputs 5 consecutive lines of image data.

The output signal from the line memory 21 is shown in FIG.
) to the next stage arithmetic circuit 22 shown in FIG.

The function of this arithmetic circuit 22 is to perform operations for the primary image shown in FIGS. 4(d) and 4(e).

Using each output of the delay circuit 40, FIGS. 4(d) and (e)
The values of the primary image components in the vertical and horizontal directions are calculated as shown in FIG. Here, the vertical primary image amount X, the horizontal primary image amount Y, and the sum Z of their absolute values are calculated by the following equation.

X= (43a+43b+43f+43g+43+4
3 1+43p+43q+43u+43v)-(43d
+43e+43i+43j+43n+43o+43s+
43t+43x+43y)Y= (43a+43b+
43c+43d+43e+43f+43g+43h+4
3 i+43j)-(43p+43q+43r+43
s+43 is 143u+43v+43w+43x+43y
)z=a (IXl+1Yl) a is the coefficient, IXI is the absolute value of and output 49 is obtained.

By the above calculation, the output of the edge identification circuit 7 is 1 of the image.
Next image size > k2 Primary image size of output 1 image ≦ 2
When , set to obtain a binary output of output O. However, the parameter 2 at this time is shown in Figure 4 (C).
The threshold value 46 can be determined as appropriate.

When the image is an edge part, the value of the sum Z of the above primary image quantities is 48
On the other hand, in the non-edge portion, the value of Z 48 tends to become small.

The edge identification circuit 7 of the next example will be explained.

An average value signal 23 is calculated by averaging the three color signals of Y, M, and C in an average value circuit 20, and this is manually input to the line memory 21.

The line memory 21 is composed of four line memories 51a to 51d as shown in FIG. 5(b), and one line of input image data is selected by a selector circuit 55a and written into the line memory. On the other hand, line memories to which writing has not been performed are read out by the selector circuit 55b, and image signals 56a, 56b, and 56c are obtained. Writing to such line memory is performed by 51a.

51b, 51c, and 51d are performed in sequence, and in the end, the output image signals 56a to 56c output three consecutive lines of image data.

The output signal from this line memory is sent to the next stage arithmetic circuit 2.
Enter 2. The function of this arithmetic circuit 22 is to perform calculations using the Laplacian operator shown in FIG. 5(a). The hardware circuit is shown in FIGS. 5(C) to (e). That is, the image signal 56a of each line.

56b and 56c are delay circuits 50a for one pixel clock.
Outputs are obtained from each of the taps 57a to 57e via 50d. The output of each tap is as shown in Fig. 5(d).
, 57b, 57d.

57e are all added up. Also, 57c is multiplied by 4. Then, both are subtracted by an adder 52 to obtain the desired Laplacian output 58a. This Laplacian output 58a is compared with a threshold value 54 by a comparator 53 shown in FIG. 5(e), and an output 59 is obtained.

By the above calculation of 'lA, the output of the edge identification circuit 7 is a binary output which is O when the Laplacian operation value>k3, output 1 when the Laplacian operation value≦3. However, the parameter 3 at this time is the threshold value 54 in Fig. 5-(e).
You can sanction it as appropriate. Note that the Laplacian operator uses all nine pixels as shown in Figure 12,
Furthermore, a matrix other than 3×3 may be used.

FIG. 7 is a schematic diagram of an image output device to which the present invention can be applied.

In FIG. 7, 71a to 71d are scanning optical systems, and the image data from the comparison circuits 5a to 5d are taken out as light beams (laser and -J) by this scanning optical system, and this light beam is cyan (C). , magenta (M), yellow (Y
), photosensitive drums 7 arranged in parallel corresponding to black (K)
It is configured to form images on 2a to 72d. Developing devices 73a to 7 are located near the photosensitive drums 72a to 72d.
3d, and each of the photosensitive drums 72a to 72a is disposed on the side of a conveyor belt 77 for conveying recording paper (not shown).
Chargers 74a to 74d are arranged opposite to 72d. To explain the operation of the above configuration, the scanning optical system 7
The modulated light beams output from the photosensitive drums 1a to 71d form optical images on the respective photosensitive drums 72a to 72d, and then, through an electrophotographic process, the formed images become electrostatic latent images, which are transferred to the developing units 73a to 73d. 73d, and the charger 7
4a to 74d, each color is sequentially transferred onto the recording paper held on the withdrawal belt 77 to form an image.

FIG. 13 shows an example of a scanning optical system. The aforementioned PWM signals 65a to 65d modulate the laser driver 89, pulse width modulate the semiconductor laser 81, and cause it to emit light. The emitted light beam of the semiconductor laser 81 is collimated by the collimator lens 80, is optically deflected by the rotating polygon mirror 82, and is converted into fθ
The lens 83 scans the photosensitive drum 72. During this beam scanning, the tip of one line of the light beam is reflected by a mirror 84 and guided to a detector 85 . The detection signal from this detector 85 is used as a synchronization signal (the above-mentioned BD signal) in the scanning direction H (horizontal direction). The light image formed on the photosensitive drum 72 forms an electrostatic latent image, and the image is output using a normal copying machine process.

Further, FIG. 10 shows the photointerrupters 75a to 75a in FIG.
75d is a groove diagram. A pinhole plate 92 with pinholes is inserted between the lamp 90 and the detector 91, and when the transfer paper 93 passes between them, light from the lamp 90 to the detector 91 is blocked, and the transfer paper 9
Detect the tip of 3. This timing signal is referred to as a TOP signal 96.

FIG. 11 shows the horizontal synchronizing signal 65. from the avant-garde TOP signal 96 and BD signal 99. 6 is a block diagram of a generation circuit that generates a vertical synchronization signal 68. FIG. First, the vertical synchronization signal 68 starts from the input of the TOP signal 96, counts the BD signal 99 by the programmable counter 144a, and obtains the vertical synchronization signal 65 when a predetermined count is reached. Further, the horizontal synchronization signal 68 is based on the pixel clock 63 with the BD signal 99 as a reference.
is formed when a predetermined count is reached.

As a result of the image processing described above, the following can be said.

Edge portions of characters and line drawings are identified as edge portions by the edge identification plate circuit. Further, even a halftone dot image with a low number of lines can be identified as an edge portion because the input sensor can sufficiently identify the halftone dots, and the printer outputs an image with excellent resolution.

On the other hand, the inside of thick characters, areas close to continuous tone such as photographs, or halftone dot images with a high number of lines are identified as non-edge areas, and are therefore For example, if the printer is 40
If it is 0 dot/inch (abbreviated as 400 dpi), the detailed image output will be 400 dots.
/inch (400 dpi) line screen, rough image output is 400 / 3 = 133 dpi line screen output. As a result, all small characters are output at 400 dpi, and for thick characters, only the edges are output at 400 dpi, and the inside of the characters is output at 133 dpi.
It is output as i. This also solves the problem of characters, line drawings, etc. being cut off.

Next, in the case of halftone originals, by using the pulse width modulation method as in this example, it is possible to output multiple gradations per pixel, so the moiré phenomenon that was a problem when applying the dither method becomes less noticeable. It disappears.

Note that in this example, a fine image was processed with a 1 pixel clock, and a rough image was processed with a 3 pixel clock, but this is just an example, and it is sufficient to select a line number that is different between the two. Although the two portions of the non-edge portion and the non-edge portion may be changed continuously. The edge identification circuit is not limited to this embodiment. or,
The same effect can be obtained even without the black component extraction circuit.

[Effects of the Invention] As described above, according to the present invention, high-quality output images can be obtained for both color originals, including halftone originals such as text/line drawings, photographs, and halftone originals. Furthermore, moire fringes can also be prevented.

[Brief explanation of drawings]

Figure 1 is a block diagram of the image processing device, Figure 2 is a block diagram of the edge identification circuit, - Figure 3 (a
) is a block diagram of the line buffer, Figures 3(b) and (c
), (d) is a block diagram of the arithmetic circuit, Figure 3 (e) is a smoothing filter diagram, Figure 4 (a)
are block diagrams of line buffers, Figures 4(b) and (C)
is a block diagram of the arithmetic circuit, Figures 4(d) and (e) are first-order image filter diagrams, and Figure 5(
a) is a diagram of the Laplacian operator, Figures 5(b) and (c)
, (d) and (e) are block diagrams of the arithmetic circuit, FIG. 6 is an explanatory diagram of timing signal switching, FIG. 7 is a schematic diagram of the image recording device, FIG. 8 is a storage format diagram of the page memory, and FIG. Figure 9 is a timing chart of modulation, Figure 10 is a configuration diagram of a photointerrupter for paper detection, Figure 11 is a block diagram of a horizontal synchronization signal and vertical synchronization signal generation circuit, Figure 12 is a diagram of another Laplacian filter, and Figure 12 is a diagram of another Laplacian filter. Figure 13 is an example of a scanning optical system. In the figure, 1... Image data input circuit, 2... Black component extraction circuit, 3a to 3d... Page memory, 4a to 4d.
...D/A conversion circuit, 5a to 5d...Comparison circuit, 6a
~6d... Pattern signal generation circuit, 7... Edge identification circuit, 8... Timing signal generation circuit. Figure 2 Figure 3 (0) Figure 3 (b) Figure 3 (C) Figure 3 (d) Figure 3 (e) Figure 4 (d) Figure 4 (e) Figure 4 (c ) Fig. 5 (0) Fig. 5 (b) Fig. 6b Fig. 5 (C) Fig. 511 (d) Fig. 5 (e) Prisoner 6 1fu;. Figure 7 Figure 9 Figure 10 Figure 11

Claims (6)

[Claims] (1) In an image processing device that converts and outputs input image data, an edge identification unit detects an edge portion of an image, and a unit changes the modulation cycle of the image output according to an identification signal from the edge identification unit. By having
An image processing device characterized in that an image of an edge portion is modulated in a first period, and an image of a non-edge portion is modulated and outputted in a period longer than the first period. (2) Edge detection is characterized in that when the difference between the density of the center pixel of a predetermined area and the average density of the area is larger than a certain threshold value, it is detected as an edge area, and when it is smaller, it is detected as a non-edge area. An image processing apparatus according to claim 1. (3) The edge portion is detected when the calculated value using the first-order differential filter is larger than a certain threshold value, and when it is smaller, the edge portion is detected as a non-edge portion. The image processing device described. (4) The image processing apparatus according to claim 1, wherein the edge portion is detected when the Laplacian calculation value is larger than a certain threshold, and when it is smaller, the edge portion is detected as a non-edge portion. (5) The image processing apparatus according to any one of claims 1 to 4, wherein the input for calculation of the edge identifying means is an average value of the input signal. (6) The image processing device according to claim 1, wherein the modulation is performed by comparing analog-converted image data with a triangular wave having a predetermined period.