JP2866091B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus that outputs an image signal after pulse width modulation.

[Prior Art] Conventionally, when binarizing multi-valued image information including a halftone image to form an image, for example, a dither method, a density pattern method, etc. using a threshold matrix are well known as the binarization method. ing. In a laser beam printer or the like, the multi-valued image data is compared with a triangular wave or the like, and the density of the image data is subjected to pulse width modulation so as to correspond to the pulse width.
The binarization method is common.

[Problems to be Solved by the Invention] However, when a line drawing such as a character is pulse-width modulated by these methods, the edge portion becomes jagged in steps,
There are problems such as a decrease in resolution of image data.

The present invention has been made in view of the above conventional example, and has as its object to provide an image processing apparatus capable of obtaining a high-quality reproduced image without lowering the resolution of an image signal.

[Means for Solving the Problems] To achieve the above object, an image processing apparatus according to the present invention comprises:
An input unit for inputting a digital image signal represented by a plurality of bits for each pixel, and a time corresponding to a predetermined number of pixels of the digital image signal as one cycle, having an extreme value in the one cycle, and the one cycle Pattern signal generating means for generating a first pattern signal and a second pattern signal in which the relative positions of the extrema are different from each other; a digital image signal and the first pattern signal input by the input means; And a pulse for selectively outputting a first pulse width modulation signal generated by comparing the first pulse width modulation signal and a second pulse width modulation signal generated by comparing the digital image signal with the second pattern signal. And a first pulse width modulation signal and a second pulse width modulation signal generated by the pulse width modulation signal generation means. Generation starting position of the pulse width modulation signal is different from each other.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Laser Beam Printer (FIGS. 1 and 5)] FIG. 1 is a block diagram showing a schematic configuration of an image signal processing section of the laser beam printer of this embodiment.

In the figure, reference numeral 101 denotes a video data output unit,
A / D conversion is performed on image data from a CD sensor or a video camera, and digital multi-valued image data of a predetermined bit (here, 8 bits) including density information is output in synchronization with a synchronous clock RCLK. This digital image data is temporarily stored in the buffer memory 102, and the timing signal generation circuit 111
The data is read out as 8-bit video data 131 in synchronization with the horizontal synchronizing signal (HSYNC) and the video clock signal (VCLK). In this way, through the buffer memory 102, the image data from the video data output unit 101 is out of synchronization and the speed is converted.

One of the video data 131 read from the buffer memory 102 is delayed by the delay circuit 116 by a delay for the identification of the identification circuit 113, and then converted into an analog video signal 121 by the D / A converter 103. Further, the other of the video data 131 is input to an identification circuit 113 described later, and is used for selecting a modulation signal described later. This analog video signal 121
Is input to one input terminal of comparators 104 to 106, and the other input terminal of each of comparators 104 to 106 binarizes analog video signal 121 (PWM
(Modulation) are input.

Here, the pattern clocks 123 to 125 are a triangular wave and a sawtooth wave, respectively, and as shown in FIG.
The pattern clock 123 input to 4 is a clock signal having a right end, the pattern clock 124 input to the comparator 105 is at the center, and the pattern clock 125 input to the comparator 106 is a clock signal having a vertex at the left end.

Further, a selection signal 122 is output in response to a change in the density of the video data 131 input to the identification circuit 113 (which will be described in detail later).
One of the output modulated signals is selected. The modulation signal (PWM) 129 output from the select circuit 107 is synchronized with the recording paper by the gate circuit 108 and input to the laser driver 109 of the recording unit 132. Here, the laser driver 109 drives the semiconductor laser 114 at a constant current for a time corresponding to the pulse width of the input modulation signal 129. The laser beam emitted from the semiconductor laser 114 scans the photoconductor,
A copy image is formed by an electrophotographic process.

FIG. 5 is a block diagram showing a schematic configuration of the recording unit 132 of the laser beam printer. Reference numeral 109 denotes a laser driver, 114 denotes a semiconductor laser, 51 denotes a collimator lens, 52 denotes a polygon mirror, and 53 denotes an fθ lens. The laser light thus modulated and corrected for fθ scans the photoconductor 50 by raster scanning to form an electrostatic latent image, and transfers the image to recording paper by an electrophotographic method. A beam detector (BD) 133 is provided near the scanning start position of one line of the laser beam and detects the start of scanning of the laser beam.

Referring back to FIG. 1, the BD generation circuit 110 generates a BD signal 116 based on the signal from the beam detector (BD) 133. The BD signal 116 and a clock 117 having a frequency four times or more that of the input video data are input from the crystal oscillator 115 to the timing signal generating circuit 111, and a horizontal synchronizing signal (HSYNC) and a video clock (VCLK) are generated. Output. Furthermore,
The timing signal generation circuit 111 outputs a screen clock (SCLK) 118 to the pattern clock generation circuit 112. The screen clock (SCLK) 118 is one time of the video clock (VCLK) 120, if necessary. This is a 50% duty clock synchronized with the video clock 120 at twice or three times the cycle.

In the pattern clock generation circuit 112, a pattern clock 123 to 12 having a predetermined shape is generated by a screen clock 118.
Has raised five. In this embodiment, these pattern clocks are triangular waves and sawtooth waves synchronized with the screen clock 118 and having the same period as the screen clock 118. These pattern clocks 123 to 125 are input to comparators 104, 105, and 106 for binarizing the analog image data 121 by PWM (pulse width modulation).

[Explanation of Modulation Example of Image Signal (FIGS. 1 and 2)] FIG. 2 is a diagram for explaining signal waveforms at various parts of the image signal processing unit in FIG.

Referring to FIG. 2, the video clock 120-4 will be described.
A cycle clock 117 of twice or more is input from the crystal oscillator 115 to the timing signal generation circuit 111, and the BD signal 116 and the clock 11
An HSYNC signal 119, a video clock signal 120, and a screen clock signal 118 synchronized with 7 are output. As described above, the screen clock 118 is a synchronizing signal for generating a pattern clock, and the pattern clock generation circuit 112
Has been entered.

The analog video signal 135 shown in FIG. 2 is obtained by converting the video data read from the buffer memory 102 into a D / A converter.
An example of conversion into an analog signal at 103 is shown. As can be seen from FIG. 2, each pixel data of analog level is output in synchronization with the video clock 120. As shown in the figure, it is assumed that the analog level becomes blacker and the density becomes higher as it goes down.

The pattern clocks 123 to 125, which are the outputs of the pattern clock generation circuit 112, are generated in synchronization with the screen clock 120 as shown in FIG.
Input to 05,106. The modulation signal 128 is a signal obtained by comparing the video signal 135 with the pattern clock 125 by the comparator 106 and binarized. The modulation signal 127 is obtained by comparing the video signal 135 with the pattern clock 124 by the comparator 105.
Shows the coded signal, and further the modulation signal 126 is the video signal 1
Reference numeral 35 denotes a binarized signal which is compared with the pattern clock 123 by the comparator 104. Then, in response to the selection signal 122 from the identification circuit 113, the selection circuit 107
, One of the three modulation signals 126 to 128 is selected and input to the recording unit 132 to be a drive signal for the laser driver 109.

In the above description of the pulse width modulation, the screen clock 118 has the same cycle as the video clock 120, but may have a cycle twice or three times the video clock 120 if necessary. In this case, the pattern clock 12
Similarly, the period from 3 to 125 is twice as long as the video clock 120,
The cycle is doubled.

[Identification Circuit and Operation Description (FIGS. 3 and 4)] FIG. 3 shows the identification circuit 113 and the select circuit 107 of this embodiment.
3 shows the configuration of a portion 130 enclosed by a broken line in FIG.

The 8-bit video data 131 read out from the buffer memory 102 is sequentially latched into 8-bit D-type flip-flops 301, 302, and 303 in synchronization with the video clock 120. The data latched on the flip-flops 301 to 303 are latched on the flip-flops 304 to 306 again by the screen clock SCLK118.

307 to 309 are multi-valued comparators (comparators)
The comparator 307 has flip-flops 304 and 305.
When the flip-flop 304 is larger than 305 (when A input> B input), the comparator 307
Output is set to a high level. The comparators 308 and 309 operate in the same manner as the comparator 307. The comparator 308 receives the output values of the flip-flops 305 and 306, and the output value of the flip-flop 305 is larger (A>
B), the output is set to a high level and output.
The comparator 309 compares the output values of the flip-flops 306 and 304, and outputs a high level when the output of the flip-flop 306 is larger.

On the other hand, each of the modulation signals 126 to 128 is
The output of each of the gates 307, 308, and 309 is input to each of the AND gates 310 to 314. The output of OR gate 315 is output when screen clock 18 is twice as long as video clock 120 and OR gate 316.
The output of the screen clock 118 is the video clock 120
Is selected by the selector 317 so as to be used when the period is three times as large as the period.

The select signal 134 input to the selector 317 is a signal output from the timing signal generation circuit 111, and selects the A input when the screen clock 118 has a cycle twice as long as the video clock 120, and the screen clock 118 This signal selects the B input when the cycle is three times as long as the video clock. The select signal 134 may be generated by a CPU (not shown) or input from an external video data output portion.

The output of the OR gate 315 has a flip-flop of 30
The output of the flip-flop 304 is compared and the modulation signal 126 is selected and output when the output value of the flip-flop 304 is larger, while the modulation signal 128 is output when the output value of the flip-flop 305 is larger. The OR gate 316 compares the output values of the flip-flops 304 to 306. When the output value of the flip-flop 304 is the maximum, the modulation signal 126 is output. When the output value of the flip-flop 306 is the maximum, the modulation signal 127 is output.
However, when the output value of the flip-flop 305 is the maximum, the modulation signal 128 is selected and output. In other words, the video data 131 within one cycle of the screen clock 118 is compared, and the PWM signal 129 such that the ON signal is the longest at the maximum of the video data 131 is selected and output.

FIG. 4 is a diagram showing an output example of a PWM signal output by the identification circuit shown in FIG. 3, and FIG. 4A is a screen clock 118.
Shows an example when the period is three times as long as the video clock 120, and FIG.
The figure shows an example in the case of a double cycle.

First, referring to FIG. 4A, assuming that a video signal 401 as shown in FIG. 4 is input, as described with reference to FIG. 2, the modulated signals 128 to 126 modulated by the respective pattern clocks are respectively shown in FIG. 4A. 402 to 404.
In the first cycle of the pattern clock, that is, in the portion of the pixel data 41 to 43, the density of the modulation signal 402 is 405 since the density of the pixel data 43 among the pixel data 41 to 43 is the maximum.
Since the portion is selected and the density of the pixel data 45 is the highest in the portion of the pixel data 44 to 46 in the second cycle, 4
06 part is selected. Similarly, the PWM output 129 becomes 41
It becomes as shown by 0.

Similarly, in FIG. 4B, the pixel data 41 and the pixel data 42 are compared in the first cycle of the pattern clock signal, and since the density of the pixel data 42 is higher, 4
In the second cycle of the pattern clock, the pixel data 43 is compared with the pixel data 44. Since the pixel data 44 has a higher density, the 422 portion of the modulation signal 415 is selected and output. Similarly, in the third cycle, since the density of the pixel data 45 is higher, the 423 portion of the modulation signal 416 is selected.
Similarly, the modulated signal 129 to be output is the PWM output 417
It becomes as shown by.

Therefore, as apparent from FIGS. 4A and 4B, the modulation signal (PWM) output 129 is more concentrated in the portion where the density of the analog video signal 401 is higher than the modulation signals 126 to 128, and the ON signal is more concentrated. ing. For this reason, blurring of a line drawing such as a character can be prevented, and the output is particularly suitable for an electrophotographic printer.

As described above, according to this embodiment, an image can be reproduced by emphasizing a high-density portion of image data, so that the outline of a line drawing or the like is not blurred and the resolution at which image data is reproduced is increased. There is.

[Effects of the Invention] As described above, according to the present invention, there is an effect that a high-quality reproduced image can be obtained without lowering the resolution.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a schematic configuration of a laser beam printer according to an embodiment, FIG. 2 is a timing chart for explaining an operation of pulse width modulation, and FIG. 3 is an identification circuit of FIG. And FIG. 4A is a circuit diagram showing details of the select circuit. FIG. 4A is a diagram showing an example of modulation when the screen clock is three times the cycle of the video clock. FIG. 5 is a diagram illustrating an example of modulation at the time, and FIG. 5 is a diagram illustrating the formation of a binary image in a recording unit when a laser beam printer is used as an example. In the figure, 101: video data output unit, 102: buffer memory, 103: D / A converter, 104 to 106: converter, 107: select circuit, 108: gate, 109: laser driver, 110: BD generation circuit, 111 ... timing signal generation circuit, 112 ... pattern clock generation circuit, 113 ...
… Identification circuit, 114… semiconductor laser, 115… crystal oscillator, 116… BD signal, 117… clock, 118… screen clock, 119… horizontal synchronization signal, 120… video clock, 121… ... Analog video signal, 122 ... Selection signal, 123-125 ... Pattern clock, 126-128 ... Modulation signal, 129 ... PWM signal, 132 ... Recording unit, 133 ... Beam detector, 134 ... Select signals, 303 to 306, flip-flops, 307 to 309, comparators, 317, selectors.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-185464 (JP, A) JP-A-62-185465 (JP, A) JP-A-1-282965 (JP, A) (58) Field (Int.Cl. ⁶ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60

Claims (1)

(57) [Claims] An input means for inputting a digital image signal represented by a plurality of bits for each pixel, and having an extreme value in one cycle, wherein one cycle corresponds to a time corresponding to a predetermined number of pixels of the digital image signal. Pattern signal generating means for generating a first pattern signal and a second pattern signal having different relative positions of the extremums in the one cycle; a digital image signal input by the input means; A first pattern width modulation signal generated by comparing the digital image signal with the second pattern signal;
Pulse width modulation signal generation means for selectively outputting a second pulse width modulation signal generated by comparing the pattern signal with the first pattern signal, and wherein the first pulse width modulation signal generation means generates the first pulse width modulation signal. The image processing apparatus according to claim 1, wherein the pulse width modulation signal and the second pulse width modulation signal are different from each other in a generation start position of the pulse width modulation signal in the one cycle.