JPH0795806B2 - Image processing device - Google Patents

Description

The present invention relates to an image processing apparatus for inputting image information and outputting it as binary image information by pulse width modulation.

[Prior Art] Conventionally, a method of reproducing a halftone image using a dither method or a density pattern method is known. However, in any case, using a small size threshold matrix,
Sufficient gradation cannot be obtained. For this reason, if an attempt is made to express gradation using a large threshold matrix,
There was a problem that the resolution was extremely reduced.

On the other hand, in addition to this, the applicant of the present invention has proposed a new method of expressing gradation with a relatively simple device configuration while maintaining high resolution. The technique is to convert the input digital image signal into an analog signal and convert the digital image signal into an analog signal in order to obtain halftone gradation when the image is formed by a laser beam printer or the like by binarizing the digital image signal. By comparing the signal with a periodic pattern signal such as a triangular wave, a binary signal subjected to pulse width modulation is generated.

FIG. 2 shows an example of a block diagram of a circuit for realizing this method.

The digital image input signal is latched by the latch circuit 1 in synchronization with the video clock 11. This video clock 11
It is a clock obtained by dividing the master clock 12 by two by the JK flip flop 4. The master clock 12 is assumed to be synchronized with the horizontal synchronizing signal 13 in advance. Here, the horizontal synchronizing signal 13 may be generated internally or may be given from the outside. Further, if this apparatus is applied to a laser beam printer, it may be, for example, a well-known beam detect (BD) signal. The digital image signal of the latch circuit 1 is converted into an analog image signal by the D / A converter 2 and input to one input terminal of the comparator 3. On the other hand, the master clock 12 is frequency-divided into a predetermined cycle by the frequency divider 5 and the cycle switching signal.
-K flip flop divided by 2 with a duty ratio of 50
% Clock signal 14. The ratio of the cycles of the clock signal 14 and the video clock 11 corresponds to the frequency division ratio of the frequency divider 5. Further, the frequency divider 5 uses the horizontal synchronization signal 13 described above.
And the frequency division ratio is loaded by the OR signal of the ripple carry out (RCO) signal of the frequency divider 5, the image signal 15 and the clock signal 14 are completely synchronized for each line. There is. The clock signal 14 is input to the pulse pattern generator 10 through the buffer 9 and converted into a triangular wave, and at the same time, the image signal 15 is matched with the dynamic range. The pulse pattern generator 10 is composed of a well-known integrating circuit composed of, for example, a resistor and a capacitor, a buffer amplifier for adjusting the dynamic range, and the like. Then, the triangular wave pattern signal output from the pulse pattern generator 10 is input to the other input terminal of the comparator 3 and compared with the analog image signal 15, and the pulse width modulation of the image signal 15 is performed.

Here, depending on the image tone of the image, that is, whether the resolution is more important than the halftone like the character image or the reproducibility of the halftone is more important like the photographic image, the cycle input to the frequency divider 5 The switching signal is switched so that the cycle of the clock signal 14 is set to the same cycle as the video clock 11 when the resolution is emphasized, or 2 to 4 times the cycle of the video clock 11 when the halftone reproducibility is emphasized. Has been switched to.

[Problems to be Solved by the Invention] In the apparatus using the above method, as a result of examination by the applicant of the present application, as a result of the applicant having a high resolution such as a character image, or a delicate gradation property such as a silver halide photograph. With regard to the document requiring the above, a high-resolution image that is several steps superior to the image obtained by the conventional binary processing or dither method was obtained. On the other hand, when an image having a periodicity in a specific direction such as a halftone image is used as a document, it has been found that the so-called moire phenomenon, which is a big problem in the conventional binary processing and dither method, is also significantly reduced. It was also clear that it may be conspicuous under some conditions. This condition is a case where the periodicity of the output image is emphasized. For example, in order to emphasize the reproducibility of the halftone, the period of the clock signal is set to be twice the video clock or more. This is the case, and as another example, in an image in which resolution is important, a well-known edge enhancement process or the like is performed in order to make fine lines particularly sharp.

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide an image processing apparatus capable of obtaining a high-quality reproduced image.

[Means for Solving Problems] In order to achieve the above object, the image processing apparatus of the present invention has the following configuration. That is, an image processing apparatus for an apparatus that forms an image by performing line scanning on a recording medium, wherein input means for inputting an image signal and characteristics of the image signal input by the input means are converted, A conversion unit capable of selecting conversion characteristics; a pulse width modulation signal generation unit for generating a pulse width modulation signal which is pulse width modulated according to a pattern signal of a predetermined cycle of the image signal converted by the conversion unit; and the pattern signal And a selecting means for selecting the cycle of.

[Operation] In the configuration described above, the conversion unit can convert the characteristics of the input image signal and select the conversion characteristic. The conversion unit converts the image signal converted by the conversion unit according to a pattern signal of a predetermined cycle. A pulse width modulated signal that is pulse width modulated is generated. At this time, when the cycle of the pattern signal is selected by the selecting means, with the selection of the cycle of the pattern signal,
The conversion characteristic of the image signal in the conversion means is selected.

[Embodiment] The image processing apparatus of the embodiment shown in FIG.
A converter 24, a delay signal generating circuit 16 of setting means, a select signal output device 19 of switching means and an analog switch 17,
Frequency divider 5 and JK flip-flop 4 of the cycle setting means
And 8 are provided.

In the configuration shown in FIG. 1, the delay signal generation circuit 16 outputs the delay signal 18 having a plurality of different delay times which are the horizontal synchronization signals 13 delayed by a preset time. The select signal output device 19 switches the select signal 20 according to the input of the horizontal synchronizing signal 13 according to a preset mode.
The analog switch 17 corresponds to this select signal 20,
One of the delay signals 18 is selected and output. On the other hand, the frequency divider 5 determines the frequency division ratio of the master clock 12, outputs a signal in accordance with the frequency division ratio in synchronization with the output of the analog switch 17, and outputs it to the pulse pattern generator 10 through the JK flip-flop 8. input. The pulse pattern generator 10 outputs a pattern signal 23 having the same cycle as the input signal to the comparator 3. On the other hand, the image signal is subjected to gunma conversion by the D / D converter 24, and its output value is latched by the latch circuit 1 and converted by the D / A converter 2 into an analog signal. The comparator 3 compares the analog image signal 15 with the pattern signal 23 to perform pulse width modulation (PWM), and 2
The value signal 26 is output.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of Pulse Width Modulation Circuit (FIG. 1)] FIG. 1 is a block diagram of the pulse width modulation circuit of the image processing apparatus showing the embodiment of the present invention. Here, the same parts as those in FIG. 2 are indicated by the same symbols. Since the description of these same parts is the same as that described above, the description thereof is omitted.

Reference numeral 16 is a delay signal generation circuit which inputs a horizontal synchronizing signal and outputs a plurality (m) of output signals obtained by applying a plurality of different delays to the horizontal synchronizing signal. The delay signal generation circuit 16 is a master clock.
Since 12 is input, the delay time can be an integral multiple of the master clock 12 or (integer + α) multiple (0 <α <1). Reference numeral 17 is an analog switch for selecting one of the m delay signals 18 output from the delay signal generating circuit 16. The selection instruction in the analog switch 17 is the selection signal 20 from the selection signal output device 19.
Done by. The select signal output device 19 counts the horizontal synchronizing signal 13 and determines the select signal 20 according to the count value according to the mode set by the image writing signal. There are n types of select signals 20 (n
≤m) code or signal level, horizontal sync signal
It is switched sequentially in synchronization with 13. Reference numeral 24 denotes a D / D converter for adjusting the gradation of the digital image signal, which has, for example, a plurality of gamma conversion tables, and one gamma conversion table is selected by the image read signal or the cycle switching signal. It is becoming like this.

Now, the delay signal generation circuit 16 is set so that two signals, that is, a signal a having a delay zero, that is, a timing equal to the horizontal synchronizing signal 13, and a signal b having a delay amount of three pulses of the master clock 12 are generated. The select signal output device 19 is set to output the select signal 20 to the analog switch 17 so that the signal a and the signal b are alternately selected each time the horizontal synchronizing signal 13 is input. Next, the master clock 12 is set to be divided into 3 by the frequency divider 5 by the synchronization switching signal.

[Description of Timing (FIG. 3)] FIG. 3 shows the timing of each signal under the above settings.

In FIG. 3, signals a and b are output signals having different delay times from the delay signal generating circuit 16 described above, and signal b rises at a timing T ₁ which is delayed from the rising edge of signal a by three master clock pulses. . The output signal of the frequency divider 5 which divides the master clock 12 by 3 is further divided by 2 by the JK flip-flop 8 to become a signal with a duty ratio of 50%. The clock signal 22 which is the output of the JK flip-flop 8 when the signal a is selected is the clock a '.
The clock signal 22 when the signal b is selected is indicated by a clock b '. Clock a 'is the falling edge of the signal a (fall of the horizontal synchronizing signal 13) (Tanmingu T _2), clock b' is raised each falling on the falling edge of signal b (timing T _3), then the horizontal synchronizing signal 13 Until is input, it will continue to be output as a square wave with a duty of 50% in a cycle of 6 cycles of the master clock 12.

The video clock 11 output from the JK flip-flop 4 is a clock obtained by dividing the master clock 12 by two as shown in the figure. The clock is reset by the horizontal synchronizing signal 13 and the horizontal synchronizing signal 13 falls at timing T ₂ and the master clock 12 falls. 12
Rises to HIGH, and thereafter, until the horizontal synchronizing signal 13 is input, it is output as a clock signal having the above-mentioned cycle. D / in sync with this video clock 11
The A converter 2 outputs an analog image signal 15 as shown in FIG. 3, for example. Here, T ₀ is a non-image area from the generation of the horizontal synchronizing signal 13 to the actual drawing.

Also, the pulse pattern generator 10 when the signal a is selected
Pattern signal 23 (23-1) of the triangular wave which is the output of and the pattern signal 23 (23-2) of the triangular wave when the signal b is selected.
Are also shown, and the corresponding waveforms of the binary signal 26 are also shown.

As described above, the select signal from the select signal output device 19
A reference numeral 20 designates a signal a and a signal b from the delay signal generation circuit 16 by switching the analog switch 17 for each horizontal line.
Since the and are alternately output, the pattern signal 23 changes line by line like triangular waves 23-1 and 23-2 in FIG. Therefore, when the analog image signal 15 has a waveform as shown in FIG. 3 for two consecutive lines, the binary signal output from the comparator 3
26 is the output signal 30, 31 for each of the triangular waves 23-1 and 23-2.
It becomes like.

[Explanation on Pixel Growth (FIGS. 4 (a), (b), 5
FIGS. 4 (a) and 4 (b))] FIGS. 4 (a) and 4 (b) show how the pixels grow when the above operation is performed.

FIG. 4 (a) is a diagram showing the growth of the pixel when the circuit of FIG. 2 is used, and FIG. 4 (b) is an example of the reproduced pixel when the circuit of FIG. 1 of this embodiment is used. And is as described above. Since the period of the pattern signal 23 is three times that of the video clock, each pixel grows around the shaded portion near the center of each of the three pixels.

Here, in the case of FIG. 4 (a), it can be seen that a strong correlation appears as a line at a 3-dot interval in the vertical direction. On the other hand, in FIG. 4 (b), the correlation in the vertical direction is weakened, and a weak correlation newly appears in the diagonal direction.
It can be seen that the strong correlation disappears as a whole.

In order to check the degree of moire when a dot image is reproduced by a laser beam printer, an image reader and laser beam printer with a resolution of 400 dots / inch (1 inch = 2.54 cm) were actually used, and the most was reported in newspapers and public notices. I read the image of a halftone dot original of 75 lines used with an image reader and played it back with a laser beam printer. As a result, when the circuit shown in FIG. 2 was used, line-shaped moire was generated at an interval of about 15 dots in the sub-scanning direction. However, when the circuit shown in FIG. It was a level with almost no problems above.

The moire described above is considered to be caused by a beating phenomenon due to the synchronization between the halftone image and the output pixel. To confirm this, the output level of the comparator 3 is used in FIG. 5 (a) (b). The results obtained by simulating the above are shown below. In the figure, each circle represents one dot of a halftone dot original of 75 lines, and each square represents one pixel represented by a resolution of 400 dpi.

FIG. 5 (a) shows the output level of the comparator 3 when it is processed by the circuit having the configuration shown in FIG. 2, and is referred to as the first and fourth columns in the main scanning direction. In this manner, every 4th row, dots that are wider than other dots appear. Therefore, moire occurs at this dot interval. On the other hand, in FIG. 5 (b) to which this embodiment is applied, it can be seen that the dots in each row in the main scanning direction have almost the same size, and there is almost no correlation between the dots.

[Description of Other Pixel Growth Example (FIGS. 6A to 6C)] In FIGS. 6A to 6C, the generation timing of the pattern signal 23 is changed from that in FIG. 4B. It is a figure which shows an example of the pixel growth in the case.

Compared to FIG. 4A, the growth centers of the pixels shown by the diagonal lines are dispersed and the moire is reduced. However, in FIG. 6 (b), although the correlation in the sub-scanning direction disappears, the line appears diagonally from the upper left to the lower right, although this is somewhat weakened, and this is the cause. Moire occurs. Therefore, in FIGS. 6A to 6C, the sixth
Moire is more likely to occur in the shape of FIG. 6A or 6C than in the shape of FIG.

In this embodiment, the shift amount of the pattern signal 23 in the main scanning direction is described as an integral multiple of the master clock 12, but this is (integer + α) multiple (0 <α <
Of course, 1) is also acceptable. Also, in the above description, the case of shifting in the sub-scanning direction is also explained by taking as an example the case of returning to the original every 2 to 4 line cycles of the main scanning, but the cycle itself may take any larger cycle. Of course, you can do that.

[Description of Other Embodiments (FIG. 1) (FIG. 7)] In the above-described embodiments, the period of the pattern signal 23 is set to three times that of the video clock 11 in order to emphasize the reproducibility of halftones. . On the other hand, when the resolution is emphasized, it has been confirmed that the cycle of the pattern signal 23 should be made equal to that of the video clock 11. Even if a halftone image is reproduced in this manner, moire hardly occurs, but, for example, the well-known edge emphasizing process or the like may enhance the periodicity, and the moire may become conspicuous. Even in such a case, it is possible to make the moire inconspicuous as in the above-mentioned embodiment.

As a specific example, the delay signal generating circuit 16 of FIG. 1 is configured to generate a signal a of zero delay and a signal c of which the delay amount is one cycle of the master clock 12 as in the above-described embodiment. Make settings. In addition, the select signal output device 19,
Each time the horizontal synchronizing signal 13 is input, the symbol a and the signal c are alternately selected. As a result, the analog switch 17 alternately outputs the signal a and the signal c for each scanning line. The division cycle 5 is set to a null state in which the master clock 12 is not divided by the cycle switching signal.

FIG. 7 shows the pixels of the output image output by the circuit of FIG. 1 set as described above. In this figure, the pixels of each output image grow centering on the hatched portion.

Of course, even in this case, the shift amount (main scanning direction) of the pattern signal is not set to be 1 time that of the master clock 12,
Of course, it may be (integer + α) times (0 <α <1). However, if the shift amount is too large, the line drawing or the like becomes conspicuously distorted. Therefore, in the case of an image in which the resolution is important, it is desirable to keep the shift amount within the range of 0 to ± 1 pixel.

As can be seen from FIG. 7, the pattern signals of the first line and the second line are delayed by one cycle of the master clock 12 (that is, 1/2 of the video clock 11), so that the pattern signals of the first line and the second line are delayed.
Each pixel on the line is shifted by 1/2 pixel. In this way, the occurrence of stripes and moire in the sub-scanning direction are suppressed.

In FIG. 1, a random number generator is used instead of the select signal output device 19, a random number is generated as a select signal 20 in synchronization with the horizontal synchronizing signal 13, and the select signal 20 is input to the analog switch 17 to generate the delay signal generating circuit 16 The output signal of may be selected at random.

Furthermore, instead of using the select signal output device 19, the delay amount of the delay signal generating circuit 16 is arbitrarily switched by the horizontal synchronizing signal 13, and the phase of the pattern signal 23 is changed periodically or randomly. Of course, it is also possible to shift.

As described above, according to this embodiment, the pattern signal 23
By adjusting the phase of each of the horizontal lines, it is possible to make the moire phenomenon, which is a problem when reproducing an image having a periodicity such as a halftone dot image, inconspicuous to a level where there is no practical problem. Further, at this time, strong correlation in the vertical direction (sub-scanning direction) disappears from the pixel array of the output image, and as a result, the pixels are dispersed in the image other than the halftone dot, and the image quality is natural.

As described above, according to the present invention, it is possible to select the optimum conversion characteristic for the cycle of the pattern signal used for pulse width modulation and convert the characteristic of the image signal according to the conversion characteristic. There is an effect that a reproduced image of high quality can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a pulse width modulation processing circuit of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram of a previously proposed circuit, and FIG. 3 is a signal of each part of the circuit of this embodiment. Timing charts showing an example of waveforms, FIGS. 4 (a) and 4 (b) are diagrams showing the growth of pixels when the circuits of FIGS. 2 and 1 are used, and FIGS. 5 (a) and 5 (b) are FIGS. 6 (a) to 6 (c) are diagrams showing pixel growth in the case where the generation timing of the pattern signal is changed in the circuit of this embodiment, and FIG. 7 is a diagram showing pixel growth in another embodiment. It is a figure which shows an example. In the figure, 1 ... latch circuit, 2 ... D / A converter, 3 ... comparator, 4,8 ... JK flip-flop, 5 ...
Frequency divider, 10 ... pulse pattern generator, 11 ... video clock, 12 ... master clock, 13 ... horizontal sync signal,
15 …… Analog image signal, 16 …… Delay signal generation circuit, 17
...... Analog switch, 19 ...... Select signal output device, 20
...... Select signal, 23 …… Pattern signal, 24 …… D / D converter, 26 …… Binary signal.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Yukihiro Ozeki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Moto Kato 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Incorporated (72) Inventor Takahiro Inoue 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Hiroshi Sasame 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. ( 56) References JP-A-58-25768 (JP, A) JP-A-60-59859 (JP, A)

Claims (1)

[Claims] 1. An image processing apparatus for an apparatus for forming an image by line-scanning a recording medium, comprising: input means for inputting an image signal; and characteristics of the image signal input by the input means. Then, a conversion unit capable of selecting the conversion characteristic, and a pulse width modulation signal generation unit for generating a pulse width modulation signal which is pulse width modulated in accordance with a pattern signal of a predetermined cycle of the image signal converted by the conversion unit, An image processing apparatus, comprising: a selecting unit that selects a cycle of the pattern signal, wherein the conversion characteristic of the converting unit is selected according to the selection of the cycle of the pattern signal.