JP2003305883A - Imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reproduce an image of high image quality even in a high speed electrophotographic imaging apparatus incapable of using pulse width modulation by controlling collapse of an isolated white dot, blur of an isolated black dot or a thin line, granulaity, and moire. <P>SOLUTION: The imaging apparatus comprises a sampling window section for storing the pixel data of a plurality of scanning lines from an inputted binary image and selecting a part of the pixel data, an LUT section for selecting multiple-valued pixel data corresponding to a remarked binary pixel from the pixel data at the sampling window section, a section for driving a scanning light forming a latent image on a photosensitive body, and a section for converting the multiple-valued pixel data at the LUT section into a driving signal of scanning light. The multiple-valued pixel data at the LUT section is converted into a plurality of pulse width signals by dividing the driving time of one pixel equally and the intensity of scanning light can also be modulated by combining a plurality of pulse width signals. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention records an input binary image by recording black dots having a predetermined area corresponding to black pixels forming an input binary image on a recording medium such as paper. The present invention relates to an image forming apparatus including an electrophotographic image recording unit such as a digital copying machine or a printer for recording.

[0002]

2. Description of the Related Art In an electrophotographic image forming apparatus such as a digital copying machine or a printer, the resolution of a recorded image is 600.
The mainstream is dpi. On the other hand, in an electrophotographic image forming apparatus such as a digital copying machine or a printer which records a binary image, a monochrome image such as a character or a line drawing can be clearly reproduced, but an original image is represented by a multivalued photographic image. As described above, if an image having gradation is simply binarized with a certain threshold value, gradation information is lost and the image quality is significantly deteriorated.

Therefore, a pseudo-halftone process using a dither method or an error diffusion method is generally used as a binarizing method for reproducing the gradation of an image even if a multivalued image such as a photograph is binarized. In an electrophotographic image recording means such as a digital copying machine or a printer, even if the resolution of the recorded image is 600 dpi as shown in FIG. 13A, the black dots actually recorded are as shown in FIG. 13B. 600dp in order to reproduce a black image so that there is no gap between black dots adjacent to
It is recorded in a larger area than the theoretical area of i. Therefore, as shown in FIG. 14A, the isolated white pixels surrounded by the black pixels that are often present in the pseudo halftone expression in the high density portion are actually printed on paper or the like as shown in FIG. 14B. In the recorded state, there is a problem that the surrounding black dots are eroded and crushed. Further, as shown in FIG. 13B, the actually recorded black dots are recorded in a larger area than the theoretical area, so that the adjacent black dots adjacent to each other influence each other to record an image. Therefore, isolated black pixels surrounded by white pixels that often exist in pseudo halftone expression at low density,
For images with low density of black pixels, such as a thin line of 1 pixel width,
The amount of light received from the adjacent pixels is reduced, and as a result, it may be difficult to reproduce the dots recorded on the recording paper or the lines may be faint.

When a multi-valued image is binarized by the error diffusion method, a large number of isolated white pixels and isolated black pixels exist. Therefore, the dither method is often used in the electrophotographic method. When the gradation is reproduced by the dither method, the resolution and the gradation are inversely proportional to each other. When the resolution is increased, the gradation is lowered, and when the gradation is increased, the resolution is decreased. Generally, in a 600 dpi electrophotographic image forming apparatus, a threshold matrix that can reproduce 106 lines and 65 gradations is often adopted.

[0005]

In offset printing, halftone dots are arranged in a uniform shape such as a circle or an ellipse, and the centers of halftone dots are arranged at equal intervals. In the case of darkening, the shape of the halftone dots is maintained and only the size is increased to increase the proportion of black in the whole. The outline of halftone dots does not blur, and
Since the interval between the centers of the shapes does not fluctuate irregularly, high-quality pseudo-halftone can be obtained. On the other hand, in the electrophotographic method, since the halftone dot shape is determined by the threshold matrix, the halftone dot shape is not uniform depending on the gradation, and the center point of the halftone dot shape also changes, so the spatial frequency characteristics of the dot arrangement are low frequency components. And have a pattern that doesn't exist. Also, if you try to enhance the sharpness of dots by using the edge effect to emphasize the outline of halftone dots, a large amount of toner will scatter, blurring the outline of halftone dots, and conversely the sharpness of dots will decrease. Or

As described above, the pseudo-halftone image processing which is not performed in the electrophotographic system is said to have a low gradation reproducibility in the low density portion and the high density portion of the image and to have a strong graininess (graininess). There is a problem.

[0007] In order to solve these problems, a number of publicly reported methods of determining the image attribute in the area of the sampling window and correcting the image using the corresponding correction data have been reported. A method of correcting an image is a method of replacing with a minute black dot smaller than a predetermined image area. As a method of forming a minute black dot smaller than a predetermined area, a method of pulse-width modulating a driving signal of scanning light or a method of intensity-modulating the amount of scanning light has been proposed.

The pulse width modulation method is a method for converting the driving time of one pixel into a plurality of equally divided pulse trains, and it is possible to freely generate minute black dots smaller than a predetermined area by combining pulse trains. Further, it is also excellent in controlling the position where minute black dots are generated. However, a pixel clock (PCLK) having a frequency T times (T is an integer determined by the number of gradations of minute black dots to be expressed) of the image clock (VCLK) that determines the driving time of one pixel is used to In the method of converting the driving time into a pulse train that is equally divided into a plurality of pulses, it is difficult to generate a pixel clock having a T-times frequency synchronized with the scanning light, and a low-speed image forming apparatus for SOHO is mainly used. Although a method of generating a pulse width signal by a method of comparing with a correction data using a triangular waveform generated using a RAMP function or the like as a reference has been proposed, a triangular waveform synchronized with a high-frequency image clock is generated. It is difficult to use, and it is used for medium-speed machines for office. With an industrial high-speed image forming apparatus in which the driving time for one pixel is shortened, it is difficult to use any of the above methods, and it is also difficult to emit or extinguish scanning light in a short divided driving time.

Intensity modulation is a method of modulating the amount of light within one pixel drive time in an analog manner with respect to a digital or analog input value. The latent image formed by the scanning light modulated by the intensity modulation is used. It is easy to be affected by the surrounding image, and it is difficult to freely generate minute black dots smaller than a predetermined area and control the position where they are generated, such as pulse width modulation. However, since a pixel clock having a frequency T times the image clock is not used, it is suitable for a high-speed industrial image forming apparatus.

The present invention has been made in view of the above circumstances, and uses the advantages of pulse width modulation and intensity modulation to compensate for each other's drawbacks to generate minute black dots smaller than a predetermined recording area. To faithfully reproduce the gradation of a pseudo-halftone image included in an image to be recorded, prevent the characters and line drawings from being crushed or blurred, and provide an image forming apparatus capable of recording an image with a quality close to that of the original image. The purpose is to

[0011]

In order to achieve the above object, an image forming apparatus according to a first aspect of the present invention stores pixel data of a plurality of scanning lines from an input binary image, and a part of the pixel data. Sampling window part to select
LU for selecting multivalued pixel data corresponding to a binary pixel of interest from the pixel data of the sampling window section
A T unit, a scanning light drive unit that drives scanning light that forms a latent image on a photoconductor, and a data conversion unit that converts multivalued pixel data of the LUT unit into a driving signal of the scanning light are provided. , So that the intensity of scanning light can be modulated by modulating multi-valued pixel data of the LUT unit into a plurality of pulse width signals obtained by equally dividing the driving time of one pixel into a plurality of pulse width signals. It is characterized by having done.

An image forming apparatus according to a second aspect of the present invention is a clock that is synchronized with scanning light and generates a binary image, and is a clock that is input to the sampling window unit and the LUT unit to select pixel data. And a pixel clock that is a clock that is synchronized with the scanning light and that is a clock that is input to the data conversion unit and that generates a driving signal of the scanning light. The frequency of the pixel clock and the image clock The frequency ratio of is a natural number.

In the image forming apparatus according to the present invention, when the frequency ratio of the pixel clock and the image clock is 1, the data conversion unit counts 1 at the rising edge of the pixel clock. Bit first counter circuit, 1-bit second counter circuit that counts at the falling edge of the pixel clock, and multi-valued data corresponding to the input binary image to the first counter circuit and the second counter circuit. It has a plurality of pulse width modulation circuits for converting into serial signals at the output timing of the counter circuit.

According to another aspect of the image forming apparatus of the present invention, when the ratio of the frequency of the pixel clock and the frequency of the image clock is other than 1, the LU in the data conversion unit is set.
A D-type register having a plurality of bits for synchronizing the pixel data from the T section with the pixel clock, a first counter circuit of at least 1 bit counting at a rising edge of the pixel clock, and a rising edge of the pixel clock. At least 1 to count on falling edges
A second counter circuit of more than 1 bit and a plurality of pulse width modulation circuits for converting multi-valued data corresponding to an input binary image into a serial signal at the output timing of the first counter circuit and the second counter circuit. It is characterized by having.

[0015]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
Embodiments of the present invention will be described in detail.

First, FIG. 1 shows a block configuration when it is applied to a printer engine 100 of an image forming apparatus according to an embodiment of the present invention. In FIG. 1, a printer engine 100 constitutes a laser beam printer which is one of image forming apparatuses not shown together with a controller not shown. The controller mainly includes a host interface unit and a RIP unit (Raster Image Pr).
processor) and a frame memory unit.
The controller receives print data from a host computer such as a personal computer in the host interface unit, converts it into raster data in the RIP unit, and temporarily records it in the frame memory unit.

A photographic image, which is a multi-valued image, is converted into binary data by a host computer and sent to the controller as print data, and a multi-valued image is sent to the controller as print data as it is and sent to the controller as a threshold matrix. In some cases, it is converted into binary data by using a binary conversion method represented by. A binary image such as a photograph temporarily recorded in the frame memory unit is sent to the printer engine 100.

In the printer engine 100, the binary image output from the controller in synchronization with the image clock VCLK is input to the sampling window unit 200,
Pre-processing for generally well-known pattern matching processing is performed. That is, all the pixel data of a plurality of scanning lines are temporarily stored in the input binary image, one pixel of each of the constituent pixels is sequentially selected as a target pixel, and the selected binary pixel and the peripheral pixels of the target pixel are sent to the LUT unit 300.

The sampling window unit 200 has a line buffer memory (not shown) for temporarily recording image data for a total of m (m is an odd integer) scanning lines before and after the pixel of interest is centered, and m scanning lines. An m-stage shift register group (not shown) for sequentially feeding the image data is provided, and the m × m pixel data around the target pixel is set as a reference area, and the m × m pixel data is stored in the LUT unit (Look).
up table) 300. The line buffer memory and the shift register group operate in synchronization with the image clock VCLK from the controller.

The LUT unit 300 converts the ROM (or RAM) (not shown) for recording pixel data and the input image data into the address of the ROM (or RAM) in which the pixel data corresponding to the image data is recorded. If the pattern configuration of the designated black pixel and the white pixel of the input image data matches, the pixel data defined in the pattern configuration is selected. The LUT unit 300 of the present invention includes an address conversion circuit (not shown) that logically operates m × m pixel data from the sampling window unit 200.
A pattern matching process is performed to obtain reference data corresponding to the constituent patterns of black pixels and white pixels in the reference area from the result of logically operating the data of × m pixels. LUT unit 30
The pixel data output from 0 is the pixel data conversion unit 40.
Input to 0.

The pixel data conversion unit 400 includes a LUT unit 30.
The multivalued pixel data output from 0 is converted into a plurality of drive signals in accordance with the input specifications of the scanning light drive unit 500, and the drive time of one pixel is converted into a pulse train equally divided into a plurality of pulses.

FIG. 2 shows a first embodiment of the present invention, which is a data conversion circuit in which the image clock VCLK and the pixel clock PCLK are the same clock. Reference numerals 401, 402, and 403 denote 2-bit parallel-serial conversion circuits, which are the output C0 of the 1-bit first counter circuit 404 that counts at the rising edge of the clock and the 1-bit second counter circuit 405 that counts at the falling edge of the clock. The output C1 is connected to the output S obtained as the input of the exclusive-or circuit 406, and is connected to a selector of two inputs and one output composed of the And circuits of 408 and 409 and the Or circuit of 410, and the output of the Exclusive-or circuit is connected. When S is'H ', the selector output In0 is the input Q1 of the selector, and when output S is'L', the selector output In0 is the input Q0.

2-bit parallel-serial conversion circuit 4
In 01, 402, and 403, since the image clock VCLK and the pixel clock PCLK are the same clock, the left shift 50 is performed using the rising and falling edges of the clock.
%, Right shift 50% and total 100% can be expressed in three levels.

FIG. 3 is a waveform diagram for explaining the operation of the data conversion circuit 400 of the first embodiment. For example, the input specifications of the scanning light drive unit require three digital signals in order to express three levels of weak exposure, medium exposure, and strong exposure, and each drive signal makes the drive time of one pixel 2 or the like. If converted into a divided pulse train, 6 bits of pixel data output from the LUT unit 400 is required.

6 bits from the LUT unit 300 (bit5
~ Bit0) The pixel data is 2 bits at a time (D5, D
4), (D3, D2), and (D1, D0) in combination, the three input signals In2, In of the scanning optical drive unit are input.
It corresponds to 1, In0. The image clock VCLK and the pixel clock PCLK are clocks that are synchronized with the scanning light in the same cycle, and thus are almost the same, and the LUT unit 30 is used.
Pixel data output from 0 in synchronization with the image clock VCLK is in phase with and synchronized with the pixel clock PCLK. If the image clock VCLK and the pixel clock PCLK are out of phase, the pixel data must be synchronized with the pixel clock.
Unless special circumstances exist, clocks that have the same frequency and are out of phase are rarely used in circuits, so they are ignored here. 1-bit first counter circuit 40 that counts at the rising edge of the pixel clock PCLK
The output C0 of No. 4 alternately outputs "H" and "L" for each cycle.

The output C1 of the 1-bit second counter circuit 405 which counts at the falling edge of the pixel clock PCLK is the output C1 of the first counter circuit 404.
After being delayed by a half cycle to 0, 'H'and'L'are alternately output every cycle. Therefore, the output S0 of the exclusive-or circuit 406, to which the output C0 of the first counter circuit 404 and the output C1 of the second counter circuit 405 are input, alternately outputs'H 'and'L' every half cycle. is doing. Exc
The parallel-serial conversion circuit 401 receives the pixel clock P from the output S of the positive-or circuit 406.
D1 and D0 are alternately output every half cycle of CLK. Similarly, the parallel-serial conversion circuit 402 alternately outputs D3 and D2 every half cycle of the pixel clock PCLK. Similarly, the parallel-serial conversion circuit 403 also outputs D5 and D4 every half cycle of the pixel clock PCLK.
Are output alternately.

FIG. 9 is a conceptual diagram of a waveform diagram showing the relationship between the pixel data input from the data conversion circuit of the first embodiment, the light intensity of scanning light, and the driving time. The waveform diagram represents the light intensity of the scanning light with the height in the vertical direction. The light intensity increases from the bottom in the order of weak exposure, medium exposure, and strong exposure. The total length in the horizontal direction represents the driving time of one pixel. The left end in the horizontal direction represents drive time 0%, the middle point represents 50%, and the right end represents 100%. When represented by pulse width modulation 2 bits and intensity modulation 3 levels, typical combinations including off are shown.

FIG. 10 is a conceptual diagram of the spot light of the scanning light for the typical combination shown in FIG.
The relationship between the pixel data input from the LUT unit 300, the light intensity of scanning light, and the driving time is shown. The size of the circle represents the relative light intensity. The larger the circle, the stronger the light intensity, and the smaller the circle, the weaker the light intensity. The total length in the horizontal direction represents the driving time of one pixel. If the center of the circle is near the midpoint in the horizontal direction, the driving time is 100%, and if it is between the left end and the midpoint or between the midpoint and the right end, 50% is indicated.

FIG. 4 shows a second embodiment in which the pixel clock PCLK is synchronized with the scanning light like the image clock VCLK, and the frequency of the pixel clock PCLK is twice the image clock VCLK. Circuit. The pixel clock PCLK can be expressed in 4 bits of 25%, 50%, 75% and 100% as a whole by using two rising edges and two falling edges of the pixel clock PCLK within one cycle of the image clock VCLK.

For example, in order for the input specifications of the scanning light drive unit to express three levels of weak exposure, medium exposure and strong exposure, three digital signals are required and each drive signal requires a drive time of one pixel. If converted into a pulse train divided into 4 etc., the pixel data output from the LUT unit 400 becomes 12
Bit is required. In the 4-bit parallel-serial conversion circuit 411, the output C0 of the 1-bit first counter circuit 414 that counts at the rising edge of the clock,
The output C1 of the 1-bit second counter circuit 415 which counts at the falling edge of the clock is 418 and 41.
It is connected to a 4-input 1-output selector composed of And circuits of 9 and 420 and 421 and an Or circuit of 422, the output C0 of the first counter circuit 414 is'H ', and the output C1 of the second counter circuit 415 is connected. Is'L ', selector output In
The selector input Q3 is output to 0, and the output C0 is'
When the output C1 is "H" in H ', the input Q2 is output,
Input Q1 when output C0 is'L 'and output C1 is'H'
Is output, and when the output C0 is “L” and the output C1 is “L”, the input Q0 is output when 0 is output. Similarly, the 4-bit parallel-serial conversion circuits 412 and 413 also output pixel data in order.

FIG. 5 shows the data conversion circuit 4 of the second embodiment.
It is a waveform diagram explaining the operation of 00. The 12-bit (bit11 to bit0) pixel data from the LUT unit 300 is 4 bits at a time (D11 to D8) and (D7 to D4).
And (D3 to D0) correspond to the three input signals In2, In1, In0 of the scanning light drive unit. Image clock VCLK and pixel clock PCLK
Is not the same clock, the pixel data output from the LUT unit 300 in synchronization with the image clock VCLK is
It is necessary to synchronize with the pixel clock PCLK, and the serialization is delayed accordingly. The output C0 of the 1-bit first counter circuit 414 that counts at the rising edge of the pixel clock PCLK is'H 'and'L' for each cycle.
Are output alternately.

The output C1 of the 1-bit second counter circuit 415 counting at the falling edge of the pixel clock PCLK is the output C1 of the first counter circuit 414.
After being delayed by a half cycle to 0, 'H'and'L'are alternately output every cycle. Therefore, the parallel-serial conversion circuit 411, to which the output C0 of the first counter circuit 414 and the output C1 of the second counter circuit 415 are input, sequentially sets D3, D2, D1, and D0 for each half cycle of the pixel clock PCLK. Repeatedly output to. Parallel-serial conversion circuit 4
Similarly, 12 also repeatedly outputs D7, D6, D5, and D4 in order every half cycle of the pixel clock PCLK. Similarly, the parallel-serial conversion circuit 413 also has D11, D10, D9, and D for each half cycle of the pixel clock PCLK.
8 is repeatedly output in order.

FIG. 11 is a conceptual diagram of a waveform diagram showing the relationship between the pixel data input from the data conversion circuit of the second embodiment, the light intensity of scanning light, and the driving time. The waveform diagram represents the light intensity of the scanning light with the height in the vertical direction. The light intensity increases from the bottom in the order of weak exposure, medium exposure, and strong exposure. The total length in the horizontal direction represents the driving time of one pixel. Driving time is 0%, 25% at the left end of the horizontal direction, 50% at the midpoint, 75
%, The right end represents 100%. Pulse width modulation 4bi
When expressed in terms of t and 3 levels of intensity modulation, 43 or more combinations including off can be expressed.

FIG. 12 is a conceptual diagram of the spot light of the scanning light, which is a typical combination represented by the pulse width modulation 4 bits and the intensity modulation 3 levels shown in FIG. The relationship between the pixel data input from the data conversion circuit, the light intensity of the scanning light, and the driving time is shown. The size of the circle represents the relative light intensity. The larger the circle, the stronger the light intensity, and the smaller the circle, the weaker the light intensity. The total length in the horizontal direction represents the driving time of one pixel. If the center of the circle is near the midpoint in the horizontal direction, the driving time is 100%, if it is between the left end and the midpoint or between the midpoint and the right end, 50%, and the initial value is 25%.

FIG. 6 shows a data conversion circuit of the third embodiment. In the embodiment of FIG. 6, the pixel clock PCLK is synchronized with the scanning light similarly to the image clock VCLK, and the frequency of the pixel clock PCLK is the image clock VCLK.
It is a data conversion circuit using a clock that is four times as large as

8-bit parallel-serial conversion circuit 4
Since the frequency of the pixel clock PCLK is four times the frequency of the image clock VCLK, the reference numerals 31, 432 and 433 indicate the pixel clock PC within one cycle of the image clock VCLK.
12.5%, 25%, 37.5%, 50%, 62.5 using LK's four rising edges and four falling edges
%, 75%, 87.5% and 100% overall 8 bits
Can be expressed in

FIG. 7 shows a data conversion circuit 4 of the third embodiment.
It is a waveform diagram explaining the operation of 00. Image clock VC
Since LK and the pixel clock PCLK are not the same clock, the pixel data output from the LUT unit 300 in synchronization with the image clock VCLK is set to the pixel clock PC.
It is necessary to synchronize with LK, which delays serialization. Output A of the 2-bit first counter circuit 434 that counts at the rising edge of the pixel clock PCLK
C0 alternately outputs "H" and "L" every cycle.
Further, the output AC1 alternately outputs “H” and “L” every two cycles. A 2-bit second counter circuit 435 that counts at the falling edge of the pixel clock PCLK
Output BC0 is the output AC0 of the first counter circuit 414.
Then, "H" and "L" are alternately output for each cycle with a half cycle delay. Also, the output BC1 is'H 'and'L' every two cycles.
Are output alternately.

Therefore, the outputs AC0 and AC1 of the first counter circuit 434 and the output BC of the second counter circuit 435 are output.
The parallel-serial conversion circuit 431 to which 0 and BC1 are input is D7 every half cycle of the pixel clock PCLK.
To D0 are sequentially and repeatedly output. Similarly, the parallel-serial conversion circuit 432 also has the pixel clock PCLK.
D15 to D8 are sequentially and repeatedly output every half cycle. Similarly, the parallel-serial conversion circuit 433 repeatedly and sequentially outputs D23 to D16 every half cycle of the pixel clock PCLK.

FIG. 8 is a truth table of the 8-bit input selector used in the third embodiment. Select terminal S3 ~
The input terminals I7 to I0 are output terminals OU depending on the condition of S0.
Reflected in T.

FIG. 13 is a diagram showing the relationship between an input image of isolated black dots and an output image recorded with a predetermined recording area, which is a conventional technique, and FIG. 14 shows isolated white dots. FIG. 6 is a diagram showing a relationship between the input image of FIG. 4 and an output image of which the input image is recorded in a predetermined recording area which is a conventional technique. FIG. 13A is an image of input data of isolated black dots in a white image. On the other hand, since the actual scanning light does not have a solid black color spot,
It is larger than the size of 1 dot for (b). vice versa,
Even if the input shown in FIG.
As shown in FIG. 4B, the white dots cannot be reproduced because they are eroded and crushed by the surrounding scanning light.

FIG. 15 shows the relationship between an input image of isolated black dots and an output image corrected and recorded using the present invention by adding small small black dots to white pixels adjacent to the isolated black dots from the input image. FIG. Further, FIG. 16 shows that an input image of isolated white dots and black pixels adjacent to the isolated white dot from the input image are replaced with small minute black dots by using the present invention from a predetermined recording area which is a conventional technique. It is a figure which shows the relationship with the output image which carried out correction recording. According to the present invention, as shown in FIG. 15B, an isolated black dot can be reproduced by replacing a white dot which is not recorded in the input image with a minute black dot which is smaller than a black dot which is recorded in a predetermined area. Further, as shown in FIG. 16B, an isolated white dot can be reproduced by replacing a black dot recorded in a predetermined area in an input image with a minute black dot smaller than a black dot recorded in a predetermined area.

FIG. 17 is a truth table showing the relationship between the three input signals of the scanning light drive section and the output light intensity. 7 is a truth table of a semiconductor laser driver IC (EL6257 manufactured by Elantec, USA) which is a typical scanning light.

[0043]

According to the present invention, image processing for improving print quality can be performed even in a high-speed image forming apparatus for industrial use by crushing isolated white dots, blurring of isolated black dots or fine lines, graininess, and moire. Can be suppressed and high quality images can be reproduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a block configuration of a printer engine of an image forming apparatus that is an embodiment of the present invention.

FIG. 2 is a data conversion circuit according to the first embodiment of the present invention.

FIG. 3 is a waveform diagram illustrating the operation of the data conversion circuit according to the first embodiment of the present invention.

FIG. 4 is a data conversion circuit according to a second embodiment of the present invention.

FIG. 5 is a waveform diagram illustrating the operation of the data conversion circuit according to the second embodiment of the present invention.

FIG. 6 is a data conversion circuit according to a third embodiment of the present invention.

FIG. 7 is a waveform diagram illustrating an operation of the data conversion circuit according to the third embodiment of the present invention.

FIG. 8 is a truth table of an 8-bit input selector used in the third embodiment of the present invention.

FIG. 9 is a conceptual diagram of a waveform diagram showing the relationship between the light intensity of the laser output from the data conversion circuit according to the first embodiment of the present invention and the driving time.

FIG. 10 is a conceptual diagram of laser spot light showing the relationship between the light intensity of the laser output from the data conversion circuit according to the first embodiment of the present invention and the driving time.

FIG. 11 is a conceptual diagram of a waveform diagram showing the relationship between the light intensity of the laser output from the data conversion circuit of the second embodiment of the present invention and the drive time.

FIG. 12 is a conceptual diagram of laser spot light showing the relationship between the light intensity of the laser output from the data conversion circuit of the second embodiment of the present invention and the driving time.

FIG. 13 is a diagram showing a relationship between an input image of isolated black dots and an output image recorded with a predetermined recording area which is a conventional technique.

FIG. 14 is a diagram showing a relationship between an input image of isolated white dots and an output image recorded with a predetermined recording area, which is a conventional technique.

FIG. 15 is a diagram showing a relationship between an input image of isolated black dots and an output image corrected and recorded by adding small small black dots to white pixels adjacent to the isolated black dot from the input image using the present invention. Is.

FIG. 16: Correction recording by replacing an input image of isolated white dots and black pixels adjacent to the isolated white dot from the input image with small minute black dots by using the present invention from a predetermined recording area which is a conventional technique It is a figure which shows the relationship with the output image which did.

FIG. 17 is a diagram showing a relationship between three input signals and an output light intensity of the scanning light drive unit.

[Explanation of symbols]

100 ... Printer engine, 200 ... Sampling window section, 300 ... LUT section, 400 ... Data conversion section, 401, 402, 403 ... Parallel-serial conversion circuit, 404, 405 ... 1-bit counter circuit, 406
... Exclusive-or circuit, 407 ... 2-bit D
Type flip-flop circuits, 408, 409 ... And circuits, 410 ... or circuits, 411, 412, 413 ... Parallel-serial conversion circuits, 414, 415 ... 1-bit counter circuits, 416 ... 4-bit D-type flip-flop circuits, 417 ... 4-bit D-type flip-flop circuit with enable terminal, 418, 419, 420, 421 ... And
Circuits, 422 ... Or circuits, 431, 432, 433 ... Parallel-serial conversion circuits, 434, 435 ... 2-bit counter circuits, 436 ... 8-bit D-type flip-flop circuits, 437 ... 8-bit D-type flip-flop circuits with enable terminals Or 438 ... Or circuit, 439 ... 8-bit input selector circuit, 500 ... Scanning light drive unit.

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI Theme Coat (Reference) H04N 1/405 F Term (Reference) 2C362 CA06 CA11 CB03 CB12 CB37 2H076 AB02 AB75 DA05 5B057 AA11 CA08 CA12 CA16 CB07 CB12 CB16 CC01 CE13 CH07 CH08 5C051 AA02 CA07 DB02 DB07 DB30 DC03 DE05 DE29 FA01 5C077 LL03 MP01 NN17 PP68 PQ08 PQ12 PQ23 TT02 TT03

Claims (4)

[Claims] 1. A sampling window unit for storing pixel data of a plurality of scanning lines from an input binary image and selecting one portion of the pixel data, and a binary pixel of interest from the pixel data of the sampling window unit. A LUT section for selecting multi-valued pixel data corresponding to, a scanning light drive section for driving scanning light for forming a latent image on a photoconductor, and the LU.
A multi-valued pixel data of the T section and a data conversion section for converting the drive signal of the scanning light, and a plurality of driving times of one pixel are equally divided from the multi-valued pixel data of the LUT section. An image forming apparatus characterized in that it is modulated into a pulse width signal, and the intensity of scanning light can be modulated by combining a plurality of the pulse width signals. 2. A clock for synchronizing with scanning light and generating a binary image, the clock being a clock input to the sampling window unit and the LUT unit for selecting pixel data, and scanning light And a pixel clock, which is a synchronized clock and is a clock that is input to the data conversion unit to generate a driving signal for scanning light, and the ratio of the frequency of the pixel clock to the frequency of the image clock is a natural number. The image forming apparatus according to claim 1, wherein: 3. When the ratio of the frequency between the pixel clock and the image clock is 1, the data conversion unit includes a 1-bit first counter circuit which counts at a rising edge of the pixel clock, A 1-bit second counter circuit that counts at the falling edge of the pixel clock, and multi-value data corresponding to an input binary image is output as a serial signal at the output timing of the first counter circuit and the second counter circuit. 3. The image forming apparatus according to claim 2, further comprising a plurality of pulse width modulation circuits for converting to. 4. When the ratio of the frequency of the pixel clock to the frequency of the image clock is other than 1, the data conversion unit includes a plurality of bits for synchronizing the pixel data from the LUT unit with the pixel clock. Number D-type register, at least one bit or more first counter circuit that counts at the rising edge of the pixel clock, and at least one bit or more second counter circuit that counts at the falling edge of the pixel clock. 3. A plurality of pulse width modulation circuits for converting multi-valued data corresponding to an input binary image into serial signals at the output timings of the first counter circuit and the second counter circuit. Image forming device.