JPH02155760A - Image forming device - Google Patents

Abstract

PURPOSE:To reproduce the sharpness of a contour and the smoothness of a contour and to reproduce a smooth density gradation on a halftone image part by storing input image data, discriminating whether the image data at the periphery of a noted pixel to be interpolated belongs to an image of binary expression or an image of a multilevel expression, and generating the interpolated data of the noted pixel. CONSTITUTION:Image data at a present time and image data at previous time are stored in latch circuits 19 - 22. A full adder 25 adds the content of two continuous image data. 8 more significant bits of total 9 bits of the added result are employed, this added value is set thereby to 1/2, and the average value of two continuous image data is obtained. A selector 26 sequentially outputs image data at previous time, intermediate average value data image data of present time by the control to switch switching terminals 27 - 30. Thus, the image data and the interpolated data are assigned to areas of two dots of 600dpi engine. In this manner, the resolution of its scanning direction becomes 600dpi, and smooth gradation is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus that receives image data of a certain print density and forms an image of a higher print density.

[Prior Art] Figure 11 is a conceptual diagram of a conventional laser beam printer system that prints at a print density of 300 dpi.
In the figure, 154 is a host computer, which has a floppy disk 1 containing various application software.
55, starts the program, and functions, for example, as a video processor. Reference numeral 153 denotes a laser beam printer (image forming device), which prints the image data (characters, figures, photographic images, etc.) formed by the video processor 154 into a visible image.

More specifically about the laser beam printer 153, 152 is a printer controller that generates image page information based on image data sent from the host computer 154. Also, host computer 1
When 54 sends code data such as characters, it may convert it into corresponding dot pattern data to generate page information. A printer engine unit 151 performs printing on a photosensitive drum (not shown) based on page image data sent from the printer controller 152.

Incidentally, in recent years, printer engine units have been designed to have higher printing density and higher gradation in order to perform higher quality printing. For example, the printing density is 600dp.
i and higher printer engines have been announced.

[Problems to be Solved by the Invention] However, conventionally, a printer controller connected to such a high-density printer engine has an amount of data memory corresponding to the high density.

For example, if the printing density is 600dpi, then 300dpi
It has four times as much memory as the case of .

Application software also needs to be created specifically for high-density printers, and many conventional printer application software for low-density printers cannot be used as is.

Figure 12 shows 1 at the conventional printing density of 300 dpi.
FIG. 3 is a diagram showing the relationship between printing position on a line and gradation change.

If such image data is printed as is with a 600dpi engine, the size of the output image will be 1/2 both vertically and horizontally.
Become. Therefore, one conventional data interpolation method is to double the dot structure both vertically and horizontally (Fig. 13).However, although this results in a larger output image, the image quality (gradation smoothness) ) has no change, so
The true potential of the 600dpi engine cannot be demonstrated.

Further, page information at a print density of 300 dpi includes a mixture of halftone images such as photographic images and binary images such as characters and figures. However, this can be solved using Ritsu's algorithm.
Interpolation to image data with a print density of 00 dpi does not provide image quality that matches the characteristics of the image; in other words, halftone images require reproducibility and smoothness of density gradation;
Furthermore, the necessity of reproducing sharpness and smoothness of contours in a binary image is not taken into consideration.

The present invention eliminates the above-mentioned drawbacks of the prior art, and its purpose is to reproduce sharpness and smoothness of contours in binary image parts, and to reproduce density gradation in halftone image parts. An object of the present invention is to provide a high-quality image forming apparatus that enables smooth reproduction of images.

[Means for Solving the Problems] In order to achieve the above object, the image forming apparatus of the present invention has the following features:
In an image forming apparatus that inputs image data of a certain print density and forms an image of a higher print density, the image forming apparatus includes a storage means for storing the input image data, and a storage means for storing the stored image data around a pixel of interest to be interpolated. a discriminating means for discriminating whether the pixel belongs to a value-based image or a multi-valued image; and data interpolation for generating interpolated data of the pixel of interest using a calculation method defined according to the discrimination result of the discriminating means. The outline is to provide the means.

Preferably, the data interpolation means generates interpolated data of the pixel of interest by a binary logical operation when the discrimination result of the discrimination means belongs to an image with a binary expression, and the data interpolation means generates interpolated data of the pixel of interest by a binary logic operation, and the discrimination result belongs to an image with a multi-value expression. One aspect of this is to generate interpolated data for the pixel of interest through numerical calculations.

[Operation] In such a configuration, the storage means stores input image data, and the zero determination means determines whether the stored image data around the pixel of interest to be interpolated belongs to a binary representation image or to a multivalue representation image. Determine whether it belongs. The data interpolation means generates interpolated data of the pixel of interest using a calculation method defined according to the determination result of the determination means. Therefore, for example, even if conventional 300dpi image data is input,
It is possible to print the same size at 600 dp L while maintaining the sharpness and smoothness of the outline in the binary image part, and the smoothness of the density gradation in the halftone image part.

Preferably, the data interpolation means generates interpolated data of the pixel of interest by a binary logical operation when the discrimination result of the discrimination means belongs to an image with a binary expression, and the data interpolation means generates interpolated data of the pixel of interest by a binary logic operation, and the discrimination result belongs to an image with a multi-value expression. At this time, interpolated data of the pixel of interest is generated by numerical calculation. Therefore, interpolation of a binary image becomes extremely simple, and the characteristics of the binary image are not impaired.

[Description of Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block configuration diagram of an image forming apparatus according to an embodiment. In FIG. 0, 52 is a printer controller, which sends out image data for, for example, 300 dpi and 256 gradations. Reference numeral 51 denotes a printer engine section, which includes a data conversion circuit for 600 dpi and 256 gradations of the embodiment.

Incidentally, the data conversion circuit may be provided on the side of the printer controller 52. In the printer engine section 51, 4 is a horizontal synchronization signal generation circuit, and the beam detect signal (
The BD flaw signal is counted, and one horizontal synchronization signal H3YNC (synchronization signal in the main scanning direction) is output every time the BD flaw signal is counted by two. On the other hand, the printer controller 52 receives the horizontal synchronization signal HSYNC and outputs 300 dpi/256 dpi.
The gradation image data VDO (VDOO to VDO7) and the image clock signal VCLK are sent to the printer engine section 51. In the printer engine section 51, the data conversion circuit forms image data for 600 dpi and 256 gradations according to the present invention from the input image data VDO for 300 dpi and 256 gradations and the image clock signal VCLK, and performs printing. Explain in detail.

In the figure, 1 is a frequency multiplier circuit which multiplies the frequency of an input image clock signal VCLK to obtain a clock signal VCLK' having a double frequency.

Reference numeral 5 denotes an oscillation circuit, which generates a clock signal LCLK having a frequency four times that of the image clock signal VCLK. 11-13
is a switching circuit, and the clock signal VCLK' or LCL
K is selected to supply a read/write clock signal to each line memory 6 to 8 (each having a depth of 8 bits). 17
is an interpolation circuit, which forms 600 dpi image data in the main scanning direction by generating and inserting interpolation data between input 300 dpi image data.

A demultiplexer 2 distributes image data interpolated by the interpolation circuit 17 to the line memories 6 to 8. The line memories 6 to 8 each have a memory capacity for one line corresponding to 600 dpi of main scanning.

3 is a device control circuit, which controls each block repeatedly for each line based on the BD double signal. That is, the demultiplexer 2 sequentially distributes the interpolated image data VDO to the line memories 6 to 8, and the switching circuits 11 to 13 write the image data VDO to the line memory selected by the clock signal VCLK'. In addition, image data that has already been written from the other two line memories that are not currently being written is sent to the clock signal LC.
Read by LK. This operation is performed sequentially for each line. For example, when writing data to line memory 6, line memories 7 and 8 perform a data read operation, and in the next line, data write operation to line memory 7 is performed, and line memory 8 and From 6 onwards, a data read operation is performed. Further, in the next line, a data write operation is performed to the line memory 8, and a data read operation is performed from the line memories 6 and 7.

14 and 15 are data selectors, and line memory 6
.about.8 read signals are selected and output. For example, when the line memory 6 is in a write operation and the line memories 7 and 8 are in a read operation, the data selector 14 selects the read data D2 of the line memory 7 and creates a series of image data D.
SL, and the data selector 15 selects the read data D3 of the line memory 8 and outputs a series of image data D.
Output S2. Reference numeral 10 denotes an interpolation circuit, which compares and discriminates or performs numerical calculations on single or plural image data DSI and DS2, and outputs the resulting image (interpolation) data Q. A line memory 9 stores image data Q for one line. A data selector 16 selects any one of the image data D1 to D4 read from the line memories 6 to 9 and outputs it as image data VDO'. Note that the device control circuit 3 also performs read/write control of the line memories 6 to 8 and 9, and selection control of the data selectors 14 to 16. FIG. 2 shows an operation timing chart of the circuit shown in FIG. 1 described above.

FIG. 3 is a block diagram of the interpolation circuit 17 of the embodiment. The interpolation circuit 17 performs data interpolation of image data in the horizontal direction. In the figure, 18° is a flip-flop,
The clock signal VCLK is frequency-divided by 2 and sent to the clock signal station VC.
Output LK. Most significant bit VD of image data VDO
O7 is alternately latched by latches 23 and 24 of the latch circuit 19 by the clock signal station VcLK. Similarly, the remaining bits VD06 to VDOO of the image data are alternately latched into two latches in each of the latch circuits 20 to 22, respectively. Therefore, the current image data and the immediately previous image data are stored in the latch circuits 19-22. 25 is a full adder which adds the contents of two consecutive image data. Then, by taking the upper 8 bits of the total 9 bits of the addition result, the added value is halved, and 2 consecutive
The average value of the image data is determined. Reference numeral 26 denotes a select circuit which sequentially outputs the image data of the previous time, the intermediate average value data, and the image data of the present time by switching control of the switching terminals 27 to 30. As a result, image data and interpolation data are assigned to each 2-bit area of the 600 dpt engine, and the resolution in the main scanning direction is also 600 dpt.
The data for 300 dpi and 256 gradations shown in FIG. 12 is converted into the data for 600 dpi and 256 gradations as shown in FIG.

FIG. 5 is a block diagram of the interpolation circuit 10 of the embodiment. In the figure, image data DSI and DS2 are input to 8-bit, 7-stage shift registers 17 and 18, respectively.

19 is a logic circuit which inputs the contents of the image data A-G stored in the shift register 17 and the image data a-g stored in the shift register 18, and outputs the corresponding 8-bit interpolation data Q.

FIGS. 6A and 6B are diagrams illustrating data interpolation processing in the interpolation circuit 10 of the embodiment.

FIG. 6(A) shows image data ANC and image data B-
-g and the pixel of interest Q to be interpolated. That is, the target pixel Q to be interpolated is located in the middle of the line between the image data A-G and B-g.

FIG. 6(B) shows the logical operation processing and numerical operation processing in the logic circuit 19 in a flow format. It goes without saying that such processing can be configured by hardware. In FIG.
It is checked whether the pixel is O" The process proceeds to step S2, where each of the 8-bit image data A-G and a-'-g is converted into 1-bit binary data A'.
~G' and a'~g. That is, pixels whose image data content is "FF" 8 are converted to logic 1, and pixels whose content is "00" to "FE" □ are converted to logic 0. In step S3, 1-bit interpolated data Q' is generated by interpolation according to the following logical formula.

Q' = ((B'+F')*b'*c'
*d'*e*f' ) + ((b'+f')*B'*C'
*D'*E'*F' ) + (C'10E' ) *c'*d' *e+ (c
'10e')*C'*D'*E'+D'*d' + (A'*B'*C'*D' *E
'*F'*G' ) + (a *b'IC*d' *e
*f'*g) Here, +: logical sum *: logical product At step S4, binary interpolated data Q' is inversely converted to multi-valued interpolated data Q. That is, when Q' is logic 1, multi-value interpolation data Q = "FF"H, and when it is logic O, Q = "00"H.
shall be. In step S6, multilevel interpolation data Q is output.

Moreover, when the determination in step S1 is NO, the upper and lower pixels,
This is a case where image data "01"8 to "FE" are included in any of the data d. In this case, it is determined that multivalued image data such as a photograph should be generated as the pixel of interest, and the process proceeds to step S5, where the average value Q of the upper and lower pixel data D and d is calculated by numerical calculation.
= (D+d)/2 is generated by interpolation. Similarly, in step S6, multilevel interpolation data Q is output.

As a result of the above, for example, the image data of the alphabet "a" of 300 dpi shown in FIG.
The image data is interpolated with 00 dpi data. This interpolated image data of 600 dpi and 256 gradations is sent to a pulse width modulation circuit to be described later.

FIG. 7 is a block diagram of the pulse width modulation circuit and image recording section of the embodiment. In the figure, 42 is a look-up table (LUT), which performs γ correction conversion on 8-bit image data (VDO') 100 input from the data selector 16, and 32 is a D/A converter, which performs correction. The subsequent image data 101 is converted into an analog image signal 102. On the other hand, 34 is a timing generation circuit, which provides a horizontal synchronization (BD) signal 1 based on the detection output of the beam detector 41.
07 and a timing signal 108 synchronized with a synchronization clock signal 109 based on the BD scratch signal. BD signal 3
5 is a triangular wave generating circuit, which generates a triangular wave signal 105 in accordance with the timing signal 108. A comparator 36 generates a PWM signal 103 in which the density of the image signal 102 is pulse width modulated by comparing the analog image signal 102 and the triangular wave signal 105. Reference numeral 37 denotes a drive circuit, which pulse-drives the semiconductor laser 38 in accordance with the PWM signal 103.

In this way, the laser beam emitted from the semiconductor laser 38 is transmitted to the photosensitive drum 4 by a polygon mirror 39 rotating at high speed.
A latent image of the input image data VDO' is formed on the uniformly charged surface of the photosensitive drum 40 by a so-called rusk scan method. do. The latent image is visualized by a developing means (not shown) and transferred to transfer paper,
A recorded image of dp i/256 gradations is obtained.

FIGS. 8(A) and 8(B) are operation timing charts of the configuration shown in FIG. 7. In FIG. A triangular wave signal 105 is generated in synchronization with the signal 108. The comparator 36 has a triangular wave signal 10
The output (PWM) signal 10 has a logic level in the section where the level of 5 exceeds the level of the analog image signal 102.
form 3. As a result, the PWM signal 1 has a pulse width (halftone) corresponding to the density level of the analog image signal 102.
03 occurs.

In the above-mentioned embodiment, the combination of the printer controller 52 with a print density of 300 dpi and the print engine with a print density of 600 dpi was shown, but the combination is not limited to this. It can also be a combination of engines.

Furthermore, in the above embodiment, the number of dots for data interpolation was explained as one dot, but it is not limited to this. In addition, interpolation of multiple dots, 4th gradation lower than 256 gradation, 8 gradation, 16 gradation, etc.
It is also effective when handling image data of gradations, 64 gradations, 128 gradations, etc.

Further, the print engine section is not limited to a laser beam printer, but may also be an LED printer, an inkjet printer, or the like.

Furthermore, the image recording method may be a brightness modulation method or the like instead of the pulse width modulation method.

[Effects of the Invention] As described above, according to the present invention, sharpness and smoothness of contours can be reproduced in the binary expression part of an image, and density gradation can be reproduced in the halftone expression part of the image. It is possible to provide an image forming device that can reproduce smoothness and has a high quality image with a simple configuration.

[Brief explanation of the drawing]

1 is a block diagram of the image forming apparatus of the embodiment, FIG. 2 is an operation timing chart of the circuit of FIG. 1, FIG. 3 is a block diagram of the interpolation circuit 17 of the embodiment, and FIG. 4 is the embodiment. Figure 5 is a block diagram of the interpolation circuit IO of the embodiment, and Figures 6 (A) and (B) are the embodiments. FIG. 7 is a block diagram of the pulse width modulation circuit and image recording section of the embodiment, and FIGS. Operation timing chart. Figure 9 is a diagram showing the input image data of the alphabet a'' at 300 dpi. Figure 10 is a diagram showing the image data of the alphabet a'' at 600 dpi after interpolation of the output data. Figure 11 is the conventional image data. A conceptual configuration diagram of a laser beam printer system that prints at a printing density of 300dpi.
Figure 13 shows the relationship between printing position on a line and gradation change.
FIG. 3 is a diagram showing the relationship between printing position on a line and gradation change. In the figure, 1... Frequency multiplier circuit, 2... Demultiplexer, 3... Device control circuit, 4... Horizontal synchronization signal generation circuit, 5... Oscillation circuit, 6-9... Lines Memory, 14.15...Data selector, 10°17.
...Interpolation circuit, 11-13...Switching circuit, 16...
It is a data selector.

Claims (2)

[Claims] (1) In an image forming apparatus that inputs image data of a certain print density and forms an image of a higher print density, the image forming apparatus includes a storage means for storing the input image data, and the stored image around the pixel of interest to be interpolated. A determining means for determining whether data belongs to a binary representation image or a multivalued representation image, and generating interpolated data of the pixel of interest using a calculation method defined according to the determination result of the determining means. An image forming apparatus comprising a data interpolation means. (2) The data interpolation means generates interpolated data for the pixel of interest by a binary logical operation when the discrimination result of the discrimination means belongs to an image with a binary expression, and the discrimination result is converted into an image with a multi-value expression. 2. The image forming apparatus according to claim 1, wherein when the pixel of interest belongs, interpolation data of the pixel of interest is generated by numerical calculation.