JPH0797560B2 - 半導体デバイスの製造方法 - Google Patents

半導体デバイスの製造方法

Info

Publication number
JPH0797560B2
JPH0797560B2 JP4412091A JP4412091A JPH0797560B2 JP H0797560 B2 JPH0797560 B2 JP H0797560B2 JP 4412091 A JP4412091 A JP 4412091A JP 4412091 A JP4412091 A JP 4412091A JP H0797560 B2 JPH0797560 B2 JP H0797560B2
Authority
JP
Japan
Prior art keywords
silicon
substrate
layer
forming
thermal oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP4412091A
Other languages
English (en)
Japanese (ja)
Other versions
JPH06204151A (ja
Inventor
ジョエル・ペレアラ・デスーザ
ジェイムズ・ヘンリー・グライナ
デヴェンドラ・クマール・サダナ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH06204151A publication Critical patent/JPH06204151A/ja
Publication of JPH0797560B2 publication Critical patent/JPH0797560B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2258—Diffusion into or out of AIIIBV compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP4412091A 1990-03-02 1991-02-18 半導体デバイスの製造方法 Expired - Lifetime JPH0797560B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US48750190A 1990-03-02 1990-03-02
US487501 1990-03-02

Publications (2)

Publication Number Publication Date
JPH06204151A JPH06204151A (ja) 1994-07-22
JPH0797560B2 true JPH0797560B2 (ja) 1995-10-18

Family

ID=23935981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4412091A Expired - Lifetime JPH0797560B2 (ja) 1990-03-02 1991-02-18 半導体デバイスの製造方法

Country Status (2)

Country Link
EP (1) EP0444465A2 (cg-RX-API-DMAC7.html)
JP (1) JPH0797560B2 (cg-RX-API-DMAC7.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69324630T2 (de) * 1992-06-13 1999-10-21 Sanyo Electric Co., Ltd. Dotierungsverfahren, Halbleiterbauelement und Verfahren zu seiner Herstellung
JP6824829B2 (ja) * 2017-06-15 2021-02-03 株式会社サイオクス 窒化物半導体積層物の製造方法、窒化物半導体自立基板の製造方法および半導体装置の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4830983A (en) 1987-11-05 1989-05-16 Xerox Corporation Method of enhanced introduction of impurity species into a semiconductor structure from a deposited source and application thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0666454B2 (ja) * 1985-04-23 1994-08-24 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション ▲ｉｉｉ▼―▲ｖ▼族半導体デバイス
US4784975A (en) * 1986-10-23 1988-11-15 International Business Machines Corporation Post-oxidation anneal of silicon dioxide

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4830983A (en) 1987-11-05 1989-05-16 Xerox Corporation Method of enhanced introduction of impurity species into a semiconductor structure from a deposited source and application thereof

Also Published As

Publication number Publication date
EP0444465A2 (en) 1991-09-04
EP0444465A3 (cg-RX-API-DMAC7.html) 1994-01-26
JPH06204151A (ja) 1994-07-22

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