JPH0786762B2 - Instruction processing method in programmable controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a processing method for timer instructions, counter instructions, etc. in a programmable controller.

(Prior Art) In a program controller, in order to execute, for example, a timer instruction, three parameters (arguments) of a timer number, an input value, and a set value are required, and the above three parameters are internally set before executing the timer instruction. Work is being done to store it in the parameter stack of. Then, the processing system of the timer instruction performs the processing after reading the above parameter stack and fetching all the parameters.

The processing after the above three parameters are stored in the parameter stack will be described below.

First, the timer instruction includes an on-delay timer, an off-delay timer, a monostable timer, a retriggerable monostable timer, an integration timer, and the like, and the counter instruction includes an up counter, a down counter, an up / down counter, and a ring counter. Although a counter is included, the operation of the on-delay timer will be described here with reference to the time chart of FIG.

The on-delay timer takes in the timer number, input value, and set value as parameters as described above, and the relationship between the input value and output value is the elapsed time after the input value is turned on (hereinafter referred to as the current value). Output value is ON after the value has passed
However, when the input value turns off, the output value turns off immediately. Here, the timer number is used for address calculation such as the address of the output value area and the address of the current value area for storing the current value.

Now, the above current value is updated by adding the deviation (t _{1 to} t _{7 in} FIG. 11) of the value (FRC value) of the counter (hereinafter referred to as free running counter = FRC) that is incremented at a fixed time. However, for this purpose, the FRC value at the time of the previous execution of the timer instruction and the current value until the execution of the previous timer instruction are required for each timer, and a work area is secured in memory. It is necessary to store these FRC values and current values.

On the other hand, in the conventional processing method of the timer instruction or the counter instruction, the timer instruction or the counter instruction is processed by the calculation, comparison, transfer processing and the like of one processor.

FIG. 7 shows the processing procedure of a conventional timer instruction, and the detailed operation will be described below.

In the figure, first, a timer number, an input value, and a set value are stored in the processing system of the programmable controller from the parameter stack (steps A1 to A3). Next, in step A1, the address that stores the FRC value at the time of executing the previous timer instruction corresponding to the timer number is calculated from the timer number that was imported internally (A4), and the FRC previous value is read based on this address ( Same A5).

Next, in step A1, the address that stores the current value at the time of executing the previous timer instruction corresponding to the timer number is calculated from the timer number that was fetched internally (at the same A
6) Read the current value based on this address (same A
7). After that, in step A1, the address that stores the FRC value at the time of executing the previous timer instruction corresponding to the timer number is calculated from the timer number imported internally (at the same A
8) Write the FRC current value to the FRC storage address corresponding to the timer number (at the same A9).

Next, the deviation between the FRC current value and the FRC previous value fetched in step A5 is calculated (A10), and the sum of this deviation and the current value fetched internally in step A7 is calculated to calculate a new current value ( A11).

Further, the address of the output area corresponding to the timer number is calculated from the timer number fetched inside in step A1 (at A12), and the data in the output value area is read based on this address (at A13). Then, the output value is determined from the comparison result of the set value internally fetched at step A3 and the current value calculated at step A11 and the input value internally fetched at step A2, and the output value region internally fetched at step A13. Write to the bit corresponding to the timer number in the internal data (at A14).

Next, from the timer number fetched inside in step A1, the address at which the current value at the time of execution of the previous timer instruction corresponding to the timer number is stored is calculated (at step A15).
Then, the current value calculated in step A11 is written to the current value address (at A16). Further, the address of the output value area corresponding to the timer number is calculated from the timer number loaded inside in step A1 (at step A17), and step A
The data in the output value area rewritten in 14 is written in the output value area (at A18).

(Problems to be Solved by the Invention) As described above, in the conventional method, for example, 18 steps of processing are required to complete one timer instruction,
Similarly, the counter instruction also requires many steps. Therefore, in the past, there was a problem that the instruction processing speed was slow.

Further, as is clear from the example of the on-delay timer described above, three or more parameters are specified for one instruction in the timer instruction or the counter instruction, and the contents of these parameters are the data and constants in the memory or register. , Or the execution result of an instruction, and its content cannot be uniquely determined. Therefore, it is necessary to execute the instruction after fetching the contents of all parameters into the processing system. The fact that an instruction can only be executed after fetching a plurality of parameters in this way also causes a reduction in instruction processing speed, which has become remarkable as the number of parameters increases.

The present invention has been proposed to solve the above problems, and an object of the present invention is to reduce the number of processing steps, or to execute instruction processing by performing parameter fetching and instruction execution in parallel. Made it possible to speed up
It is to provide an instruction processing system in a programmable controller.

(Means for Solving the Problem) In order to achieve the above object, the first invention is a memory access processing means for performing memory access to a data memory storing a plurality of parameters, and a numerical operation based on an instruction. Numerical operation processing means and address calculation processing means for calculating the address of the work area on the data memory are separately provided, and these respective means are operated in parallel to execute the instruction.

According to a second aspect of the present invention, one instruction is distributed to a plurality of sub-instructions, and each sub-instruction is composed of one sub-function forming an instruction body and at least one parameter, and the programmable controller has one parameter. After the fetching, the corresponding sub-function is executed, and other parameters are fetched during this execution period, so that the parameter fetching and the sub-function executing are performed in parallel.

(Operation) According to the first aspect of the invention, a memory access processing means for accessing the data memory, a numerical operation processing means for performing a numerical operation based on an instruction, and an address for calculating an address of a work area on the data memory. By individually providing the calculation processing means and operating the respective means in parallel, it is possible to reduce the total processing steps, and it is possible to speed up the processing of the timer instruction and the counter instruction.

According to the second invention, in the process of converting one instruction into the execution format, the instruction is decomposed into a plurality of sub-instructions including a sub-function and one or more parameters, and the instruction processing means of the programmable controller uses the sub-instruction. After fetching the parameter following one sub-function, the processing of that sub-function is immediately executed, and at the same time, the parameter relating to the next sub-instruction is fetched. This makes it possible to speed up the processing of the timer instruction and the counter instruction by simultaneously fetching the parameters and executing the sub-function.

(Embodiment) An embodiment of the first invention will be described below with reference to the drawings. FIG. 1 shows the configuration of this embodiment. In FIG.
0 is a numerical calculation processing means for performing numerical calculation based on an instruction, 200
Is an address calculation processing means for calculating the address of the work area, 300 is a control processing means for performing the memory access processing and controlling the numerical operation processing means 100 and the address calculation processing means 200, and 400 is a data memory.

Here, the numerical calculation processing means 100, RFC previous value, current value,
Internal registers 101 to 105 that store set values, input values, and output value data, and a free-running counter (FR
C) 106, FRC previous value of internal register 101 and FR of FRC106
A subtractor 107 to which the C value is input, an internal register 110 that stores the deviation of the FRC value calculated by this subtractor 107,
It comprises an adder 108 to which the deviation and the current value of the internal register 102 are input, and a comparator 109 to which the current value, set value, input value and output value data are input.

In addition, the address calculation processing means 200 is a timer number, FRC.
Internal registers 201 to 204 that store the previous value storage start address, current value storage start address, and output value storage start address, and the FRC previous value storage start address, current value storage start address, and output value storage start address are input. Selector 205 and an adder 206 to which the output of the selector 205 and the timer number of the internal register 201 are input.

Further, the control processing means 300, the numerical operation processing means 100,
A sequential parallel processing control unit 301 for sequentially controlling the parallel operation of the address calculation processing unit 200 and a memory access control unit 302 described later, and a data memory 4.
The data memory 400 includes a memory access control unit 302 for controlling read / write of 00, and the data memory 400 is a parameter stack in which a timer number, an input value and a set value are stored.
401, FRC previous value area 402, current value area 403, and output value area 404.

In FIG. 1, reference numeral 501 indicates a data bus, and 502 indicates an address bus.

Thus, in this embodiment, the processing procedure shown in FIG.
It is intended to speed up the processing of the timer instruction and the counter instruction by realizing the parallel operation of the numerical operation processing system, the address calculation processing system and the memory access processing system.

FIG. 2 shows the processing procedure of the timer instruction in this embodiment. In FIG. 2, P is the processing procedure of the memory access processing system, P'is the processing procedure of the address calculation processing system, and P'is the numerical operation. The processing procedures of the processing system are shown respectively.

Explaining these processes over time, first, the timer number is read from the parameter stack 401 and stored in the internal register 201 (step B1). Next, the input value is read from the parameter stack 401 and stored in the internal register 104 (at the same B2).

Further, from the timer number in the internal register 201 and the FRC previous value storage start address stored in the internal register 202, the FRC value at the time of executing the previous timer instruction corresponding to the timer number is calculated using the adder 206 via the selector 205. The stored address is calculated (at the same B2 '). Based on this address, the FRC previous value is read and stored in the internal register 101 (at the same B3).

Next, from the timer number stored in the internal register 201 and the current value storage start address stored in the internal register 203, the current when the previous timer instruction corresponding to the timer number is executed using the adder 206 via the selector 205. The address where the value is stored is calculated (at the same B3 '). The current value is read based on this address and the internal register
Stored in 102 (same B4).

Further, from the timer number stored in the internal register 201 and the FRC previous value storage start address stored in the internal register 202, the adder 206 is used via the selector 205 to execute the previous timer instruction corresponding to the timer number. FRC
The address where the value is stored is calculated (at the same B4 '). Also,
FRC previous value stored in internal register 101 and FRC106
Of the FRC value from the previous timer instruction execution using the subtractor 107 and stores the deviation in the internal register 110 (Same as B4 ″). It represents the elapsed time from the execution of the instruction to the execution of the current timer instruction.

Based on the address calculated in step B4 ′ above, FRC1
Write the FRC value of 06 to the FRC value storage address corresponding to the timer number as the current value (at the same B5). Then, from the deviation of the FRC stored in the internal register 110 (elapsed time from the execution of the previous timer instruction) and the current value stored in the internal register 102 at the execution of the previous timer instruction, the adder 10
A new current value is calculated using 8 and stored in the internal register 102 (B5 ″).

Next, read the setting value from the parameter stack 401,
It is stored in the internal register 103 (at the same B6). Then, the output value storage address corresponding to the timer number is calculated from the timer number stored in the internal register 201 and the output value storage start address stored in the internal register 204 using the adder 206 via the selector 205. (Same as B6 ').
Based on this address, the output area data corresponding to the timer number is read and stored in the internal register 105 (at the same B7).

Further, from the timer number stored in the internal register 201 and the current value storage start address stored in the internal register 203, the current value at the time of execution of the current timer instruction corresponding to the timer number using the adder 206 via the selector 205. The address where the value is stored is calculated (at the same B7 '). Based on this address, the current value of the internal register 102 is written to the current value storage address corresponding to the timer number (at the same B
8).

Then, the output value storage address corresponding to the timer number is calculated from the timer number stored in the internal register 201 and the output value storage start address stored in the internal register 204 using the adder 206 via the selector 205. (Same B8 '). Also, the output value is determined by the comparator 109 from the comparison result between the new current value of the internal register 102 and the set value of the internal register 103, and the input value of the internal register 104. Of the output value area address of the internal register 105 is written to the output value area address corresponding to the timer number (same as B8 ″). B9).

As described above, even in this embodiment, the processing items are the same as the conventional 18 items, but since memory access, numerical operation, and address calculation can be performed in the same step, the number of steps until the timer instruction is completed is It will be completed in 9 steps. Therefore, the time required for timer instruction processing can be reduced by half as compared with the conventional method, and the timer instruction processing can be executed at twice the speed of the conventional method.

Next, FIGS. 3 to 5 show an embodiment of the second invention. According to the present invention, one timer instruction or counter instruction is further decomposed into a plurality of sub instructions, and the number of parameters is 1
By defining one sub-function that constitutes the instruction body for one or two, the corresponding sub-function is executed immediately after incorporating one or two parameters inside the processing system, and It is intended for speeding up.

That is, for example, as shown in FIG.
But the function F "TiM" constituting the instruction body, Taimananba as an operand, if it is composed of three parameters P ₁ to P ₃ Metropolitan consisting input value and the set value, the timer instruction C subfunctions SF ₁ “TiMO” and timer number parameter P ₁ , sub-function SF ₂ “TiM
1 "and input value parameter P ₂ , subfunction SF ₃ “ T
It is decomposed into a set of iM2 "and the parameter P ₃ of the set value, and each is set as subinstructions C ₁ , C ₂ , and C ₃ .

The sub-instructions C _{1 to} C ₃ are, in the sub-instruction C ₁ , read the timer number (take in the operand), calculate the current value area address, and calculate the current value read output value area address in the order of sub-instruction C ₁ , as will be described later. in performs processing for the sub-instruction C _2, 'input value of the read (uptake operand)' input value "0" or "1" Kano determination 'input value "0" when the current value " 0 ", and" when the 1 "performs a process of updating the current value, also, for sub-instruction C ₃ is
"Read set value (capture of operand)""Comparison between current value and set value" Processing is performed in the order of setting output values.

FIG. 4 shows a hardware configuration to which this embodiment is applied. In the figure, reference numeral 600 denotes a program memory, and the program memory 600 stores the sub-instructions C _{1 to} C ₃ defined for each parameter. In addition,
In this embodiment, each parameter indicates the address of the data memory 400 'where these data are stored. In addition to the timer number, the input value and the set value, the current value, the output value and the like are stored in the data memory 400 'as in the first invention.

700 is an instruction processing means, and this instruction processing means 700
A memory management unit 710 to read or write data on the data memory 400 ', the sub-instruction includes independently and instruction execution means 720 for executing the (subfunctions), each sub-instruction C ₁ -C Memory read / write such as fetching parameter contents for each ₃ and each sub instruction C ₁ ~
It is configured so that the execution of C ₃ subfunctions SF _{1 to} SF ₃ can be processed in parallel.

The memory management means 710 includes an internal register 711 for storing a timer number, an input value, a set value and a current value, an internal register 712 for storing a current value area address and an output value area address, and an instruction executing means 720. Is an address generator that receives the timer number and generates each address.
721 and the input value determination unit 7 that determines whether the input value is “0” or “1”
22 and a comparator 723 that generates an output value by comparing the current value and the set value.

Then, in this embodiment, as soon as the parameter of one sub-instruction is fetched, the sub-function relating to this sub-instruction is executed, and during this period, the parameter of the next sub-instruction is fetched in parallel. That is, as shown in FIG. 5, in the sub-function “TiM0”, the timer number is read from the data memory 400 ′ to the internal register 711 (FIG. 5), and the address generator 721 generates the current value area address to generate the internal register. At the stage of storing in 712 (same), the input value is read from the data memory 400 'to the internal register 711 in the sub-function "TiM" 1 (same'). On the other hand, in the sub-function "TiM0", the current value is read from the data memory 400 'to the internal register 711 (same), and at the same time, in the sub-function "TiM1", the input value is determined by the input value determination unit 722 (same'). .

Further, in the sub-function "TiM0", the output value area address is generated by the address generation unit 721 and stored in the internal register 712 (same), and at this time, in the sub-function "TiM2" from the data memory 400 'to the internal register 711. Read the set value. While the sub-function "TiM1" is performing the current value change process (same as above) according to the input value, the sub-function "TiM1"
In M2 ", the comparator 723 compares the current value with the set value (same"), and then outputs the output value to the data memory 40.
It is set to 0 '(same as above).

As described above, in this embodiment, the fetch of the operand of each sub-instruction and the execution of the sub-function are performed in parallel, so that the execution time of the timer instruction can be shortened as a whole.

Although only the processing of the timer instruction has been described in the above embodiments of the invention, any of the inventions can be applied to the processing of the counter instruction.

(Effect of the Invention) As described above, according to the first invention, a numerical operation processing system,
An address calculation processing system and a memory access processing system are operated in parallel, and according to the second invention, one instruction is decomposed into a plurality of sub-instructions for each parameter, and a sub-function related to a certain sub-instruction. Is executed in parallel with the execution of parameters and the acquisition of parameters for other sub-instructions, so that there is an effect that the instruction processing speed can be increased by shortening the overall instruction execution time.

[Brief description of drawings]

1 and 2 show an embodiment of the first invention, FIG. 1 is a block diagram of hardware used in this embodiment, and FIG. 2 shows an instruction processing procedure in this embodiment. A flow chart, FIGS. 3 to 5 show an embodiment of the second invention, FIG. 3 is an explanatory view of a method of disassembling a timer instruction, and FIG. 4 is a block diagram of hardware used in this embodiment. , FIG. 5 is a diagram showing the processing contents of each sub-function, FIGS. 6 and 7 are for explaining a conventional technique, FIG. 6 is an operation explanatory diagram of an on-delay timer, and FIG. It is a flowchart which shows the process sequence of a timer instruction. 100 ... Numerical calculation processing means, 101 to 105,110,201 to 204,711,712 ... Internal register 106 ... Free running counter 107 ... Subtractor, 108,206 ... Adder 109,723 ... Comparator 200 ... Address calculation processing means 205 ... Selector, 300 ... Control processing unit 301 ... Sequential parallel processing control unit 302 ... Memory access control unit 400, 400 '... Data memory 401 ... Parameter stack 402 ... FRC previous value area, 403 ... Current value area 404 ... Output Value area 501 501 Data bus 502 Address bus 600 Program memory 700 Instruction processing means 710 Memory management means 720 Instruction execution means 721 Address generator 722 Input value Judgment part

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-59-223804 (JP, A) JP-A-63-136201 (JP, A) JP-A-55-33231 (JP, A)

Claims (2)

[Claims] 1. In a programmable controller which fetches a plurality of parameters inside and executes an instruction, a memory access processing means for making a memory access to a data memory in which the parameter is stored, and a numerical value for performing a numerical operation based on the instruction. A programmable controller characterized in that arithmetic processing means and address calculation processing means for calculating an address of a work area on the data memory are individually provided, and each of these means is operated in parallel to execute the instruction. Instruction processing method. 2. A programmable controller that fetches a plurality of parameters inside and executes an instruction, decomposes one instruction into a plurality of sub-instructions, and each sub-instruction is one sub-function forming an instruction body and at least one sub-instruction. And a parameter, wherein the programmable controller fetches one parameter, executes the corresponding sub-function, and fetches another parameter during this execution period.